SPRSP35 Data sheet

6.9.5.19.2 MMC1/2 - SD/SDIO Interface

MMC1 and MMC2 interfaces are compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01 as well as SDIO Specification v3.00 and they support the following SD Card applications:

Default speed
High speed
UHS–I SDR12
UHS–I SDR25
UHS–I SDR50
UHS–I SDR104
UHS–I DDR50

Table 6-78 presents the required DLL software configuration settings for MMC1 timing modes.

Table 6-78 MMC1/2 DLL Delay Mapping for All Timing Modes

REGISTER NAME		MMCSD12_SS_PHY_CTRL_4_REG				MMCSD12_SS_PHY_CTRL_5_REG
BIT FIELD		[20]	[15:12]	[8]	[4:0]	[2:0]
BIT FIELD NAME		OTAPDLYENA	OTAPDLYSEL	ITAPDLYENA	ITAPDLYSEL	CLKBUFSEL
MODE	DESCRIPTION	DELAY ENABLE	DELAY VALUE	INPUT DELAY ENABLE	INPUT DELAY VALUE	DELAY BUFFER DURATION
Default Speed	4-bit PHY operating 3.3 V, 25 MHz	0x1	0x1	0x0	0x0	0x7
High Speed	4-bit PHY operating 3.3 V, 50 MHz	0x1	0x1	0x0	0x0	0x7
UHS-I SDR12	4-bit PHY operating 1.8 V, 25 MHz	0x1	0xF	0x0	0x0	0x7
UHS-I SDR25	4-bit PHY operating 1.8 V, 50 MHz	0x1	0xF	0x0	0x0	0x7
UHS-I SDR50	4-bit PHY operating 1.8 V, 100 MHz	0x1	0xC	0x1	Tuning	0x7
UHS-I DR50	4-bit PHY operating 1.8 V, 50 MHz	0x1	0xC	0x1	0x2	0x7
UHS-I SDR104	4-bit PHY operating 1.8, V 200 MHz	0x1	0x5	0x1	Tuning	0x7

Table 6-79 presents timing conditions for MMC1.

Table 6-79 MMC1/2 Timing Conditions

PARAMETER			MIN	MAX	UNIT
INPUT CONDITIONS
SR_I	Input slew rate	Default Speed, High Speed	0.69	2.06	V/ns
SR_I	Input slew rate	UHS–I SDR12, UHS–I SDR25	0.34	1.34	V/ns
OUTPUT CONDITIONS
C_L	Output load capacitance	All modes	1	10	pF
PCB CONNECTIVITY REQUIREMENTS
t_{d(Trace Delay)}	Propagation delay of each trace	UHS–I DDR50	240	1134	ps
t_{d(Trace Delay)}	Propagation delay of each trace	All other modes	126	1386	ps
t_{d(Trace Mismatch Delay)}	Propagation delay mismatch across all traces	UHS–I DDR50, UHS–I SDR104		20	ps
t_{d(Trace Mismatch Delay)}	Propagation delay mismatch across all traces	All other modes		100	ps