SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
Table 6-34, Section 6.9.5.3.2.1, Section 6.9.5.3.2.2, and Section 6.9.5.3.2.3 present timing conditions, requirements, and switching characteristics for CPSW2G RMII.
PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
INPUT CONDITIONS | |||||
SRI | Input signal slew rate | VDDSHVx(1) = 1.8V | 0.2 | 0.54 | V/ns |
VDDSHVx(1) = 3.3V | 0.8 | 1.2 | V/ns | ||
OUTPUT CONDITIONS | |||||
CL | Output load capacitance | 3 | 25 | pF |