SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
MODE | OSPI_PHY_CONFIGURATION_REG BIT FIELD | DELAY VALUE | |
---|---|---|---|
OSPI0 | OSPI1 | ||
Transmit | |||
1.8V | PHY_CONFIG_TX_DLL_DELAY_FLD | 0x40 | 0x41 |
3.3V | PHY_CONFIG_TX_DLL_DELAY_FLD | 0x3C | 0x3E |
Receive | |||
1.8V, DQS | PHY_CONFIG_RX_DLL_DELAY_FLD | 0x13 | 0x15 |
3.3V, DQS | PHY_CONFIG_RX_DLL_DELAY_FLD | 0x1E | 0x1E |
All other modes | PHY_CONFIG_RX_DLL_DELAY_FLD | 0x0 | 0x0 |
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
O15 | tsu(D-LBCLK) | Setup time, D[i:0] valid before active LBCLK (DQS) edge(1) | 1.8V, External Board Loopback | 0.52 | ns | |
3.3V, External Board Loopback | 1.97 | ns | ||||
O16 | th(LBCLK-D) | Hold time, D[i:0] valid after active LBCLK (DQS) edge(1) | 1.8V, External Board Loopback | 1.24 (3) | ns | |
3.3V, External Board Loopback | 1.44 (3) | ns | ||||
O17 | tsu(D-DQS) | Setup time, DQS edge to D[i:0] transition(1) | 1.8V, DQS | -0.46 | ns | |
3.3V, DQS | -0.66 | ns | ||||
O18 | th(DQS-D) | Hold time, DQS edge to D[i:0] transition(1) | 1.8V, DQS | 3.59 | ns | |
3.3V, DQS | 8.89 | ns |