SPRSP35K
February 2019 – April 2024
DRA829J
,
DRA829J-Q1
,
DRA829V
,
DRA829V-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
3.1
Functional Block Diagram
4
Device Comparison
4.1
Related Products
5
Terminal Configuration and Functions
5.1
Pin Diagram
5.2
Pin Attributes
5.3
Signal Descriptions
5.3.1
ADC
5.3.1.1
MCU Domain
5.3.2
DDRSS
5.3.2.1
MAIN Domain
5.3.3
GPIO
5.3.3.1
MAIN Domain
5.3.3.2
WKUP Domain
5.3.4
I2C
5.3.4.1
MAIN Domain
5.3.4.2
MCU Domain
5.3.4.3
WKUP Domain
5.3.5
I3C
5.3.5.1
MAIN Domain
5.3.5.2
MCU Domain
5.3.6
MCAN
5.3.6.1
MAIN Domain
5.3.6.2
MCU Domain
5.3.7
MCSPI
5.3.7.1
MAIN Domain
5.3.7.2
MCU Domain
5.3.8
UART
5.3.8.1
MAIN Domain
5.3.8.2
MCU Domain
5.3.8.3
WKUP Domain
5.3.9
MDIO
5.3.9.1
MCU Domain
5.3.10
CPSW2G
5.3.10.1
MCU Domain
5.3.11
CPSW9G
5.3.11.1
MAIN Domain
5.3.12
ECAP
5.3.12.1
MAIN Domain
5.3.13
EQEP
5.3.13.1
MAIN Domain
5.3.14
EHRPWM
5.3.14.1
MAIN Domain
5.3.15
USB
5.3.15.1
MAIN Domain
5.3.16
SERDES
5.3.16.1
MAIN Domain
5.3.17
OSPI
5.3.17.1
MCU Domain
5.3.18
Hyperbus
5.3.18.1
MCU Domain
5.3.19
GPMC
5.3.19.1
MAIN Domain
5.3.20
MMC
5.3.20.1
MAIN Domain
5.3.21
CPTS
5.3.21.1
MCU Domain
5.3.21.2
MAIN Domain
5.3.22
UFS
5.3.22.1
MAIN Domain
5.3.23
PRU_ICSSG [Currently Not Supported]
5.3.23.1
MAIN Domain
5.3.24
MCASP
5.3.24.1
MAIN Domain
5.3.25
DSS
5.3.25.1
MAIN Domain
5.3.26
DP
5.3.26.1
MAIN Domain
5.3.27
Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem
5.3.27.1
MAIN Domain
5.3.28
DSI_TX
5.3.28.1
MAIN Domain
5.3.29
VPFE
5.3.29.1
MAIN Domain
5.3.30
DMTIMER
5.3.30.1
MAIN Domain
5.3.30.2
MCU Domain
5.3.31
Emulation and Debug
5.3.31.1
MAIN Domain
5.3.32
System and Miscellaneous
5.3.32.1
Boot Mode Configuration
5.3.32.1.1
MAIN Domain
5.3.32.1.2
MCU Domain
5.3.32.2
Clock
5.3.32.2.1
MAIN Domain
5.3.32.2.2
WKUP Domain
5.3.32.3
System
5.3.32.3.1
MAIN Domain
5.3.32.3.2
WKUP Domain
5.3.32.4
EFUSE
5.3.33
Power Supply
5.4
Pin Multiplexing
5.5
Pin Connectivity Requirements
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Power-On-Hour (POH) Limits
6.4
Recommended Operating Conditions
6.5
Operating Performance Points
6.6
Electrical Characteristics
6.6.1
I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
6.6.2
Fail-Safe Reset (FS Reset) Electrical Characteristics
6.6.3
HFOSC/LFOSC Electrical Characteristics
6.6.4
eMMCPHY Electrical Characteristics
6.6.5
SDIO Electrical Characteristics
6.6.6
CSI-2/DSI D-PHY Electrical Characteristics
6.6.7
ADC12B Electrical Characteristics
6.6.8
MLB LVCMOS Electrical Characteristics
6.6.9
LVCMOS Electrical Characteristics
6.6.10
USB2PHY Electrical Characteristics
6.6.11
SerDes 4-L-PHY/2-L-PHY Electrical Characteristics
6.6.12
UFS M-PHY Electrical Characteristics
6.6.13
eDP/DP AUX-PHY Electrical Characteristics
6.6.14
DDR0 Electrical Characteristics
6.7
VPP Specifications for One-Time Programmable (OTP) eFuses
6.7.1
Recommended Operating Conditions for OTP eFuse Programming
6.7.2
Hardware Requirements
6.7.3
Programming Sequence
6.7.4
Impact to Your Hardware Warranty
6.8
Thermal Resistance Characteristics
6.8.1
Thermal Resistance Characteristics for ALF Package
6.9
Timing and Switching Characteristics
6.9.1
Timing Parameters and Information
6.9.2
Power Supply Sequencing
6.9.2.1
Power Supply Slew Rate Requirement
6.9.2.2
Combined MCU and Main Domains Power-Up Sequencing
6.9.2.3
Combined MCU and Main Domains Power- Down Sequencing
6.9.2.4
Isolated MCU and Main Domains Power- Up Sequencing
6.9.2.5
Isolated MCU and Main Domains, Primary Power- Down Sequencing
6.9.2.6
Entry and Exit of MCU Only State
6.9.2.7
Entry and Exit of DDR Retention State
6.9.3
System Timing
6.9.3.1
Reset Timing
6.9.3.2
Safety Signal Timing
6.9.3.3
Clock Timing
6.9.4
Clock Specifications
6.9.4.1
Input and Output Clocks / Oscillators
6.9.4.1.1
WKUP_OSC0 Internal Oscillator Clock Source
6.9.4.1.1.1
Load Capacitance
6.9.4.1.1.2
Shunt Capacitance
6.9.4.1.2
WKUP_OSC0 LVCMOS Digital Clock Source
6.9.4.1.3
Auxiliary OSC1 Internal Oscillator Clock Source
6.9.4.1.3.1
Load Capacitance
6.9.4.1.3.2
Shunt Capacitance
6.9.4.1.4
Auxiliary OSC1 LVCMOS Digital Clock Source
6.9.4.1.5
Auxiliary OSC1 Not Used
6.9.4.1.6
WKUP_LFOSC0 Internal Oscillator Clock Source
6.9.4.1.6.1
WKUP_LFOSC0 Not Used
6.9.4.2
Output Clocks
6.9.4.3
PLLs
6.9.4.4
Module and Peripheral Clocks Frequencies
6.9.5
Peripherals
6.9.5.1
ATL
6.9.5.1.1
ATL_PCLK Timing Requirements
6.9.5.1.2
ATL_AWS[x] Timing Requirements
6.9.5.1.3
ATL_BWS[x] Timing Requirements
6.9.5.1.4
ATCLK[x] Switching Characteristics
6.9.5.2
VPFE
6.9.5.3
CPSW2G
6.9.5.3.1
CPSW2G MDIO Interface Timings
6.9.5.3.2
CPSW2G RMII Timings
6.9.5.3.2.1
CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
6.9.5.3.2.2
CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
6.9.5.3.2.3
CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
6.9.5.3.3
CPSW2G RGMII Timings
6.9.5.3.3.1
RGMII[x]_RXC Timing Requirements – RGMII Mode
6.9.5.3.3.2
CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
6.9.5.3.3.3
CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
6.9.5.3.3.4
RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
6.9.5.4
CPSW9G
6.9.5.4.1
CPSW9G MDIO Interface Timings
6.9.5.4.2
CPSW9G RMII Timings
6.9.5.4.2.1
RMII[x]_REF_CLK Timing Requirements – RMII Mode
6.9.5.4.2.2
RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
6.9.5.4.2.3
RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics – RMII Mode
6.9.5.4.3
CPSW9G RGMII Timings
6.9.5.4.3.1
RGMII[x]_RXC Timing Requirements – RGMII Mode
6.9.5.4.3.2
RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode
6.9.5.4.3.3
RGMII[x]_TXC Switching Characteristics – RGMII Mode
6.9.5.4.3.4
RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
6.9.5.5
CSI-2
6.9.5.6
DDRSS
6.9.5.7
DSS
6.9.5.8
eCAP
6.9.5.8.1
Timing Requirements for eCAP
6.9.5.8.2
Switching Characteristics for eCAP
6.9.5.9
EPWM
6.9.5.9.1
Timing Requirements for eHRPWM
6.9.5.9.2
Switching Characteristics for eHRPWM
6.9.5.10
eQEP
6.9.5.10.1
Timing Requirements for eQEP
6.9.5.10.2
Switching Characteristics for eQEP
6.9.5.11
GPIO
6.9.5.11.1
GPIO Timing Requirements
6.9.5.11.2
GPIO Switching Characteristics
6.9.5.12
GPMC
6.9.5.12.1
GPMC and NOR Flash — Synchronous Mode
6.9.5.12.1.1
GPMC and NOR Flash Timing Requirements — Synchronous Mode
6.9.5.12.1.2
GPMC and NOR Flash Switching Characteristics – Synchronous Mode
6.9.5.12.2
GPMC and NOR Flash — Asynchronous Mode
6.9.5.12.2.1
GPMC and NOR Flash Timing Requirements – Asynchronous Mode
6.9.5.12.2.2
GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
6.9.5.12.3
GPMC and NAND Flash — Asynchronous Mode
6.9.5.12.3.1
GPMC and NAND Flash Timing Requirements – Asynchronous Mode
6.9.5.12.3.2
GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
6.9.5.12.4
GPMC0 IOSET
6.9.5.13
HyperBus
6.9.5.13.1
Timing Requirements for HyperBus
6.9.5.13.2
HyperBus 166 MHz Switching Characteristics
6.9.5.13.3
HyperBus 100 MHz Switching Characteristics
6.9.5.14
I2C
6.9.5.15
I3C
6.9.5.16
MCAN
6.9.5.17
MCASP
6.9.5.18
MCSPI
6.9.5.18.1
MCSPI — Master Mode
6.9.5.18.2
MCSPI — Slave Mode
6.9.5.19
MMCSD
6.9.5.19.1
MMC0 - eMMC Interface
6.9.5.19.1.1
Legacy SDR Mode
6.9.5.19.1.2
High Speed SDR Mode
6.9.5.19.1.3
High Speed DDR Mode
6.9.5.19.1.4
HS200 Mode
6.9.5.19.2
MMC1/2 - SD/SDIO Interface
6.9.5.19.2.1
Default Speed Mode
6.9.5.19.2.2
High Speed Mode
6.9.5.19.2.3
UHS–I SDR12 Mode
6.9.5.19.2.4
UHS–I SDR25 Mode
6.9.5.19.2.5
UHS–I SDR50 Mode
6.9.5.19.2.6
UHS–I DDR50 Mode
6.9.5.19.2.7
UHS–I SDR104 Mode
6.9.5.20
CPTS
6.9.5.20.1
CPTS Timing Requirements
6.9.5.20.2
CPTS Switching Characteristics
6.9.5.21
OSPI
6.9.5.21.1
OSPI PHY Mode
6.9.5.21.1.1
OSPI With Data Training
6.9.5.21.1.1.1
OSPI Switching Characteristics – Data Training
6.9.5.21.1.2
OSPI Without Data Training
6.9.5.21.1.2.1
OSPI Timing Requirements – SDR Mode
6.9.5.21.1.2.2
OSPI Switching Characteristics – SDR Mode
6.9.5.21.1.2.3
OSPI Timing Requirements – DDR Mode
6.9.5.21.1.2.4
OSPI Switching Characteristics – DDR Mode
6.9.5.21.2
OSPI Tap Mode
6.9.5.21.2.1
OSPI Tap SDR Timing
6.9.5.21.2.2
OSPI Tap DDR Timing
6.9.5.22
PCIE
6.9.5.23
Timers
6.9.5.23.1
Timing Requirements for Timers
6.9.5.23.2
Switching Characteristics for Timers
6.9.5.24
UART
6.9.5.24.1
Timing Requirements for UART
6.9.5.24.2
UART Switching Characteristics
6.9.5.25
USB
6.9.6
Emulation and Debug
6.9.6.1
Trace
6.9.6.2
JTAG
6.9.6.2.1
JTAG Electrical Data and Timing
6.9.6.2.1.1
JTAG Timing Requirements
6.9.6.2.1.2
JTAG Switching Characteristics
7
Detailed Description
7.1
Overview
7.2
Processor Subsystems
7.2.1
Arm Cortex-A72
7.2.2
Arm Cortex-R5F
7.2.3
DSP C71x
7.2.4
DSP C66x
7.3
Accelerators and Coprocessors
7.3.1
GPU
7.3.2
D5520MP2
7.3.3
VXE384MP2
7.4
Other Subsystems
7.4.1
MSMC
7.4.2
NAVSS
7.4.2.1
NAVSS0
7.4.2.2
MCU_NAVSS
7.4.3
PDMA Controller
7.4.4
Power Supply
7.4.5
Peripherals
7.4.5.1
ADC
7.4.5.2
ATL
7.4.5.3
CSI
7.4.5.3.1
Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
7.4.5.3.2
Camera Streaming Interface Transmitter (CSI_TX_IF)
7.4.5.4
CPSW2G
7.4.5.5
CPSW9G
7.4.5.6
DCC
7.4.5.7
DDRSS
7.4.5.8
DSS
7.4.5.8.1
DSI
7.4.5.8.2
eDP
7.4.5.9
VPFE
7.4.5.10
eCAP
7.4.5.11
EPWM
7.4.5.12
ELM
7.4.5.13
ESM
7.4.5.14
eQEP
7.4.5.15
GPIO
7.4.5.16
GPMC
7.4.5.17
Hyperbus
7.4.5.18
I2C
7.4.5.19
I3C
7.4.5.20
MCAN
7.4.5.21
MCASP
7.4.5.22
MCRC Controller
7.4.5.23
MCSPI
7.4.5.24
MMC/SD
7.4.5.25
OSPI
7.4.5.26
PCIE
7.4.5.27
SerDes
7.4.5.28
WWDT
7.4.5.29
Timers
7.4.5.30
UART
7.4.5.31
USB
7.4.5.32
UFS
8
Applications and Implementation
8.1
Power Supply Mapping
8.2
Device Connection and Layout Fundamentals
8.2.1
Power Supply Decoupling and Bulk Capacitors
8.2.1.1
Power Distribution Network Implementation Guidance
8.2.2
External Oscillator
8.2.3
JTAG and EMU
8.2.4
Reset
8.2.5
Unused Pins
8.2.6
Hardware Design Guide for JacintoTM 7 Devices
8.3
Peripheral- and Interface-Specific Design Information
8.3.1
LPDDR4 Board Design and Layout Guidelines
8.3.2
OSPI and QSPI Board Design and Layout Guidelines
8.3.2.1
No Loopback and Internal Pad Loopback
8.3.2.2
External Board Loopback
8.3.2.3
DQS (only available in Octal Flash devices)
8.3.3
SERDES REFCLK Design Guidelines
8.3.4
USB VBUS Design Guidelines
8.3.5
System Power Supply Monitor Design Guidelines
8.3.6
High Speed Differential Signal Routing Guidance
8.3.7
Thermal Solution Guidance
9
Device and Documentation Support
9.1
Device Nomenclature
9.1.1
Standard Package Symbolization
9.1.2
Device Naming Convention
9.2
Tools and Software
9.3
Documentation Support
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
11.1
Packaging Information
6.9.5.21.1.1.1
OSPI Switching Characteristics – Data Training
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
t
c(CLK)
Cycle time, CLK
DDR, 1.8V
6
ns
DDR, 3.3V
7.5
ns
t
c(CLK)
Cycle time, CLK
SDR, 1.8V
6
ns
SDR, 3.3V
7.5
ns