SPRSP35K February 2019 – April 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1
PRODUCTION DATA
Table 4-1 shows the features of the SoC, highlighting the differences.
FEATURES(6) | REFERENCE NAME | DRA829JM | DRA829VM |
---|---|---|---|
Features | |||
PROCESSORS AND ACCELERATORS | |||
Speed Grades | T | T | |
Arm Cortex-A72 Microprocessor Subsystem | Arm A72 | Dual Core | Dual Core |
Arm Cortex-R5F | Arm R5F | Hexa Core | Hexa Core |
Lockstep | Optional(1) | Optional(1) | |
Device Management Security Controller | DMSC | Yes | Yes |
C7x Floating Point, Vector DSP | C7x DSP | Yes | No |
Deep Learning Accelerator | MMA | Yes | No |
Two C66x Floating Point DSP | C66x DSP | Dual Core | No |
Graphics Accelerator 3D GPU PowerVR Rogue 8XE GE8430 | GPU | Yes | No |
Depth and Motion Processing Accelerators | DMPAC | No | No |
Vision Processing Accelerators | VPAC | No | No |
Security Accelerators | SA | Yes | Yes |
Video Encoder / Decoder | VENC/ VDEC | Yes | No |
SAFETY AND SECURITY | |||
Safety Targeted | Safety | Optional(1) | Optional(1) |
Device Security | Security | Optional(2) | Optional(2) |
AEC-Q100 Qualified | Q1 | Optional(3) | Optional(3) |
PROGRAM AND DATA STORAGE | |||
On-Chip Shared Memory (RAM) in MAIN Domain | OCSRAM | 512KB SRAM | 512KB SRAM |
On-Chip Shared Memory (RAM) in MCU Domain | MCU_MSRAM | 1MB SRAM | 1MB SRAM |
Multicore Shared Memory Controller | MSMC | 8MB (On-Chip SRAM with ECC) | 8MB (On-Chip SRAM with ECC) |
LPDDR4 DDR Subsystem | DDRSS | Up to 8GB (32-bit data) with inline ECC | Up to 8GB (32-bit data) with inline ECC |
SECDED | 7-Bit | 7-Bit | |
General-Purpose Memory Controller | GPMC | Up to 1GB with ECC | Up to 1GB with ECC |
PERIPHERALS | |||
Display Subsystem | DSS | Yes | Yes |
Modular Controller Area Network Interface with Full CAN-FD Support | MCAN | 16 | 16 |
General-Purpose I/O | GPIO | Up to 226 | Up to 226 |
Inter-Integrated Circuit Interface | I2C | 10 | 10 |
Improved Inter-Integrated Circuit Interface | I3C | 3 | 3 |
Analog-to-Digital Converter | ADC | 2 | 2 |
Capture Subsystem with Camera Serial Interface (CSI2) | CSI2.0 4L RX | 2 | 2 |
CSI2.0 4L TX | 1 | 1 | |
Multichannel Serial Peripheral Interface | MCSPI | 11 | 11 |
Multichannel Audio Serial Port | MCASP0 | 16 Serializers | 16 Serializers |
MCASP1 | 12 Serializers | 12 Serializers | |
MCASP2 | 6 Serializers | 6 Serializers | |
MCASP3 | 4 Serializers | 4 Serializers | |
MCASP4 | 4 Serializers | 4 Serializers | |
MCASP5 | 4 Serializers | 4 Serializers | |
MCASP6 | 4 Serializers | 4 Serializers | |
MCASP7 | 4 Serializers | 4 Serializers | |
MCASP8 | 4 Serializers | 4 Serializers | |
MCASP9 | 4 Serializers | 4 Serializers | |
MCASP10 | 8 Serializers | 8 Serializers | |
MCASP11 | 8 Serializers | 8 Serializers | |
MultiMedia Card/ Secure Digital Interface | MMCSD0 | eMMC (8-bits) | eMMC (8-bits) |
MMCSD1 | SD/SDIO (4-bits) | SD/SDIO (4-bits) | |
MMCSD2 | SD/SDIO (4-bits) | SD/SDIO (4-bits) | |
Universal Flash Storage | UFS 2L | Yes (2 Lanes) | Yes (2 Lanes) |
Flash Subsystem (FSS) | OSPI0 | 8-bits(5) | 8-bits(5) |
OSPI1(7) | 4-bits | 4-bits | |
HyperBus | Yes(5) | Yes(5) | |
4x PCI Express Port with Integrated PHY | PCIE0 | Up to Two Lanes(4) | Up to Two Lanes(4) |
PCIE1 | Up to Two Lanes(4) | Up to Two Lanes(4) | |
PCIE2 | Up to Two Lanes(4) | Up to Two Lanes(4) | |
PCIE3 | Up to Two Lanes(4) | Up to Two Lanes(4) | |
2x Programmable Real-Time Unit Subsystem and TSN Communication Subsystem (Ethernet Subsystem) | PRU_ICSSG0 | No | No |
PRU_ICSSG1 | No | No | |
Gigabit Ethernet Interface | CPSW2G | RMII or RGMII | RMII or RGMII |
CPSW9G | 8 × RMII 8 × RGMII 8 × SGMII(4) |
8 × RMII 8 × RGMII 8 × SGMII(4) |
|
General-Purpose Timers | TIMER | 30 | 30 |
Enhanced High Resolution Pulse-Width Modulator Module | eHRPWM | 6 | 6 |
Enhanced Capture Module | eCAP | 3 | 3 |
Enhanced Quadrature Encoder Pulse Module | eQEP | 3 | 3 |
Universal Asynchronous Receiver and Transmitter | UART | 12 | 12 |
Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device (DRD) Ports with SS PHY | USB0 | Yes(4) | Yes(4) |
USB1 | Yes(4) | Yes(4) |