SPRSP65G April   2021  – May 2024 AM2431 , AM2432 , AM2434

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM243x ALV Pin Diagram
      2. 5.1.2 AM243x ALX Pin Diagram
    2. 5.2 Pin Attributes
      1.      13
      2.      14
      3. 5.2.1 AM243x Package Comparison Table (ALV vs. ALX)
    3. 5.3 Signal Descriptions
      1.      17
      2. 5.3.1  AM243x_ALX Package - Unsupported Interfaces and Signals
      3. 5.3.2  ADC
        1.       MAIN Domain Instances
          1.        21
      4. 5.3.3  CPSW
        1.       MAIN Domain Instances
          1.        24
          2.        25
          3.        26
          4.        27
          5. 5.3.3.1.1 CPSW3G IOSETs
      5. 5.3.4  CPTS
        1.       MAIN Domain Instances
          1.        31
          2.        32
      6. 5.3.5  DDRSS
        1.       MAIN Domain Instances
          1.        35
      7. 5.3.6  ECAP
        1.       MAIN Domain Instances
          1.        38
          2.        39
          3.        40
      8. 5.3.7  Emulation and Debug
        1.       MAIN Domain Instances
          1.        43
        2.       MCU Domain Instances
          1.        45
      9. 5.3.8  EPWM
        1.       MAIN Domain Instances
          1.        48
          2.        49
          3.        50
          4.        51
          5.        52
          6.        53
          7.        54
          8.        55
          9.        56
          10.        57
      10. 5.3.9  EQEP
        1.       MAIN Domain Instances
          1.        60
          2.        61
          3.        62
      11. 5.3.10 FSI
        1.       MAIN Domain Instances
          1.        65
          2.        66
          3.        67
          4.        68
          5.        69
          6.        70
          7.        71
          8.        72
      12. 5.3.11 GPIO
        1.       MAIN Domain Instances
          1.        75
          2.        76
        2.       MCU Domain Instances
          1.        78
      13. 5.3.12 GPMC
        1.       MAIN Domain Instances
          1.        81
          2. 5.3.12.1.1 GPMC0 IOSETs (ALV)
      14. 5.3.13 I2C
        1.       MAIN Domain Instances
          1.        85
          2.        86
          3.        87
          4.        88
        2.       MCU Domain Instances
          1.        90
          2.        91
      15. 5.3.14 MCAN
        1.       MAIN Domain Instances
          1.        94
          2.        95
      16. 5.3.15 SPI (MCSPI)
        1.       MAIN Domain Instances
          1.        98
          2.        99
          3.        100
          4.        101
          5.        102
        2.       MCU Domain Instances
          1.        104
          2.        105
      17. 5.3.16 MMC
        1.       MAIN Domain Instances
          1.        108
          2.        109
      18. 5.3.17 OSPI
        1.       MAIN Domain Instances
          1.        112
      19. 5.3.18 Power Supply
        1.       114
      20. 5.3.19 PRU_ICSSG
        1.       MAIN Domain Instances
          1.        117
          2.        118
      21. 5.3.20 Reserved
        1.       120
      22. 5.3.21 SERDES
        1.       MAIN Domain Instances
          1.        123
      23. 5.3.22 System and Miscellaneous
        1. 5.3.22.1 Boot Mode Configuration
          1.        MAIN Domain Instances
            1.         127
        2. 5.3.22.2 Clocking
          1.        MCU Domain Instances
            1.         130
        3. 5.3.22.3 SYSTEM
          1.        MAIN Domain Instances
            1.         133
          2.        MCU Domain Instances
            1.         135
        4. 5.3.22.4 VMON
          1.        137
      24. 5.3.23 TIMER
        1.       MAIN Domain Instances
          1.        140
        2.       MCU Domain Instances
          1.        142
      25. 5.3.24 UART
        1.       MAIN Domain Instances
          1.        145
          2.        146
          3.        147
          4.        148
          5.        149
          6.        150
          7.        151
        2.       MCU Domain Instances
          1.        153
          2.        154
      26. 5.3.25 USB
        1.       MAIN Domain Instances
          1.        157
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Consumption Summary
    7. 6.7  Electrical Characteristics
      1. 6.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.7.4  eMMCPHY Electrical Characteristics
      5. 6.7.5  SDIO Electrical Characteristics
      6. 6.7.6  LVCMOS Electrical Characteristics
      7. 6.7.7  ADC12B Electrical Characteristics (ALV package)
      8. 6.7.8  ADC10B Electrical Characteristics (ALX package)
      9. 6.7.9  USB2PHY Electrical Characteristics
      10. 6.7.10 SerDes PHY Electrical Characteristics
      11. 6.7.11 DDR Electrical Characteristics
    8. 6.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.8.2 Hardware Requirements
      3. 6.8.3 Programming Sequence
      4. 6.8.4 Impact to Your Hardware Warranty
    9. 6.9  Thermal Resistance Characteristics
      1. 6.9.1 Thermal Resistance Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Requirements
        1. 6.10.2.1 Power Supply Slew Rate Requirement
        2. 6.10.2.2 Power Supply Sequencing
          1. 6.10.2.2.1 Power-Up Sequencing
          2. 6.10.2.2.2 Power-Down Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input Clocks / Oscillators
          1. 6.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.10.5 Peripherals
        1. 6.10.5.1  CPSW3G
          1. 6.10.5.1.1 CPSW3G MDIO Timing
          2. 6.10.5.1.2 CPSW3G RMII Timing
          3. 6.10.5.1.3 CPSW3G RGMII Timing
          4. 6.10.5.1.4 CPSW3G IOSETs
        2. 6.10.5.2  DDRSS
        3. 6.10.5.3  ECAP
        4. 6.10.5.4  EPWM
        5. 6.10.5.5  EQEP
        6. 6.10.5.6  FSI
        7. 6.10.5.7  GPIO
        8. 6.10.5.8  GPMC
          1. 6.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 6.10.5.8.4 GPMC0 IOSETs (ALV)
        9. 6.10.5.9  I2C
        10. 6.10.5.10 MCAN
        11. 6.10.5.11 MCSPI
          1. 6.10.5.11.1 MCSPI — Controller Mode
          2. 6.10.5.11.2 MCSPI — Peripheral Mode
        12. 6.10.5.12 MMCSD
          1. 6.10.5.12.1 MMC0 - eMMC Interface
            1. 6.10.5.12.1.1 Legacy SDR Mode
            2. 6.10.5.12.1.2 High Speed SDR Mode
            3. 6.10.5.12.1.3 High Speed DDR Mode
            4. 6.10.5.12.1.4 HS200 Mode
          2. 6.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 6.10.5.12.2.1 Default Speed Mode
            2. 6.10.5.12.2.2 High Speed Mode
            3. 6.10.5.12.2.3 UHS–I SDR12 Mode
            4. 6.10.5.12.2.4 UHS–I SDR25 Mode
            5. 6.10.5.12.2.5 UHS–I SDR50 Mode
            6. 6.10.5.12.2.6 UHS–I DDR50 Mode
            7. 6.10.5.12.2.7 UHS–I SDR104 Mode
        13. 6.10.5.13 CPTS
        14. 6.10.5.14 OSPI
          1. 6.10.5.14.1 OSPI0 PHY Mode
            1. 6.10.5.14.1.1 OSPI0 With PHY Data Training
            2. 6.10.5.14.1.2 OSPI0 Without Data Training
              1. 6.10.5.14.1.2.1 OSPI0 PHY SDR Timing
              2. 6.10.5.14.1.2.2 OSPI0 PHY DDR Timing
          2. 6.10.5.14.2 OSPI0 Tap Mode
            1. 6.10.5.14.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.14.2.2 OSPI0 Tap DDR Timing
        15. 6.10.5.15 PCIe
        16. 6.10.5.16 PRU_ICSSG
          1. 6.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 6.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 6.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 6.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 6.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 6.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 6.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 6.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 6.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 6.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 6.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 6.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 6.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 6.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 6.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 6.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 6.10.5.17 Timers
        18. 6.10.5.18 UART
        19. 6.10.5.19 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem (R5FSS)
      2. 7.2.2 Arm Cortex-M4F (M4FSS)
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 7.4 Other Subsystems
      1. 7.4.1 PDMA Controller
      2. 7.4.2 Peripherals
        1. 7.4.2.1  ADC
        2. 7.4.2.2  DCC
        3. 7.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 7.4.2.4  ECAP
        5. 7.4.2.5  EPWM
        6. 7.4.2.6  ELM
        7. 7.4.2.7  ESM
        8. 7.4.2.8  GPIO
        9. 7.4.2.9  EQEP
        10. 7.4.2.10 General-Purpose Memory Controller (GPMC)
        11. 7.4.2.11 I2C
        12. 7.4.2.12 MCAN
        13. 7.4.2.13 MCRC Controller
        14. 7.4.2.14 MCSPI
        15. 7.4.2.15 MMCSD
        16. 7.4.2.16 OSPI
        17. 7.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 7.4.2.18 Serializer/Deserializer (SerDes) PHY
        19. 7.4.2.19 Real Time Interrupt (RTI/WWDT)
        20. 7.4.2.20 Dual Mode Timer (DMTIMER)
        21. 7.4.2.21 UART
        22. 7.4.2.22 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 General Routing Guidelines
      2. 8.2.2 DDR Board Design and Layout Guidelines
      3. 8.2.3 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.3.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.3.2 External Board Loopback
        3. 8.2.3.3 DQS (only available in Octal SPI devices)
      4. 8.2.4 USB VBUS Design Guidelines
      5. 8.2.5 System Power Supply Monitor Design Guidelines
      6. 8.2.6 High Speed Differential Signal Routing Guidance
      7. 8.2.7 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
      2. 8.3.2 Oscillator Ground Connection
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
      1. 9.3.1 Information About Cautions and Warnings
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

6.7.7 ADC12B Electrical Characteristics (ALV package)

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution (ALV package) 12 Bits
VADC0_VREFP(1) Positive Reference Voltage,
ADC0_VREFP		 1.71 1.89 V
VADC0_VREFN(1) Negative Reference Voltage,
ADC0_VREFN		 VSS V
VADC_AIN[7:0] Analog Input Voltage,
ADC_AIN[7:0], Full-scale		 VSS VDDA_ADC0 V
DNL Differential Non-Linearity > -1 +1 LSB
INL Integral Non-Linearity -2 +2 LSB
LSBGAIN-ERROR Gain Error ±10 LSB
LSBOFFSET-ERROR Offset Error ±5 LSB
SNR Signal-to-Noise Ratio Input Signal:
200 kHz sine wave at
-0.5 dB Full Scale		 70 dB
THD Total Harmonic Distortion Input Signal:
200 kHz sine wave at
-0.5 dB Full Scale		 -75 dB
ZADC_AIN[0:7] Analog Input Impedance,
ADC0_AIN[7:0]		 (2) Ω
IIN Input Leakage ±10 μA
CSMPL Sampling Capacitance 5.5 pF
Sampling Dynamics
FSMPL_CLK ADC0 SMPL_CLK Frequency 60 MHz
tC Conversion Time 13 ADC0
SMPL_CLK
Cycles
tACQ Acquisition Time 2 257 ADC0
SMPL_CLK
Cycles
TR Sampling Rate ADC0 SMPL_CLK
= 60MHz		 4 MSPS
General Purpose Input Mode(3)
VIL Input Low Voltage 0.35 × VDDA_ADC0 V
VILSS Input Low Voltage Steady State 0.35 × VDDA_ADC0 V
VIH Input High Voltage 0.65 × VDDA_ADC0 V
VIHSS Input High Voltage Steady State 0.65 × VDDA_ADC0 V
VHYS Input Hysteresis Voltage 200 mV
II Input Leakage Current ADC0_AIN[7:0] = VDDA_ADC0
or
ADC0_AIN[7:0] = VSS		 10 μA
(1) The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails. ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is connected to a power source capable of providing at least 4 mA of current. ADC0_REFP can be connected to the same power source as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency decoupling capacitor must be connected directly to the ADC0_REFP and ADC0_REFN pins with vias and be placed in the ball array on the back side of the PCB.
(2) The ADC0_AIN pins are connected to an internal sampling capacitor for a user configurable acquisition time and acquisition frequency. The input impedance of the ADC0_AIN pins is a function of the sampling capacitance along with user configurable acquisition time and acquisition frequency. The designer must understand the time required for the source impedance of each ADC0_AIN pin to charge the internal sampling capacitor. The acquisition time must be set long enough for the internal sampling capacitor to settle to greater than 14 bits of accuracy.
(3) ADC0 can be configured to operate in General Purpose Input mode, where all ADC0_AIN[7:0] inputs are globally enabled to operate as digital inputs via the ADC0_CTRL register (gpi_mode_en = 1).