SPRSP65G April   2021  – May 2024 AM2431 , AM2432 , AM2434

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM243x ALV Pin Diagram
      2. 5.1.2 AM243x ALX Pin Diagram
    2. 5.2 Pin Attributes
      1.      13
      2.      14
      3. 5.2.1 AM243x Package Comparison Table (ALV vs. ALX)
    3. 5.3 Signal Descriptions
      1.      17
      2. 5.3.1  AM243x_ALX Package - Unsupported Interfaces and Signals
      3. 5.3.2  ADC
        1.       MAIN Domain Instances
          1.        21
      4. 5.3.3  CPSW
        1.       MAIN Domain Instances
          1.        24
          2.        25
          3.        26
          4.        27
          5. 5.3.3.1.1 CPSW3G IOSETs
      5. 5.3.4  CPTS
        1.       MAIN Domain Instances
          1.        31
          2.        32
      6. 5.3.5  DDRSS
        1.       MAIN Domain Instances
          1.        35
      7. 5.3.6  ECAP
        1.       MAIN Domain Instances
          1.        38
          2.        39
          3.        40
      8. 5.3.7  Emulation and Debug
        1.       MAIN Domain Instances
          1.        43
        2.       MCU Domain Instances
          1.        45
      9. 5.3.8  EPWM
        1.       MAIN Domain Instances
          1.        48
          2.        49
          3.        50
          4.        51
          5.        52
          6.        53
          7.        54
          8.        55
          9.        56
          10.        57
      10. 5.3.9  EQEP
        1.       MAIN Domain Instances
          1.        60
          2.        61
          3.        62
      11. 5.3.10 FSI
        1.       MAIN Domain Instances
          1.        65
          2.        66
          3.        67
          4.        68
          5.        69
          6.        70
          7.        71
          8.        72
      12. 5.3.11 GPIO
        1.       MAIN Domain Instances
          1.        75
          2.        76
        2.       MCU Domain Instances
          1.        78
      13. 5.3.12 GPMC
        1.       MAIN Domain Instances
          1.        81
          2. 5.3.12.1.1 GPMC0 IOSETs (ALV)
      14. 5.3.13 I2C
        1.       MAIN Domain Instances
          1.        85
          2.        86
          3.        87
          4.        88
        2.       MCU Domain Instances
          1.        90
          2.        91
      15. 5.3.14 MCAN
        1.       MAIN Domain Instances
          1.        94
          2.        95
      16. 5.3.15 SPI (MCSPI)
        1.       MAIN Domain Instances
          1.        98
          2.        99
          3.        100
          4.        101
          5.        102
        2.       MCU Domain Instances
          1.        104
          2.        105
      17. 5.3.16 MMC
        1.       MAIN Domain Instances
          1.        108
          2.        109
      18. 5.3.17 OSPI
        1.       MAIN Domain Instances
          1.        112
      19. 5.3.18 Power Supply
        1.       114
      20. 5.3.19 PRU_ICSSG
        1.       MAIN Domain Instances
          1.        117
          2.        118
      21. 5.3.20 Reserved
        1.       120
      22. 5.3.21 SERDES
        1.       MAIN Domain Instances
          1.        123
      23. 5.3.22 System and Miscellaneous
        1. 5.3.22.1 Boot Mode Configuration
          1.        MAIN Domain Instances
            1.         127
        2. 5.3.22.2 Clocking
          1.        MCU Domain Instances
            1.         130
        3. 5.3.22.3 SYSTEM
          1.        MAIN Domain Instances
            1.         133
          2.        MCU Domain Instances
            1.         135
        4. 5.3.22.4 VMON
          1.        137
      24. 5.3.23 TIMER
        1.       MAIN Domain Instances
          1.        140
        2.       MCU Domain Instances
          1.        142
      25. 5.3.24 UART
        1.       MAIN Domain Instances
          1.        145
          2.        146
          3.        147
          4.        148
          5.        149
          6.        150
          7.        151
        2.       MCU Domain Instances
          1.        153
          2.        154
      26. 5.3.25 USB
        1.       MAIN Domain Instances
          1.        157
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Consumption Summary
    7. 6.7  Electrical Characteristics
      1. 6.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.7.4  eMMCPHY Electrical Characteristics
      5. 6.7.5  SDIO Electrical Characteristics
      6. 6.7.6  LVCMOS Electrical Characteristics
      7. 6.7.7  ADC12B Electrical Characteristics (ALV package)
      8. 6.7.8  ADC10B Electrical Characteristics (ALX package)
      9. 6.7.9  USB2PHY Electrical Characteristics
      10. 6.7.10 SerDes PHY Electrical Characteristics
      11. 6.7.11 DDR Electrical Characteristics
    8. 6.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.8.2 Hardware Requirements
      3. 6.8.3 Programming Sequence
      4. 6.8.4 Impact to Your Hardware Warranty
    9. 6.9  Thermal Resistance Characteristics
      1. 6.9.1 Thermal Resistance Characteristics
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1 Timing Parameters and Information
      2. 6.10.2 Power Supply Requirements
        1. 6.10.2.1 Power Supply Slew Rate Requirement
        2. 6.10.2.2 Power Supply Sequencing
          1. 6.10.2.2.1 Power-Up Sequencing
          2. 6.10.2.2.2 Power-Down Sequencing
      3. 6.10.3 System Timing
        1. 6.10.3.1 Reset Timing
        2. 6.10.3.2 Safety Signal Timing
        3. 6.10.3.3 Clock Timing
      4. 6.10.4 Clock Specifications
        1. 6.10.4.1 Input Clocks / Oscillators
          1. 6.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.10.4.1.1.1 Load Capacitance
            2. 6.10.4.1.1.2 Shunt Capacitance
          2. 6.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 6.10.4.2 Output Clocks
        3. 6.10.4.3 PLLs
        4. 6.10.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.10.5 Peripherals
        1. 6.10.5.1  CPSW3G
          1. 6.10.5.1.1 CPSW3G MDIO Timing
          2. 6.10.5.1.2 CPSW3G RMII Timing
          3. 6.10.5.1.3 CPSW3G RGMII Timing
          4. 6.10.5.1.4 CPSW3G IOSETs
        2. 6.10.5.2  DDRSS
        3. 6.10.5.3  ECAP
        4. 6.10.5.4  EPWM
        5. 6.10.5.5  EQEP
        6. 6.10.5.6  FSI
        7. 6.10.5.7  GPIO
        8. 6.10.5.8  GPMC
          1. 6.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 6.10.5.8.4 GPMC0 IOSETs (ALV)
        9. 6.10.5.9  I2C
        10. 6.10.5.10 MCAN
        11. 6.10.5.11 MCSPI
          1. 6.10.5.11.1 MCSPI — Controller Mode
          2. 6.10.5.11.2 MCSPI — Peripheral Mode
        12. 6.10.5.12 MMCSD
          1. 6.10.5.12.1 MMC0 - eMMC Interface
            1. 6.10.5.12.1.1 Legacy SDR Mode
            2. 6.10.5.12.1.2 High Speed SDR Mode
            3. 6.10.5.12.1.3 High Speed DDR Mode
            4. 6.10.5.12.1.4 HS200 Mode
          2. 6.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 6.10.5.12.2.1 Default Speed Mode
            2. 6.10.5.12.2.2 High Speed Mode
            3. 6.10.5.12.2.3 UHS–I SDR12 Mode
            4. 6.10.5.12.2.4 UHS–I SDR25 Mode
            5. 6.10.5.12.2.5 UHS–I SDR50 Mode
            6. 6.10.5.12.2.6 UHS–I DDR50 Mode
            7. 6.10.5.12.2.7 UHS–I SDR104 Mode
        13. 6.10.5.13 CPTS
        14. 6.10.5.14 OSPI
          1. 6.10.5.14.1 OSPI0 PHY Mode
            1. 6.10.5.14.1.1 OSPI0 With PHY Data Training
            2. 6.10.5.14.1.2 OSPI0 Without Data Training
              1. 6.10.5.14.1.2.1 OSPI0 PHY SDR Timing
              2. 6.10.5.14.1.2.2 OSPI0 PHY DDR Timing
          2. 6.10.5.14.2 OSPI0 Tap Mode
            1. 6.10.5.14.2.1 OSPI0 Tap SDR Timing
            2. 6.10.5.14.2.2 OSPI0 Tap DDR Timing
        15. 6.10.5.15 PCIe
        16. 6.10.5.16 PRU_ICSSG
          1. 6.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 6.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 6.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 6.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 6.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 6.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 6.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 6.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 6.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 6.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 6.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 6.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 6.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 6.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 6.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 6.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 6.10.5.17 Timers
        18. 6.10.5.18 UART
        19. 6.10.5.19 USB
      6. 6.10.6 Emulation and Debug
        1. 6.10.6.1 Trace
        2. 6.10.6.2 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem (R5FSS)
      2. 7.2.2 Arm Cortex-M4F (M4FSS)
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 7.4 Other Subsystems
      1. 7.4.1 PDMA Controller
      2. 7.4.2 Peripherals
        1. 7.4.2.1  ADC
        2. 7.4.2.2  DCC
        3. 7.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 7.4.2.4  ECAP
        5. 7.4.2.5  EPWM
        6. 7.4.2.6  ELM
        7. 7.4.2.7  ESM
        8. 7.4.2.8  GPIO
        9. 7.4.2.9  EQEP
        10. 7.4.2.10 General-Purpose Memory Controller (GPMC)
        11. 7.4.2.11 I2C
        12. 7.4.2.12 MCAN
        13. 7.4.2.13 MCRC Controller
        14. 7.4.2.14 MCSPI
        15. 7.4.2.15 MMCSD
        16. 7.4.2.16 OSPI
        17. 7.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 7.4.2.18 Serializer/Deserializer (SerDes) PHY
        19. 7.4.2.19 Real Time Interrupt (RTI/WWDT)
        20. 7.4.2.20 Dual Mode Timer (DMTIMER)
        21. 7.4.2.21 UART
        22. 7.4.2.22 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 General Routing Guidelines
      2. 8.2.2 DDR Board Design and Layout Guidelines
      3. 8.2.3 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.3.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.3.2 External Board Loopback
        3. 8.2.3.3 DQS (only available in Octal SPI devices)
      4. 8.2.4 USB VBUS Design Guidelines
      5. 8.2.5 System Power Supply Monitor Design Guidelines
      6. 8.2.6 High Speed Differential Signal Routing Guidance
      7. 8.2.7 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
      2. 8.3.2 Oscillator Ground Connection
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
      1. 9.3.1 Information About Cautions and Warnings
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information
Table 5-44 GPMC0 Signal Descriptions
Signal Name [1] ((3))Signal Type [2]Description [3]ALV PIN [4]ALX PIN [4]
GPMC0_ADVn_ALEOGPMC Address Valid (active low) or Address Latch EnableP16
GPMC0_CLK (1)OGPMC ClockR17
GPMC0_DIROGPMC Data Bus Signal Direction ControlN17
GPMC0_FCLK_MUX (2)OGPMC functional clock output selected through mux logicR17
GPMC0_OEn_REnOGPMC Output Enable (active low) or Read Enable (active low)R18
GPMC0_WEnOGPMC Write Enable (active low)T21
GPMC0_WPnOGPMC Flash Write Protect (active low)N16
GPMC0_A0OZGPMC Address 0 Output. Only used to effectively address 8-bit data non-multiplexed memoriesU2, U7G1, T2
GPMC0_A1OZGPMC address 1 Output in A/D non-multiplexed mode and Address 17 in A/D multiplexed modeAA2, V7K2, Y4
GPMC0_A2OZGPMC address 2 Output in A/D non-multiplexed mode and Address 18 in A/D multiplexed modeT2, W7H5, U3
GPMC0_A3OZGPMC address 3 Output in A/D non-multiplexed mode and Address 19 in A/D multiplexed modeV4, W11AA10, N2
GPMC0_A4OZGPMC address 4 Output in A/D non-multiplexed mode and Address 20 in A/D multiplexed modeU4, V11N3, Y10
GPMC0_A5OZGPMC address 5 Output in A/D non-multiplexed mode and Address 21 in A/D multiplexed modeAA12, V1K4, Y11
GPMC0_A6OZGPMC address 6 Output in A/D non-multiplexed mode and Address 22 in A/D multiplexed modeW1, Y12G2, V12
GPMC0_A7OZGPMC address 7 Output in A/D non-multiplexed mode and Address 23 in A/D multiplexed modeW12, Y4P2, Y12
GPMC0_A8OZGPMC address 8 Output in A/D non-multiplexed mode and Address 24 in A/D multiplexed modeAA13, T6AA11, T4
GPMC0_A9OZGPMC address 9 Output in A/D non-multiplexed mode and Address 25 in A/D multiplexed modeU11, U6R5, V10
GPMC0_A10OZGPMC address 10 Output in A/D non-multiplexed mode and Address 26 in A/D multiplexed modeU5, V15M4, Y14
GPMC0_A11OZGPMC address 11 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeAA4, U12T3, W11
GPMC0_A12OZGPMC address 12 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeP2, V14E4, Y16
GPMC0_A13OZGPMC address 13 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeP3, W14D2, U13
GPMC0_A14OZGPMC address 14 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeAA10, AA3K1, Y6
GPMC0_A15OZGPMC address 15 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeR6, V10AA8, N1
GPMC0_A16OZGPMC address 16 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeT5, U10N4, Y9
GPMC0_A17OZGPMC address 17 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeAA11, U1E1, W9
GPMC0_A18OZGPMC address 18 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeT4, Y11L2, V9
GPMC0_A19OZGPMC address 19 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeR5, Y10F5, Y8
GPMC0_A20OZGPMC address 20 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeR21
GPMC0_A21OZGPMC address 21 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeY18
GPMC0_A22OZGPMC address 22 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeN16
GPMC0_AD0IOGPMC Data 0 Input/Output in A/D non-multiplexed mode and additionally Address 1 Output in A/D multiplexed modeT20R21
GPMC0_AD1IOGPMC Data 1 Input/Output in A/D non-multiplexed mode and additionally Address 2 Output in A/D multiplexed modeU21R20
GPMC0_AD2IOGPMC Data 2 Input/Output in A/D non-multiplexed mode and additionally Address 3 Output in A/D multiplexed modeT18T19
GPMC0_AD3IOGPMC Data 3 Input/Output in A/D non-multiplexed mode and additionally Address 4 Output in A/D multiplexed modeU20V21
GPMC0_AD4IOGPMC Data 4 Input/Output in A/D non-multiplexed mode and additionally Address 5 Output in A/D multiplexed modeU18U21
GPMC0_AD5IOGPMC Data 5 Input/Output in A/D non-multiplexed mode and additionally Address 6 Output in A/D multiplexed modeU19T20
GPMC0_AD6IOGPMC Data 6 Input/Output in A/D non-multiplexed mode and additionally Address 7 Output in A/D multiplexed modeV20T18
GPMC0_AD7IOGPMC Data 7 Input/Output in A/D non-multiplexed mode and additionally Address 8 Output in A/D multiplexed modeV21U19
GPMC0_AD8IOGPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed modeV19U18
GPMC0_AD9IOGPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed modeT17U20
GPMC0_AD10IOGPMC Data 10 Input/Output in A/D non-multiplexed mode and additionally Address 11 Output in A/D multiplexed modeR16V20
GPMC0_AD11IOGPMC Data 11 Input/Output in A/D non-multiplexed mode and additionally Address 12 Output in A/D multiplexed modeW20W20
GPMC0_AD12IOGPMC Data 12 Input/Output in A/D non-multiplexed mode and additionally Address 13 Output in A/D multiplexed modeW21Y20
GPMC0_AD13IOGPMC Data 13 Input/Output in A/D non-multiplexed mode and additionally Address 14 Output in A/D multiplexed modeV18Y19
GPMC0_AD14IOGPMC Data 14 Input/Output in A/D non-multiplexed mode and additionally Address 15 Output in A/D multiplexed modeY21Y18
GPMC0_AD15IOGPMC Data 15 Input/Output in A/D non-multiplexed mode and additionally Address 16 Output in A/D multiplexed modeY20AA19
GPMC0_AD16IOGPMC Data 16 Input/Output in A/D non-multiplexed mode and additionally Address 17 Output in A/D multiplexed modeY7V4
GPMC0_AD17IOGPMC Data 17 Input/Output in A/D non-multiplexed mode and additionally Address 18 Output in A/D multiplexed modeU8W5
GPMC0_AD18IOGPMC Data 18 Input/Output in A/D non-multiplexed mode and additionally Address 19 Output in A/D multiplexed modeW8AA4
GPMC0_AD19IOGPMC Data 19 Input/Output in A/D non-multiplexed mode and additionally Address 20 Output in A/D multiplexed modeV8Y5
GPMC0_AD20IOGPMC Data 20 Input/Output in A/D non-multiplexed mode and additionally Address 21 Output in A/D multiplexed modeY8AA5
GPMC0_AD21IOGPMC Data 21 Input/Output in A/D non-multiplexed mode and additionally Address 22 Output in A/D multiplexed modeV13U14
GPMC0_AD22IOGPMC Data 22 Input/Output in A/D non-multiplexed mode and additionally Address 23 Output in A/D multiplexed modeAA7Y2
GPMC0_AD23IOGPMC Data 23 Input/Output in A/D non-multiplexed mode and additionally Address 24 Output in A/D multiplexed modeU13V13
GPMC0_AD24IOGPMC Data 24 Input/Output in A/D non-multiplexed mode and additionally Address 25 Output in A/D multiplexed modeW13Y13
GPMC0_AD25IOGPMC Data 25 Input/Output in A/D non-multiplexed mode and additionally Address 26 Output in A/D multiplexed modeU15W16
GPMC0_AD26IOGPMC Data 26 Input/Output in A/D non-multiplexed mode and additionally Address 27 Output in A/D multiplexed modeU14W13
GPMC0_AD27IOGPMC Data 27 Input/Output in A/D non-multiplexed mode and additionally Address 28 Output in A/D multiplexed modeAA8V5
GPMC0_AD28IOGPMC Data 28 Input/Output in A/D non-multiplexed mode and additionally Address 29 Output in A/D multiplexed modeU9W2
GPMC0_AD29IOGPMC Data 29 Input/Output in A/D non-multiplexed mode and additionally Address 30 Output in A/D multiplexed modeW9V6
GPMC0_AD30IOGPMC Data 30 Input/Output in A/D non-multiplexed mode and additionally Address 31 Output in A/D multiplexed modeAA9AA7
GPMC0_AD31IOGPMC Data 31 Input/Output in A/D non-multiplexed mode and additionally Address 0 Output in A/D multiplexed modeY9Y7
GPMC0_BE0n_CLEOGPMC Lower-Byte Enable (active low) or Command Latch EnableP17
GPMC0_BE1nOGPMC Upper-Byte Enable (active low)T19P21
GPMC0_BE2nOGPMC Upper-Byte Enable (active low)V9W6
GPMC0_BE3nOGPMC Upper-Byte Enable (active low)AA14AA14
GPMC0_CSn0OGPMC Chip Select 0 (active low)R19
GPMC0_CSn1OGPMC Chip Select 1 (active low)R20
GPMC0_CSn2OGPMC Chip Select 2 (active low)P19
GPMC0_CSn3OGPMC Chip Select 3 (active low)R21
GPMC0_WAIT0IGPMC External Indication of WaitW19
GPMC0_WAIT1IGPMC External Indication of WaitY18
(1) The RXACTIVE bit of the CTRLMMR_PADCONFIG32 register must be set to 0x1 and the TX_DIS bit of the CTRLMMR_PADCONFIG32 register must be reset to 0x0 when GPMC0 is operating in synchronous mode.
(2) The GPMC0_FCLK_MUX signal is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.
(3) The GPMC0 interface is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.