SPRSP65G April 2021 – May 2024 AM2431 , AM2432 , AM2434
PRODUCTION DATA
Signal Name [1] | Signal Type [2] | Description [3] | ALV PIN [4] | ALX PIN [4] |
---|---|---|---|---|
CLKOUT0 | O | RMII Clock Output (50MHz). This pin is used for clock source to the external PHY and must be routed back to the RMII_REF_CLK pin for proper device operation. | A19, U13 | A18, V13 |
EXTINTn (1) (2) | I | External Interrupt | C19 | |
EXT_REFCLK1 | I | External clock input to MAIN Domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WWDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) | A19 | A18 |
OBSCLK0 | O | Observation clock output for test and debug purposes only | D17 | A15 |
PORz_OUT | O | MAIN Domain POR status output | E17 | D18 |
RESETSTATz | O | MAIN Domain warm reset status output | F16 | E19 |
RESET_REQz | I | MAIN Domain external warm reset request input | E18 | C17 |
SYSCLKOUT0 | O | SYSCLK0 output from MAIN PLL controller (divided by 6) for test and debug purposes only | C17 | B14 |