SPRSP65G April 2021 – May 2024 AM2431 , AM2432 , AM2434
PRODUCTION DATA
Table 6-74, Figure 6-60, Table 6-75, and Figure 6-61 present timing requirements and switching characteristics for MMC0 – High Speed DDR Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
HSDDR1 | tsu(cmdV-clk) | Setup time, MMC0_CMD valid before MMC0_CLK rising edge | 1.62 | ns | |
HSDDR2 | th(clk-cmdV) | Hold time, MMC0_CMD valid after MMC0_CLK rising edge | 2.52 | ns | |
HSDDR3 | tsu(dV-clk) | Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition | 0.83 | ns | |
HSDDR4 | th(clk-dV) | Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition | 1.76 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC0_CLK | 50 | MHz | ||
HSDDR5 | tc(clk) | Cycle time, MMC0_CLK | 20 | ns | |
HSDDR6 | tw(clkH) | Pulse duration, MMC0_CLK high | 9.2 | ns | |
HSDDR7 | tw(clkL) | Pulse duration, MMC0_CLK low | 9.2 | ns | |
HSDDR8 | td(clk-cmdV) | Delay time, MMC0_CLK rising edge to MMC0_CMD transition | 3.31 | 7.65 | ns |
HSDDR9 | td(clk-dV) | Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition | 2.81 | 6.94 | ns |