SPRSP65G April 2021 – May 2024 AM2431 , AM2432 , AM2434
PRODUCTION DATA
Table 6-88, and Figure 6-72 present switching characteristics for MMC1 – UHS-I DDR50 Mode.
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC1_CLK | 50 | MHz | ||
DDR505 | tc(clk) | Cycle time, MMC1_CLK | 20 | ns | |
DDR506 | tw(clkH) | Pulse duration, MMC1_CLK high | 9.2 | ns | |
DDR507 | tw(clkL) | Pulse duration, MMC1_CLK low | 9.2 | ns | |
DDR508 | td(clk-cmdV) | Delay time, MMC1_CLK rising edge to MMC1_CMD transition | 1.2 | 6.35 | ns |
DDR509 | td(clk-dV) | Delay time, MMC1_CLK transition to MMC1_DAT[3:0] transition | 1.2 | 6.35 | ns |