SPRSP65G April 2021 – May 2024 AM2431 , AM2432 , AM2434
PRODUCTION DATA
Table 6-56 and Table 6-57 present timing requirements and switching characteristics for GPMC and NOR Flash — Asynchronous Mode.
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
FA5(1) | tacc(d) | Data access time | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
H(4) | ns | |
FA20(2) | tacc1-pgmode(d) | Page mode successive data access time | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
P(3) | ns | |
FA21(1) | tacc2-pgmode(d) | Page mode first data access time | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
H(4) | ns |
NO. | PARAMETER | DESCRIPTION | MODE(15) | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
133MHz | ||||||
FA0 | tw(be[x]nV) | Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time | Read | N (12) | ns | |
Write | N (12) | |||||
FA1 | tw(csnV) | Pulse duration, output chip select GPMC_CSn[i](13) low | Read | A (1) | ns | |
Write | A (1) | |||||
FA3 | td(csnV-advnIV) | Delay time, output chip select GPMC_CSn[i](13) valid to output address valid and address latch enable GPMC_ADVn_ALE invalid | Read | B - 2.1 (2) | B + 2.1 (2) | ns |
Write | B - 2.1 (2) | B + 2.1 (2) | ||||
FA4 | td(csnV-oenIV) | Delay time, output chip select GPMC_CSn[i](13) valid to output enable GPMC_OEn_REn invalid (Single read) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
C - 2.1 (3) | C + 2.1 (3) | ns |
FA9 | td(aV-csnV) | Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSn[i](13) valid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
J - 2.1 (9) | J + 2.1 (9) | ns |
FA10 | td(be[x]nV-csnV) | Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSn[i](13) valid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
J - 2.1 (9) | J + 2.1 (9) | ns |
FA12 | td(csnV-advnV) | Delay time, output chip select GPMC_CSn[i](13) valid to output address valid and address latch enable GPMC_ADVn_ALE valid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
K - 2.1 (10) | K + 2.1 (10) | ns |
FA13 | td(csnV-oenV) | Delay time, output chip select GPMC_CSn[i](13) valid to output enable GPMC_OEn_REn valid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
L - 2.1 (11) | L + 2.1 (11) | ns |
FA16 | tw(aIV) | Pulse duration output address GPMC_A[26:1] invalid between 2 successive read and write accesses | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
G (7) | ns | |
FA18 | td(csnV-oenIV) | Delay time, output chip select GPMC_CSn[i](13) valid to output enable GPMC_OEn_REn invalid (Burst read) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
I - 2.1 (8) | I + 2.1 (8) | ns |
FA20 | tw(aV) | Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
D (4) | ns | |
FA25 | td(csnV-wenV) | Delay time, output chip select GPMC_CSn[i](13) valid to output write enable GPMC_WEn valid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
E - 2.1 (5) | E + 2.1 (5) | ns |
FA27 | td(csnV-wenIV) | Delay time, output chip select GPMC_CSn[i](13) valid to output write enable GPMC_WEn invalid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
F - 2.1 (6) | F + 2.1 (6) | ns |
FA28 | td(wenV-dV) | Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
2.1 | ns | |
FA29 | td(dV-csnV) | Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSn[i](13) valid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
J - 2.1 (9) | J + 2.1 (9) | ns |
FA37 | td(oenV-aIV) | Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
2.1 | ns |