- The OSPI[x]_CLK output pin must
be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
- The signal propagation delay from
the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B) must
be ≤ 450 ps (~7cm as stripline or ~8cm as microstrip)
- The signal propagation delay of
each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be
approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to
the attached OSPI/QSPI/SPI device CLK pin (A to B)
- 50 Ω PCB routing is recommended
along with series terminations, as shown in Figure 8-2
- Propagation delays and matching:
- (A to B) ≤ 450 ps
- (E to F, or F to E) = ((A
to B) ± 60 ps)