SPRSP65G April 2021 – May 2024 AM2431 , AM2432 , AM2434
PRODUCTION DATA
MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and supports the following eMMC applications:
Table 6-68 presents the required DLL software configuration settings for MMC0 timing modes.
REGISTER NAME | MMCSD0_SS_PHY_CTRL_4_REG | MMCSD0_SS_PHY_CTRL_5_REG | |||||||
---|---|---|---|---|---|---|---|---|---|
BIT FIELD | [31:24] | [20] | [15:12] | [8] | [4:0] | [17:16] | [10:8] | [2:0] | |
BIT FIELD NAME | STRBSEL | OTAPDLYENA | OTAPDLYSEL | ITAPDLYENA | ITAPDLYSEL | SELDLYTXCLK SELDLYRXCLK |
FRQSEL | CLKBUFSEL | |
MODE | DESCRIPTION | STROBE DELAY |
OUTPUT DELAY ENABLE |
OUTPUT DELAY VALUE |
INPUT DELAY ENABLE |
INPUT DELAY VALUE |
DLL DELAY CHAIN SELECT |
DLL REF FREQUENCY |
DELAY BUFFER DURATION |
Legacy SDR | 8-bit PHY operating 1.8 V, 25MHz | 0x0 | 0x0 | NA(1) | 0x1 | 0x10 | 0x1 | 0x0 | 0x7 |
High Speed SDR | 8-bit PHY operating 1.8 V, 50MHz | 0x0 | 0x0 | NA(1) | 0x1 | 0xA | 0x1 | 0x0 | 0x7 |
High Speed DDR | 8-bit PHY operating 1.8 V, 50MHz | 0x0 | 0x1 | 0x6 | 0x1 | 0x3 | 0x0 | 0x4 | 0x7 |
HS200 | 8-bit PHY operating 1.8 V, 200MHz | 0x0 | 0x1 | 0x7 | 0x1 | Tuning(2) | 0x0 | 0x0 | 0x7 |
Table 6-78 presents timing conditions for MMC0.
PARAMETER | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|
INPUT CONDITIONS | ||||||
SRI | Input slew rate | Legacy SDR | 0.14 | 1.44 | V/ns | |
High Speed SDR | 0.3 | 0.9 | V/ns | |||
High Speed DDR (CMD) | 0.3 | 0.9 | V/ns | |||
High Speed DDR (DAT[7:0]) | 0.45 | 0.9 | V/ns | |||
OUTPUT CONDITIONS | ||||||
CL | Output load capacitance | Legacy SDR | 1 | 12 | pF | |
High Speed SDR | 1 | 12 | pF | |||
High Speed DDR | 1 | 12 | pF | |||
HS200 | 1 | 6 | pF | |||
PCB CONNECTIVITY REQUIREMENTS | ||||||
td(Trace Delay) | Propagation delay of each trace | All modes | 126 | 756 | ps | |
td(Trace Mismatch Delay) | Propagation delay mismatch across all traces | Legacy SDR, High Speed SDR | 100 | ps | ||
High Speed DDR, HS200 | 8 | ps |