SPRSP65G April 2021 – May 2024 AM2431 , AM2432 , AM2434
PRODUCTION DATA
MMC1 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
Table 6-77 presents the required DLL software configuration settings for MMC1 timing modes.
REGISTER NAME | MMCSD1_SS_PHY_CTRL_4_REG | MMCSD1_SS_PHY_CTRL_5_REG | ||||
---|---|---|---|---|---|---|
BIT FIELD | [20] | [15:12] | [8] | [4:0] | [2:0] | |
BIT FIELD NAME | OTAPDLYENA | OTAPDLYSEL | ITAPDLYENA | ITAPDLYSEL | CLKBUFSEL | |
MODE | DESCRIPTION | DELAY ENABLE |
DELAY VALUE |
INPUT DELAY ENABLE |
INPUT DELAY VALUE |
DELAY BUFFER DURATION |
Default Speed |
4-bit PHY operating 3.3 V, 25MHz |
0x1 | 0x0 | 0x1 | 0x0 | 0x7 |
High Speed |
4-bit PHY
operating 3.3 V, 50MHz |
0x1 | 0x0 | 0x1 | 0x0 | 0x7 |
UHS-I SDR12 |
4-bit PHY
operating 1.8 V, 25MHz |
0x1 | 0xF | 0x1 | 0x0 | 0x7 |
UHS-I SDR25 |
4-bit PHY
operating 1.8 V, 50MHz |
0x1 | 0xF | 0x1 | 0x0 | 0x7 |
UHS-I SDR50 |
4-bit PHY
operating 1.8 V, 100MHz |
0x1 | 0xC | 0x1 | Tuning(1) | 0x7 |
UHS-I DDR50 |
4-bit PHY
operating 1.8 V, 50MHz |
0x1 | 0x9 | 0x1 | Tuning(1) | 0x7 |
UHS-I SDR104 |
4-bit PHY operating 1.8,V 200MHz |
0x1 | 0x6 | 0x1 | Tuning(1) | 0x7 |
Table 6-78 presents timing conditions for MMC1.
PARAMETER | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|
Input Conditions | ||||||
SRI | Input slew rate | Default Speed, High Speed | 0.69 | 2.06 | V/ns | |
UHS–I SDR12, UHS–I SDR25 | 0.34 | 1.34 | V/ns | |||
UHS–I DDR50 | 1 | 2 | V/ns | |||
Output Conditions | ||||||
CL | Output load capacitance | UHS–I DDR50 | 3 | 10 | pF | |
All other modes | 1 | 10 | pF | |||
PCB Connectivity Requirements | ||||||
td(Trace Delay) | Propagation delay of each trace | UHS–I DDR50 | 240 | 1134 | ps | |
All other modes | 126 | 1386 | ps | |||
td(Trace Mismatch Delay) | Propagation delay mismatch across all traces | UHS–I DDR50, UHS–I SDR104 | 20 | ps | ||
All other modes | 100 | ps |