SPRSP65G April 2021 – May 2024 AM2431 , AM2432 , AM2434
PRODUCTION DATA
Table 6-46, Table 6-47, Figure 6-34, Table 6-48, Figure 6-35, Table 6-49, and Figure 6-36 present timing conditions, requirements, and switching characteristics for FSI.
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
INPUT CONDITIONS | ||||
SRI | Input slew rate | 0.8 | 4 | V/ns |
OUTPUT CONDITIONS | ||||
CL | Output load capacitance | 1 | 7 | pF |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
FSIR1 | tc(RX_CLK) | Cycle time, FSI_RXn_CLK | 20 | ns | |
FSIR2 | tw(RX_CLK) | Pulse width, FSI_RXn_CLK low or FSI_RXn_CLK high | 0.5P - 1(1) | 0.5P + 1(1) | ns |
FSIR3 | tsu(RX_D-RX_CLK) | Setup time, FSI_RXn_D[1:0] valid before FSI_RXn_CLK | 3 | ns | |
FSIR4 | th(RX_CLK-RX_D) | Hold time, FSI_RXn_D[1:0] valid after FSI_RXn_CLK | 2.5 | ns |
NO. | PARAMETER | MODE | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
FSIT1 | tc(TX_CLK) | Cycle time, FSI_TXn_CLK | FSI Mode | 20 | ns | |
FSIT2 | tw(TX_CLK) | Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high | FSI Mode | 0.5p + 1(1) | 0.5P - 1(1) | ns |
FSIT3 | td(TX_CLK-TX_D) | Delay time, FSI_TXn_D[1:0] valid after FSI_TXn_CLK high or FSI_TXn_CLK low | FSI Mode | 0.25P - 2(1) | 0.25P + 2.5(1) | ns |
NO. | PARAMETER | MODE | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
FSIT4 | tc(TX_CLK) | Cycle time, FSI_TXn_CLK | SPI Mode | 20 | ns | |
FSIT5 | tw(TX_CLK) | Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high | SPI Mode | 0.5P + 1(1) | 0.5P - 1(1) | ns |
FSIT6 | td(TX_CLKH-TX_D0) | Delay time, FSI_TXn_CLK high to FSI_TXn_D0 valid | SPI Mode | 3 | ns | |
FSIT7 | td(TX_D1-TX_CLK) | Delay time, FSI_TXn_D1 low to FSI_TXn_CLK high | SPI Mode | P - 3(1) | ns | |
FSIT8 | td(TX_CLK-TX_D1) | Delay time, FSI_TXn_CLK low to FSI_TXn_D1 high | SPI Mode | P - 2(1) | ns |
For more information, see Fast Serial Interface section in Peripherals chapter in the device TRM.