SPRSP65G April 2021 – May 2024 AM2431 , AM2432 , AM2434
PRODUCTION DATA
Table 6-81, Figure 6-65, Table 6-82, and Figure 6-66 present timing requirements and switching characteristics for MMC1 – High Speed Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
HS1 | tsu(cmdV-clkH) | Setup time, MMC1_CMD valid before MMC1_CLK rising edge | 2.15 | ns | |
HS2 | th(clkH-cmdV) | Hold time, MMC1_CMD valid after MMC1_CLK rising edge | 1.67 | ns | |
HS3 | tsu(dV-clkH) | Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge | 2.15 | ns | |
HS4 | th(clkH-dV) | Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge | 1.67 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC1_CLK | 50 | MHz | ||
HS5 | tc(clk) | Cycle time. MMC1_CLK | 20 | ns | |
HS6 | tw(clkH) | Pulse duration, MMC1_CLK high | 9.2 | ns | |
HS7 | tw(clkL) | Pulse duration, MMC1_CLK low | 9.2 | ns | |
HS8 | td(clkL-cmdV) | Delay time, MMC1_CLK falling edge to MMC1_CMD transition | -1.8 | 1.8 | ns |
HS9 | td(clkL-dV) | Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition | -1.8 | 1.8 | ns |