SPRSP85A April   2024  – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Reducing Current Consumption
        1. 6.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Special Considerations for 5V Fail-Safe Pins
    8. 6.8  Thermal Resistance Characteristics for PDT Package
    9. 6.9  Thermal Resistance Characteristics for PZ Package
    10. 6.10 Thermal Resistance Characteristics for PNA Package
    11. 6.11 Thermal Resistance Characteristics for PM Package
    12. 6.12 Thermal Resistance Characteristics for RSH Package
    13. 6.13 Thermal Design Considerations
    14. 6.14 System
      1. 6.14.1  Power Management Module (PMM)
        1. 6.14.1.1 Introduction
        2. 6.14.1.2 Overview
          1. 6.14.1.2.1 Power Rail Monitors
            1. 6.14.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.14.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.14.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.14.1.2.2 External Supervisor Usage
          3. 6.14.1.2.3 Delay Blocks
          4. 6.14.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.14.1.2.5 VREGENZ
        3. 6.14.1.3 External Components
          1. 6.14.1.3.1 Decoupling Capacitors
            1. 6.14.1.3.1.1 VDDIO Decoupling
            2. 6.14.1.3.1.2 VDD Decoupling
        4. 6.14.1.4 Power Sequencing
          1. 6.14.1.4.1 Supply Pins Ganging
          2. 6.14.1.4.2 Signal Pins Power Sequence
          3. 6.14.1.4.3 Supply Pins Power Sequence
            1. 6.14.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.14.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.14.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.14.1.4.3.4 Supply Slew Rate
        5. 6.14.1.5 Power Management Module Electrical Data and Timing
          1. 6.14.1.5.1 Power Management Module Operating Conditions
          2. 6.14.1.5.2 Power Management Module Characteristics
      2. 6.14.2  Reset Timing
        1. 6.14.2.1 Reset Sources
        2. 6.14.2.2 Reset Electrical Data and Timing
          1. 6.14.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.14.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.14.2.2.3 Reset Timing Diagrams
      3. 6.14.3  Clock Specifications
        1. 6.14.3.1 Clock Sources
        2. 6.14.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.14.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.14.3.2.1.1 Input Clock Frequency
            2. 6.14.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.14.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.14.3.2.1.4 X1 Timing Requirements
            5. 6.14.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.14.3.2.1.6 APLL Characteristics
            7. 6.14.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.14.3.2.1.8 Internal Clock Frequencies
        3. 6.14.3.3 Input Clocks and PLLs
        4. 6.14.3.4 XTAL Oscillator
          1. 6.14.3.4.1 Introduction
          2. 6.14.3.4.2 Overview
            1. 6.14.3.4.2.1 Electrical Oscillator
              1. 6.14.3.4.2.1.1 Modes of Operation
                1. 6.14.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.14.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.14.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.14.3.4.2.2 Quartz Crystal
            3. 6.14.3.4.2.3 GPIO Modes of Operation
          3. 6.14.3.4.3 Functional Operation
            1. 6.14.3.4.3.1 ESR – Effective Series Resistance
            2. 6.14.3.4.3.2 Rneg – Negative Resistance
            3. 6.14.3.4.3.3 Start-up Time
              1. 6.14.3.4.3.3.1 X1/X2 Precondition
            4. 6.14.3.4.3.4 DL – Drive Level
          4. 6.14.3.4.4 How to Choose a Crystal
          5. 6.14.3.4.5 Testing
          6. 6.14.3.4.6 Common Problems and Debug Tips
          7. 6.14.3.4.7 Crystal Oscillator Specifications
            1. 6.14.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.14.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.14.3.4.7.3 Crystal Oscillator Parameters
        5. 6.14.3.5 Internal Oscillators
          1. 6.14.3.5.1 INTOSC Characteristics
      4. 6.14.4  Flash Parameters
        1. 6.14.4.1 Flash Parameters 
      5. 6.14.5  RAM Specifications
      6. 6.14.6  ROM Specifications
      7. 6.14.7  Emulation/JTAG
        1. 6.14.7.1 JTAG Electrical Data and Timing
          1. 6.14.7.1.1 JTAG Timing Requirements
          2. 6.14.7.1.2 JTAG Switching Characteristics
          3. 6.14.7.1.3 JTAG Timing Diagram
        2. 6.14.7.2 cJTAG Electrical Data and Timing
          1. 6.14.7.2.1 cJTAG Timing Requirements
          2. 6.14.7.2.2 cJTAG Switching Characteristics
          3. 6.14.7.2.3 cJTAG Timing Diagram
      8. 6.14.8  GPIO Electrical Data and Timing
        1. 6.14.8.1 GPIO – Output Timing
          1. 6.14.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.14.8.1.2 General-Purpose Output Timing Diagram
        2. 6.14.8.2 GPIO – Input Timing
          1. 6.14.8.2.1 General-Purpose Input Timing Requirements
          2. 6.14.8.2.2 Sampling Mode
        3. 6.14.8.3 Sampling Window Width for Input Signals
      9. 6.14.9  Interrupts
        1. 6.14.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.14.9.1.1 External Interrupt Timing Requirements
          2. 6.14.9.1.2 External Interrupt Switching Characteristics
          3. 6.14.9.1.3 External Interrupt Timing
      10. 6.14.10 Low-Power Modes
        1. 6.14.10.1 Clock-Gating Low-Power Modes
        2. 6.14.10.2 Low-Power Mode Wake-up Timing
          1. 6.14.10.2.1 IDLE Mode Timing Requirements
          2. 6.14.10.2.2 IDLE Mode Switching Characteristics
          3. 6.14.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.14.10.2.4 STANDBY Mode Timing Requirements
          5. 6.14.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.14.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.14.10.2.7 HALT Mode Timing Requirements
          8. 6.14.10.2.8 HALT Mode Switching Characteristics
          9. 6.14.10.2.9 HALT Entry and Exit Timing Diagram
    15. 6.15 Analog Peripherals
      1. 6.15.1 Block Diagram
      2. 6.15.2 Analog Pins and Internal Connections
      3. 6.15.3 Analog Signal Descriptions
      4. 6.15.4 Analog-to-Digital Converter (ADC)
        1. 6.15.4.1 ADC Configurability
          1. 6.15.4.1.1 Signal Mode
        2. 6.15.4.2 ADC Electrical Data and Timing
          1. 6.15.4.2.1 ADC Operating Conditions
          2. 6.15.4.2.2 ADC Characteristics
          3. 6.15.4.2.3 ADC INL and DNL
          4. 6.15.4.2.4 ADC Performance Per Pin
          5. 6.15.4.2.5 ADC Input Model
          6. 6.15.4.2.6 ADC Timing Diagrams
      5. 6.15.5 Temperature Sensor
        1. 6.15.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.15.5.1.1 Temperature Sensor Characteristics
      6. 6.15.6 Comparator Subsystem (CMPSS)
        1. 6.15.6.1 CMPx_DACL
        2. 6.15.6.2 CMPSS Connectivity Diagram
        3. 6.15.6.3 Block Diagram
        4. 6.15.6.4 CMPSS Electrical Data and Timing
          1. 6.15.6.4.1 CMPSS Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.15.6.4.2 CMPSS DAC Static Electrical Characteristics
          4. 6.15.6.4.3 CMPSS Illustrative Graphs
          5. 6.15.6.4.4 Buffered Output from CMPx_DACL Operating Conditions
          6. 6.15.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics
      7. 6.15.7 Buffered Digital-to-Analog Converter (DAC)
        1. 6.15.7.1 Buffered DAC Electrical Data and Timing
          1. 6.15.7.1.1 Buffered DAC Operating Conditions
          2. 6.15.7.1.2 Buffered DAC Electrical Characteristics
      8. 6.15.8 Programmable Gain Amplifier (PGA)
        1. 6.15.8.1 PGA Electrical Data and Timing
          1. 6.15.8.1.1 PGA Operating Conditions
          2. 6.15.8.1.2 PGA Characteristics
    16. 6.16 Control Peripherals
      1. 6.16.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.16.1.1 Control Peripherals Synchronization
        2. 6.16.1.2 ePWM Electrical Data and Timing
          1. 6.16.1.2.1 ePWM Timing Requirements
          2. 6.16.1.2.2 ePWM Switching Characteristics
          3. 6.16.1.2.3 Trip-Zone Input Timing
            1. 6.16.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.16.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.16.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.16.2.1 HRPWM Electrical Data and Timing
          1. 6.16.2.1.1 High-Resolution PWM Characteristics
      3. 6.16.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.16.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.16.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.16.4 Enhanced Capture (eCAP)
        1. 6.16.4.1 eCAP Block Diagram
        2. 6.16.4.2 eCAP Synchronization
        3. 6.16.4.3 eCAP Electrical Data and Timing
          1. 6.16.4.3.1 eCAP Timing Requirements
          2. 6.16.4.3.2 eCAP Switching Characteristics
      5. 6.16.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.16.5.1 eQEP Electrical Data and Timing
          1. 6.16.5.1.1 eQEP Timing Requirements
          2. 6.16.5.1.2 eQEP Switching Characteristics
    17. 6.17 Communications Peripherals
      1. 6.17.1 Modular Controller Area Network (MCAN)
      2. 6.17.2 Inter-Integrated Circuit (I2C)
        1. 6.17.2.1 I2C Electrical Data and Timing
          1. 6.17.2.1.1 I2C Timing Requirements
          2. 6.17.2.1.2 I2C Switching Characteristics
          3. 6.17.2.1.3 I2C Timing Diagram
      3. 6.17.3 Power Management Bus (PMBus) Interface
        1. 6.17.3.1 PMBus Electrical Data and Timing
          1. 6.17.3.1.1 PMBus Electrical Characteristics
          2. 6.17.3.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.17.3.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.17.3.1.4 PMBus Standard Mode Switching Characteristics
      4. 6.17.4 Serial Communications Interface (SCI)
      5. 6.17.5 Serial Peripheral Interface (SPI)
        1. 6.17.5.1 SPI Controller Mode Timings
          1. 6.17.5.1.1 SPI Controller Mode Timing Requirements
          2. 6.17.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.17.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.17.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.17.5.2 SPI Peripheral Mode Timings
          1. 6.17.5.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.17.5.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.17.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.17.6 Local Interconnect Network (LIN)
      7. 6.17.7 Fast Serial Interface (FSI)
        1. 6.17.7.1 FSI Transmitter
          1. 6.17.7.1.1 FSITX Electrical Data and Timing
            1. 6.17.7.1.1.1 FSITX Switching Characteristics
            2. 6.17.7.1.1.2 FSITX Timings
        2. 6.17.7.2 FSI Receiver
          1. 6.17.7.2.1 FSIRX Electrical Data and Timing
            1. 6.17.7.2.1.1 FSIRX Timing Requirements
            2. 6.17.7.2.1.2 FSIRX Switching Characteristics
            3. 6.17.7.2.1.3 FSIRX Timings
        3. 6.17.7.3 FSI SPI Compatibility Mode
          1. 6.17.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.17.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.17.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 6.17.8 Universal Serial Bus (USB)
        1. 6.17.8.1 USB Electrical Data and Timing
          1. 6.17.8.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.17.8.1.2 USB Output Ports DP and DM Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Trigonometric Math Unit (TMU)
      3. 7.6.3 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Security
      1. 7.11.1 Securing the Boundary of the Chip
        1. 7.11.1.1 JTAGLOCK
        2. 7.11.1.2 Zero-pin Boot
      2. 7.11.2 Dual-Zone Security
      3. 7.11.3 Disclaimer
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2.     TAPE AND REEL INFORMATION
    3.     TRAY

5.4.1 GPIO Muxed Pins

Table 5-6 GPIO Muxed Pins
0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
GPIO0 EPWM1_A OUTPUTXBAR7 SCIA_RX I2CA_SDA SPIA_PTE FSIRXA_CLK MCANA_RX CLB_OUTPUTXBAR8 EQEP1_INDEX EPWM3_A
GPIO1 EPWM1_B SCIA_TX I2CA_SCL SPIA_POCI EQEP1_STROBE MCANA_TX CLB_OUTPUTXBAR7 EPWM10_B EPWM3_B
GPIO2 EPWM2_A OUTPUTXBAR1 PMBUSA_SDA SPIA_PICO SCIA_TX FSIRXA_D1 I2CB_SDA EPWM10_A MCANB_TX EPWM4_A
GPIO3 EPWM2_B OUTPUTXBAR2 OUTPUTXBAR2 PMBUSA_SCL SPIA_CLK SCIA_RX FSIRXA_D0 I2CB_SCL MCANB_RX EPWM4_B
GPIO4 EPWM3_A I2CA_SCL MCANA_TX OUTPUTXBAR3 SPIB_CLK EQEP2_STROBE FSIRXA_CLK CLB_OUTPUTXBAR6 EPWM11_B SPIA_POCI EPWM1_A
GPIO5 EPWM3_B I2CA_SDA OUTPUTXBAR3 MCANA_RX SPIA_PTE FSITXA_D1 CLB_OUTPUTXBAR5 SCIA_RX EPWM1_B
GPIO6 EPWM4_A OUTPUTXBAR4 SYNCOUT EQEP1_A SPIB_POCI FSITXA_D0 FSITXA_D1 CLB_OUTPUTXBAR8 EPWM2_A
GPIO7 EPWM4_B EPWM2_A OUTPUTXBAR5 EQEP1_B SPIB_PICO FSITXA_CLK CLB_OUTPUTXBAR2 SCIA_TX MCANA_TX EPWM2_B
GPIO8 EPWM5_A ADCSOCAO EQEP1_STROBE SCIA_TX SPIA_PICO I2CA_SCL FSITXA_D1 CLB_OUTPUTXBAR5 EPWM11_A
GPIO9 EPWM5_B SCIB_TX OUTPUTXBAR6 EQEP1_INDEX SCIA_RX SPIA_CLK I2CA_SCL FSITXA_D0 LINA_RX PMBUSA_SCL I2CB_SCL EQEP3_B
GPIO10 EPWM6_A ADCSOCBO EQEP1_A SCIB_TX SPIA_POCI I2CA_SDA FSITXA_CLK LINA_TX EQEP3_STROBE CLB_OUTPUTXBAR4
GPIO11 EPWM6_B MCANA_RX OUTPUTXBAR7 EQEP1_B SCIB_RX SPIA_PTE FSIRXA_D1 LINA_RX EQEP2_A SPIA_PICO EQEP3_INDEX
GPIO12 EPWM7_A MCANA_RX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0 LINA_TX SPIA_CLK
GPIO13 EPWM7_B MCANA_TX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK LINA_RX SPIA_POCI
GPIO14 EPWM8_A SCIB_TX I2CB_SDA OUTPUTXBAR3 PMBUSA_SDA SPIB_CLK EQEP2_A LINA_TX EPWM3_A CLB_OUTPUTXBAR7
GPIO15 EPWM8_B SCIB_RX I2CB_SCL OUTPUTXBAR4 PMBUSA_SCL SPIB_PTE EQEP2_B LINA_RX EPWM3_B CLB_OUTPUTXBAR6
GPIO16 SPIA_PICO OUTPUTXBAR7 EPWM9_A SCIA_TX EQEP1_STROBE PMBUSA_SCL XCLKOUT EQEP2_B SPIB_POCI EQEP3_STROBE
GPIO17 SPIA_POCI OUTPUTXBAR8 EPWM9_B SCIA_RX EQEP1_INDEX PMBUSA_SDA MCANA_TX EPWM6_A
GPIO18 SPIA_CLK SCIB_TX MCANB_RX EPWM6_A I2CA_SCL EQEP2_A PMBUSA_CTL XCLKOUT LINA_TX EQEP3_INDEX X2
GPIO19 SPIA_PTE SCIB_RX MCANB_TX EPWM6_B I2CA_SDA EQEP2_B PMBUSA_ALERT CLB_OUTPUTXBAR1 LINA_RX X1
GPIO20 EQEP1_A EPWM12_A SPIB_PICO MCANA_TX ADCE_EXTMUXSEL0 I2CA_SCL SCIC_TX
GPIO21 EQEP1_B EPWM12_B SPIB_POCI MCANA_RX ADCE_EXTMUXSEL1 I2CA_SDA SCIC_RX
GPIO22 EQEP1_STROBE SCIB_TX SPIB_CLK LINA_TX CLB_OUTPUTXBAR1 LINA_TX EPWM4_A EQEP3_A
GPIO23 EQEP1_INDEX SCIB_RX SPIB_PTE LINA_RX CLB_OUTPUTXBAR3 LINA_RX EPWM12_A EPWM4_B USB0DM
GPIO24 OUTPUTXBAR1 EQEP2_A SPIA_PTE EPWM8_A SPIB_PICO LINA_TX PMBUSA_SCL SCIA_TX ERRORSTS EPWM9_A
GPIO25 OUTPUTXBAR2 EQEP2_B EQEP1_A SPIB_POCI FSITXA_D1 PMBUSA_SDA SCIA_RX EQEP3_A
GPIO26 OUTPUTXBAR3 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK FSITXA_D0 PMBUSA_CTL I2CA_SDA EQEP3_B
GPIO27 OUTPUTXBAR4 EQEP2_STROBE OUTPUTXBAR4 SPIB_PTE FSITXA_CLK PMBUSA_ALERT I2CA_SCL EQEP3_STROBE
GPIO28 SCIA_RX EPWM7_A OUTPUTXBAR5 EQEP1_A EQEP2_STROBE LINA_TX SPIB_CLK ERRORSTS I2CB_SDA
GPIO29 SCIA_TX EPWM7_B OUTPUTXBAR6 EQEP1_B EQEP2_INDEX LINA_RX SPIB_PTE ERRORSTS I2CB_SCL AUXCLKIN
GPIO30 SPIB_PICO OUTPUTXBAR7 EQEP1_STROBE FSIRXA_CLK MCANA_RX EPWM1_A EQEP3_INDEX
GPIO31 SPIB_POCI OUTPUTXBAR8 EQEP1_INDEX FSIRXA_D1 MCANA_TX EPWM1_B
GPIO32 I2CA_SDA EQEP1_INDEX SPIB_CLK EPWM8_B LINA_TX FSIRXA_D0 MCANB_TX PMBUSA_SDA ADCSOCBO
GPIO33 I2CA_SCL SPIB_PTE OUTPUTXBAR4 LINA_RX FSIRXA_CLK MCANB_RX EQEP2_B ADCSOCAO SCIC_RX
GPIO34 OUTPUTXBAR1 PMBUSA_SDA I2CB_SDA
GPIO35 SCIA_RX SPIA_POCI I2CA_SDA MCANB_RX PMBUSA_SCL LINA_RX EQEP1_A PMBUSA_CTL EPWM5_B TDI
GPIO37 OUTPUTXBAR2 SPIA_PTE I2CA_SCL SCIA_TX MCANB_TX LINA_TX EQEP1_B PMBUSA_ALERT EPWM5_A TDO
GPIO40 SPIB_PICO EPWM2_B PMBUSA_SDA FSIRXA_D0 SCIB_TX EQEP1_A LINA_TX CLB_OUTPUTXBAR4 EQEP3_STROBE
GPIO41 EPWM7_A EPWM2_A PMBUSA_SCL FSIRXA_D1 SCIB_RX EQEP1_B LINA_RX EPWM12_B SPIB_POCI USB0DP
GPIO42 LINA_RX OUTPUTXBAR5 PMBUSA_CTL I2CA_SDA SCIC_RX EQEP1_STROBE CLB_OUTPUTXBAR3
GPIO43 OUTPUTXBAR6 PMBUSA_ALERT I2CA_SCL SCIC_TX PMBUSA_ALERT EQEP1_INDEX CLB_OUTPUTXBAR4
GPIO44 OUTPUTXBAR7 EQEP1_A PMBUSA_SDA FSITXA_CLK PMBUSA_CTL CLB_OUTPUTXBAR3 FSIRXA_D0 LINA_TX
GPIO45 OUTPUTXBAR8 FSITXA_D0 PMBUSA_ALERT CLB_OUTPUTXBAR4
GPIO46 LINA_TX MCANA_TX FSITXA_D1 PMBUSA_SDA
GPIO47 LINA_RX MCANA_RX CLB_OUTPUTXBAR2 PMBUSA_SCL
GPIO48 OUTPUTXBAR3 MCANA_TX SCIA_TX PMBUSA_SDA
GPIO49 OUTPUTXBAR4 MCANA_RX SCIA_RX LINA_RX FSITXA_D0
GPIO50 EQEP1_A MCANA_TX SPIB_PICO I2CB_SDA FSITXA_D1
GPIO51 EQEP1_B MCANA_RX SPIB_POCI I2CB_SCL FSITXA_CLK
GPIO52 EQEP1_STROBE CLB_OUTPUTXBAR5 SPIB_CLK SYNCOUT FSIRXA_D0
GPIO53 EQEP1_INDEX CLB_OUTPUTXBAR6 SPIB_PTE ADCSOCAO MCANB_RX FSIRXA_D1
GPIO54 SPIA_PICO EQEP2_A OUTPUTXBAR2 ADCSOCBO LINA_TX FSIRXA_CLK
GPIO55 SPIA_POCI EQEP2_B OUTPUTXBAR3 ERRORSTS LINA_RX
GPIO56 SPIA_CLK CLB_OUTPUTXBAR7 MCANA_TX EQEP2_STROBE SCIB_TX SPIB_PICO I2CA_SDA EQEP1_A FSIRXA_D1
GPIO57 SPIA_PTE CLB_OUTPUTXBAR8 MCANA_RX EQEP2_INDEX SCIB_RX SPIB_POCI I2CA_SCL EQEP1_B FSIRXA_CLK
GPIO58 OUTPUTXBAR1 SPIB_CLK LINA_TX MCANB_TX EQEP1_STROBE FSIRXA_D0
GPIO59 OUTPUTXBAR2 SPIB_PTE LINA_RX MCANB_RX EQEP1_INDEX
GPIO60 EPWM12_B MCANA_TX OUTPUTXBAR3 SPIB_PICO
GPIO61 MCANA_RX OUTPUTXBAR4 SPIB_POCI MCANB_RX
GPIO62 EPWM10_A OUTPUTXBAR3 MCANA_TX SCIA_TX PMBUSA_SDA
GPIO63 EPWM10_B OUTPUTXBAR4 MCANA_RX SCIA_RX LINA_RX
GPIO64 SCIA_RX EPWM11_A EPWM7_A OUTPUTXBAR5 EQEP1_A EQEP2_STROBE LINA_TX SPIB_CLK ERRORSTS I2CB_SDA
GPIO65 EQEP1_A EPWM11_B SPIB_PICO MCANA_TX I2CA_SCL
GPIO66 EQEP1_B EPWM12_A SPIB_POCI MCANA_RX I2CA_SDA
GPIO67 EPWM7_B EPWM12_B MCANA_TX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK LINA_RX SPIA_POCI SCIC_RX
GPIO68 EPWM7_A EPWM3_A MCANA_RX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0 LINA_TX SPIA_CLK SCIC_TX
GPIO69 EPWM6_B EPWM3_B OUTPUTXBAR7 EQEP1_B SCIB_RX SPIA_PTE FSIRXA_D1 LINA_RX EQEP2_A SPIA_PICO EQEP3_INDEX
GPIO70 I2CA_SCL SPIB_PTE OUTPUTXBAR4 LINA_RX FSIRXA_CLK MCANA_RX EQEP2_B ADCSOCAO EQEP3_A
GPIO71 SPIA_PICO EPWM4_B OUTPUTXBAR7 EPWM9_A SCIA_TX EQEP1_STROBE PMBUSA_SCL XCLKOUT EQEP2_INDEX SPIB_POCI EQEP3_STROBE
GPIO72 SPIA_POCI EPWM5_A OUTPUTXBAR8 EPWM9_B SCIA_RX EQEP1_INDEX PMBUSA_SDA MCANA_TX EPWM6_A EQEP3_B
GPIO73 OUTPUTXBAR1 EPWM5_B SPIA_PTE EPWM8_A SPIB_PICO LINA_TX PMBUSA_SCL SCIA_TX ERRORSTS EPWM9_A
GPIO74 EPWM2_B ADCSOCAO MCANA_TX SPIA_POCI EQEP1_B
GPIO75 EPWM1_B LINA_RX EPWM6_A SPIA_CLK EQEP1_STROBE SCIC_RX
GPIO76 EPWM4_A OUTPUTXBAR2 SPIA_PTE MCANA_RX EQEP1_INDEX
GPIO77 EPWM1_A OUTPUTXBAR3 SPIA_PICO MCANA_TX EQEP1_A SCIC_TX
GPIO78 EPWM8_A EPWM3_A OUTPUTXBAR1 EPWM2_B FSITXA_CLK
GPIO79 EPWM8_B EPWM3_B MCANA_RX EPWM2_A I2CA_SDA PMBUSA_SCL
GPIO80 EPWM1_A OUTPUTXBAR7 SCIA_RX I2CB_SDA SPIA_PTE FSITXA_D0 MCANA_RX CLB_OUTPUTXBAR8 EQEP1_INDEX EPWM3_A
GPIO81 EPWM1_B OUTPUTXBAR6 SCIC_RX SPIB_CLK I2CB_SCL FSITXA_D1 MCANA_TX EQEP3_INDEX
GPIO211 EPWM10_A EQEP3_A
GPIO212 EPWM10_B EQEP3_B
GPIO213 EPWM11_A EQEP3_STROBE
GPIO214 EPWM11_B EQEP3_INDEX
GPIO215 EPWM7_B EQEP2_A
GPIO224 EPWM11_B OUTPUTXBAR3 SPIA_PICO EPWM1_A MCANA_TX EQEP1_A ADCE_EXTMUXSEL3 SCIC_TX
GPIO226 EPWM10_B LINA_RX EPWM6_A SPIA_CLK EPWM1_B EQEP1_STROBE ADCE_EXTMUXSEL1 SCIC_RX
GPIO227 I2CB_SCL EPWM3_A OUTPUTXBAR1 EPWM2_B
GPIO228 EPWM10_A ADCSOCAO MCANA_TX SPIA_POCI EPWM2_B EQEP1_B ADCE_EXTMUXSEL0
GPIO230 I2CB_SDA EPWM3_B MCANA_RX EPWM2_A I2CA_SDA PMBUSA_SCL
GPIO236 EPWM7_A EQEP1_INDEX EPWM12_A
GPIO242 EPWM11_A OUTPUTXBAR2 SPIA_PTE EPWM4_A MCANA_RX EQEP1_INDEX ADCE_EXTMUXSEL2
GPIO247 EPWM12_B
GPIO253 EPWM12_A
AIO208
AIO209
AIO210
AIO225
AIO229
AIO231
AIO232
AIO233
AIO234
AIO235
AIO237
AIO238
AIO239
AIO240
AIO241
AIO244
AIO245
AIO248
AIO249
AIO251
AIO252