SPRSP85A April   2024  – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Reducing Current Consumption
        1. 6.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Special Considerations for 5V Fail-Safe Pins
    8. 6.8  Thermal Resistance Characteristics for PDT Package
    9. 6.9  Thermal Resistance Characteristics for PZ Package
    10. 6.10 Thermal Resistance Characteristics for PNA Package
    11. 6.11 Thermal Resistance Characteristics for PM Package
    12. 6.12 Thermal Resistance Characteristics for RSH Package
    13. 6.13 Thermal Design Considerations
    14. 6.14 System
      1. 6.14.1  Power Management Module (PMM)
        1. 6.14.1.1 Introduction
        2. 6.14.1.2 Overview
          1. 6.14.1.2.1 Power Rail Monitors
            1. 6.14.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.14.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.14.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.14.1.2.2 External Supervisor Usage
          3. 6.14.1.2.3 Delay Blocks
          4. 6.14.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.14.1.2.5 VREGENZ
        3. 6.14.1.3 External Components
          1. 6.14.1.3.1 Decoupling Capacitors
            1. 6.14.1.3.1.1 VDDIO Decoupling
            2. 6.14.1.3.1.2 VDD Decoupling
        4. 6.14.1.4 Power Sequencing
          1. 6.14.1.4.1 Supply Pins Ganging
          2. 6.14.1.4.2 Signal Pins Power Sequence
          3. 6.14.1.4.3 Supply Pins Power Sequence
            1. 6.14.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.14.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.14.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.14.1.4.3.4 Supply Slew Rate
        5. 6.14.1.5 Power Management Module Electrical Data and Timing
          1. 6.14.1.5.1 Power Management Module Operating Conditions
          2. 6.14.1.5.2 Power Management Module Characteristics
      2. 6.14.2  Reset Timing
        1. 6.14.2.1 Reset Sources
        2. 6.14.2.2 Reset Electrical Data and Timing
          1. 6.14.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.14.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.14.2.2.3 Reset Timing Diagrams
      3. 6.14.3  Clock Specifications
        1. 6.14.3.1 Clock Sources
        2. 6.14.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.14.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.14.3.2.1.1 Input Clock Frequency
            2. 6.14.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.14.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.14.3.2.1.4 X1 Timing Requirements
            5. 6.14.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.14.3.2.1.6 APLL Characteristics
            7. 6.14.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.14.3.2.1.8 Internal Clock Frequencies
        3. 6.14.3.3 Input Clocks and PLLs
        4. 6.14.3.4 XTAL Oscillator
          1. 6.14.3.4.1 Introduction
          2. 6.14.3.4.2 Overview
            1. 6.14.3.4.2.1 Electrical Oscillator
              1. 6.14.3.4.2.1.1 Modes of Operation
                1. 6.14.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.14.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.14.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.14.3.4.2.2 Quartz Crystal
            3. 6.14.3.4.2.3 GPIO Modes of Operation
          3. 6.14.3.4.3 Functional Operation
            1. 6.14.3.4.3.1 ESR – Effective Series Resistance
            2. 6.14.3.4.3.2 Rneg – Negative Resistance
            3. 6.14.3.4.3.3 Start-up Time
              1. 6.14.3.4.3.3.1 X1/X2 Precondition
            4. 6.14.3.4.3.4 DL – Drive Level
          4. 6.14.3.4.4 How to Choose a Crystal
          5. 6.14.3.4.5 Testing
          6. 6.14.3.4.6 Common Problems and Debug Tips
          7. 6.14.3.4.7 Crystal Oscillator Specifications
            1. 6.14.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.14.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.14.3.4.7.3 Crystal Oscillator Parameters
        5. 6.14.3.5 Internal Oscillators
          1. 6.14.3.5.1 INTOSC Characteristics
      4. 6.14.4  Flash Parameters
        1. 6.14.4.1 Flash Parameters 
      5. 6.14.5  RAM Specifications
      6. 6.14.6  ROM Specifications
      7. 6.14.7  Emulation/JTAG
        1. 6.14.7.1 JTAG Electrical Data and Timing
          1. 6.14.7.1.1 JTAG Timing Requirements
          2. 6.14.7.1.2 JTAG Switching Characteristics
          3. 6.14.7.1.3 JTAG Timing Diagram
        2. 6.14.7.2 cJTAG Electrical Data and Timing
          1. 6.14.7.2.1 cJTAG Timing Requirements
          2. 6.14.7.2.2 cJTAG Switching Characteristics
          3. 6.14.7.2.3 cJTAG Timing Diagram
      8. 6.14.8  GPIO Electrical Data and Timing
        1. 6.14.8.1 GPIO – Output Timing
          1. 6.14.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.14.8.1.2 General-Purpose Output Timing Diagram
        2. 6.14.8.2 GPIO – Input Timing
          1. 6.14.8.2.1 General-Purpose Input Timing Requirements
          2. 6.14.8.2.2 Sampling Mode
        3. 6.14.8.3 Sampling Window Width for Input Signals
      9. 6.14.9  Interrupts
        1. 6.14.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.14.9.1.1 External Interrupt Timing Requirements
          2. 6.14.9.1.2 External Interrupt Switching Characteristics
          3. 6.14.9.1.3 External Interrupt Timing
      10. 6.14.10 Low-Power Modes
        1. 6.14.10.1 Clock-Gating Low-Power Modes
        2. 6.14.10.2 Low-Power Mode Wake-up Timing
          1. 6.14.10.2.1 IDLE Mode Timing Requirements
          2. 6.14.10.2.2 IDLE Mode Switching Characteristics
          3. 6.14.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.14.10.2.4 STANDBY Mode Timing Requirements
          5. 6.14.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.14.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.14.10.2.7 HALT Mode Timing Requirements
          8. 6.14.10.2.8 HALT Mode Switching Characteristics
          9. 6.14.10.2.9 HALT Entry and Exit Timing Diagram
    15. 6.15 Analog Peripherals
      1. 6.15.1 Block Diagram
      2. 6.15.2 Analog Pins and Internal Connections
      3. 6.15.3 Analog Signal Descriptions
      4. 6.15.4 Analog-to-Digital Converter (ADC)
        1. 6.15.4.1 ADC Configurability
          1. 6.15.4.1.1 Signal Mode
        2. 6.15.4.2 ADC Electrical Data and Timing
          1. 6.15.4.2.1 ADC Operating Conditions
          2. 6.15.4.2.2 ADC Characteristics
          3. 6.15.4.2.3 ADC INL and DNL
          4. 6.15.4.2.4 ADC Performance Per Pin
          5. 6.15.4.2.5 ADC Input Model
          6. 6.15.4.2.6 ADC Timing Diagrams
      5. 6.15.5 Temperature Sensor
        1. 6.15.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.15.5.1.1 Temperature Sensor Characteristics
      6. 6.15.6 Comparator Subsystem (CMPSS)
        1. 6.15.6.1 CMPx_DACL
        2. 6.15.6.2 CMPSS Connectivity Diagram
        3. 6.15.6.3 Block Diagram
        4. 6.15.6.4 CMPSS Electrical Data and Timing
          1. 6.15.6.4.1 CMPSS Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.15.6.4.2 CMPSS DAC Static Electrical Characteristics
          4. 6.15.6.4.3 CMPSS Illustrative Graphs
          5. 6.15.6.4.4 Buffered Output from CMPx_DACL Operating Conditions
          6. 6.15.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics
      7. 6.15.7 Buffered Digital-to-Analog Converter (DAC)
        1. 6.15.7.1 Buffered DAC Electrical Data and Timing
          1. 6.15.7.1.1 Buffered DAC Operating Conditions
          2. 6.15.7.1.2 Buffered DAC Electrical Characteristics
      8. 6.15.8 Programmable Gain Amplifier (PGA)
        1. 6.15.8.1 PGA Electrical Data and Timing
          1. 6.15.8.1.1 PGA Operating Conditions
          2. 6.15.8.1.2 PGA Characteristics
    16. 6.16 Control Peripherals
      1. 6.16.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.16.1.1 Control Peripherals Synchronization
        2. 6.16.1.2 ePWM Electrical Data and Timing
          1. 6.16.1.2.1 ePWM Timing Requirements
          2. 6.16.1.2.2 ePWM Switching Characteristics
          3. 6.16.1.2.3 Trip-Zone Input Timing
            1. 6.16.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.16.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.16.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.16.2.1 HRPWM Electrical Data and Timing
          1. 6.16.2.1.1 High-Resolution PWM Characteristics
      3. 6.16.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.16.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.16.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.16.4 Enhanced Capture (eCAP)
        1. 6.16.4.1 eCAP Block Diagram
        2. 6.16.4.2 eCAP Synchronization
        3. 6.16.4.3 eCAP Electrical Data and Timing
          1. 6.16.4.3.1 eCAP Timing Requirements
          2. 6.16.4.3.2 eCAP Switching Characteristics
      5. 6.16.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.16.5.1 eQEP Electrical Data and Timing
          1. 6.16.5.1.1 eQEP Timing Requirements
          2. 6.16.5.1.2 eQEP Switching Characteristics
    17. 6.17 Communications Peripherals
      1. 6.17.1 Modular Controller Area Network (MCAN)
      2. 6.17.2 Inter-Integrated Circuit (I2C)
        1. 6.17.2.1 I2C Electrical Data and Timing
          1. 6.17.2.1.1 I2C Timing Requirements
          2. 6.17.2.1.2 I2C Switching Characteristics
          3. 6.17.2.1.3 I2C Timing Diagram
      3. 6.17.3 Power Management Bus (PMBus) Interface
        1. 6.17.3.1 PMBus Electrical Data and Timing
          1. 6.17.3.1.1 PMBus Electrical Characteristics
          2. 6.17.3.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.17.3.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.17.3.1.4 PMBus Standard Mode Switching Characteristics
      4. 6.17.4 Serial Communications Interface (SCI)
      5. 6.17.5 Serial Peripheral Interface (SPI)
        1. 6.17.5.1 SPI Controller Mode Timings
          1. 6.17.5.1.1 SPI Controller Mode Timing Requirements
          2. 6.17.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.17.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.17.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.17.5.2 SPI Peripheral Mode Timings
          1. 6.17.5.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.17.5.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.17.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.17.6 Local Interconnect Network (LIN)
      7. 6.17.7 Fast Serial Interface (FSI)
        1. 6.17.7.1 FSI Transmitter
          1. 6.17.7.1.1 FSITX Electrical Data and Timing
            1. 6.17.7.1.1.1 FSITX Switching Characteristics
            2. 6.17.7.1.1.2 FSITX Timings
        2. 6.17.7.2 FSI Receiver
          1. 6.17.7.2.1 FSIRX Electrical Data and Timing
            1. 6.17.7.2.1.1 FSIRX Timing Requirements
            2. 6.17.7.2.1.2 FSIRX Switching Characteristics
            3. 6.17.7.2.1.3 FSIRX Timings
        3. 6.17.7.3 FSI SPI Compatibility Mode
          1. 6.17.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.17.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.17.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 6.17.8 Universal Serial Bus (USB)
        1. 6.17.8.1 USB Electrical Data and Timing
          1. 6.17.8.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.17.8.1.2 USB Output Ports DP and DM Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Trigonometric Math Unit (TMU)
      3. 7.6.3 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Security
      1. 7.11.1 Securing the Boundary of the Chip
        1. 7.11.1.1 JTAGLOCK
        2. 7.11.1.2 Zero-pin Boot
      2. 7.11.2 Dual-Zone Security
      3. 7.11.3 Disclaimer
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2.     TAPE AND REEL INFORMATION
    3.     TRAY

5.3.2 Digital Signals

Table 5-3 Digital Signals
SIGNAL NAME PIN TYPE DESCRIPTION GPIO 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
ADCE_EXTMUXSEL0 O ADCE external mux selection pin for position 0 20, 228 18, 60 14, 48 10, 33 6, 27 24
ADCE_EXTMUXSEL1 O ADCE external mux selection pin for position 1 21, 226 19, 61 15, 49 11, 34 7, 28 25
ADCE_EXTMUXSEL2 O ADCE external mux selection pin for position 2 242 20 16 12 8 6
ADCE_EXTMUXSEL3 O ADCE external mux selection pin for position 3 224 21 17 13 9 7
ADCSOCAO O ADC Start of Conversion A for External ADC 8, 33, 53, 70, 74, 228 16, 18, 65, 74, 86, 95 12, 14, 53, 74 10, 38, 58 6, 32, 47 29
ADCSOCBO O ADC Start of Conversion B for External ADC 10, 32, 54 17, 79, 122 13, 64, 93 49, 76 40, 63 37
AUXCLKIN I Auxiliary Clock Input 29 1 100 3 1 2
CLB_OUTPUTXBAR1 O CLB Output X-BAR Output 1 19, 22 88, 104 69, 83 51, 67 42, 56 39, 51
CLB_OUTPUTXBAR2 O CLB Output X-BAR Output 2 7, 47 8, 105 6, 84 68 57 52
CLB_OUTPUTXBAR3 O CLB Output X-BAR Output 3 23, 42, 44 94, 102, 106 81, 85 57, 65, 69 54 49
CLB_OUTPUTXBAR4 O CLB Output X-BAR Output 4 10, 40, 43, 45 91, 101, 110, 122 80, 93 54, 64, 73, 76 53, 63 48
CLB_OUTPUTXBAR5 O CLB Output X-BAR Output 5 5, 8, 52 15, 95, 118 11, 74, 89 58, 74 47, 61 55
CLB_OUTPUTXBAR6 O CLB Output X-BAR Output 6 4, 15, 53 16, 96, 124 12, 75, 95 59, 78 48 43
CLB_OUTPUTXBAR7 O CLB Output X-BAR Output 7 1, 14, 56 80, 99, 125 65, 78, 96 62, 79 51 46
CLB_OUTPUTXBAR8 O CLB Output X-BAR Output 8 0, 6, 57, 80 81, 100, 116, 126 66, 79, 97 63, 80 52, 64 1, 47
EPWM1_A O ePWM-1 Output A 0, 4, 30, 77, 80, 224 21, 96, 100, 113, 116, 127 17, 75, 79, 98 1, 13, 59, 63 9, 48, 52 7, 43, 47
EPWM1_B O ePWM-1 Output B 1, 5, 31, 75, 81, 226 19, 99, 111, 117, 118, 128 15, 78, 89, 99 2, 11, 62, 74 7, 51, 61 46, 55
EPWM2_A O ePWM-2 Output A 2, 6, 7, 41, 79, 230 50, 98, 103, 105, 115, 126 40, 77, 82, 84, 97 29, 61, 66, 68, 80 25, 50, 55, 57, 64 1, 23, 45, 50, 52
EPWM2_B O ePWM-2 Output B 3, 7, 40, 74, 78, 227, 228 18, 48, 86, 97, 101, 105, 114 14, 38, 76, 80, 84 10, 28, 60, 64, 68 6, 24, 49, 53, 57 22, 44, 48, 52
EPWM3_A O ePWM-3 Output A 0, 4, 14, 68, 78, 80, 227 48, 72, 96, 100, 114, 116, 125 38, 75, 79, 96 28, 59, 63, 79 24, 48, 52 22, 43, 47
EPWM3_B O ePWM-3 Output B 1, 5, 15, 69, 79, 230 50, 73, 99, 115, 118, 124 40, 78, 89, 95 29, 62, 74, 78 25, 51, 61 23, 46, 55
EPWM4_A O ePWM-4 Output A 2, 6, 22, 76, 242 20, 98, 104, 112, 126 16, 77, 83, 97 12, 61, 67, 80 8, 50, 56, 64 1, 6, 45, 51
EPWM4_B O ePWM-4 Output B 3, 7, 23, 71 83, 97, 102, 105 76, 81, 84 60, 65, 68 49, 54, 57 44, 49, 52
EPWM5_A O ePWM-5 Output A 8, 37, 72 76, 84, 95 61, 74 46, 58 37, 47 34
EPWM5_B O ePWM-5 Output B 9, 35, 73 78, 85, 119 63, 90 48, 75 39, 62 36, 56
EPWM6_A O ePWM-6 Output A 10, 17, 18, 72, 75, 226 19, 67, 84, 87, 111, 122 15, 55, 68, 93 11, 40, 50, 76 7, 34, 41, 63 31, 38
EPWM6_B O ePWM-6 Output B 11, 19, 69 64, 73, 88 52, 69 37, 51 31, 42 28, 39
EPWM7_A O ePWM-7 Output A 12, 28, 41, 64, 68, 236 2, 49, 56, 63, 72, 103 1, 39, 51, 82 4, 28, 36, 66 2, 24, 30, 55 3, 22, 27, 50
EPWM7_B O ePWM-7 Output B 13, 29, 67, 215 1, 10, 47, 62 50, 100 3, 35 1, 29 2, 26
EPWM8_A O ePWM-8 Output A 14, 24, 73, 78 68, 85, 114, 125 56, 96 41, 79 35 32
EPWM8_B O ePWM-8 Output B 15, 32, 79 79, 115, 124 64, 95 49, 78 40 37
EPWM9_A O ePWM-9 Output A 16, 24, 71, 73 66, 68, 83, 85 54, 56 39, 41 33, 35 30, 32
EPWM9_B O ePWM-9 Output B 17, 72 67, 84 55 40 34 31
EPWM10_A O ePWM-10 Output A 2, 62, 211, 228 18, 43, 58, 98 14, 46, 77 10, 31, 61 6, 50 45
EPWM10_B O ePWM-10 Output B 1, 63, 212, 226 19, 44, 59, 99 15, 47, 78 11, 32, 62 7, 51 46
EPWM11_A O ePWM-11 Output A 8, 64, 213, 242 20, 45, 56, 95 16, 74 12, 58 8, 47 6
EPWM11_B O ePWM-11 Output B 4, 65, 214, 224 21, 46, 57, 96 17, 75 13, 59 9, 48 7, 43
EPWM12_A O ePWM-12 Output A 20, 23, 66, 236, 253 9, 49, 60, 102 39, 41, 48, 81 28, 33, 65 24, 27, 54 22, 24, 49
EPWM12_B O ePWM-12 Output B 21, 41, 60, 67, 247 10, 52, 61, 103 42, 44, 49, 82 34, 66 28, 55 25, 50
EQEP1_A I eQEP-1 Input A 6, 10, 20, 25, 28, 35, 40, 44, 50, 56, 64, 65, 77, 224 2, 13, 21, 56, 57, 60, 69, 78, 80, 101, 106, 113, 122, 126 1, 9, 17, 48, 57, 63, 65, 80, 85, 93, 97 4, 13, 33, 42, 48, 64, 69, 76, 80 2, 9, 27, 39, 53, 63, 64 1, 3, 7, 24, 36, 48
EQEP1_B I eQEP-1 Input B 7, 11, 21, 29, 37, 41, 51, 57, 66, 69, 74, 228 1, 9, 14, 18, 61, 64, 73, 76, 81, 86, 103, 105 10, 14, 49, 52, 61, 66, 82, 84, 100 3, 10, 34, 37, 46, 66, 68 1, 6, 28, 31, 37, 55, 57 2, 25, 28, 34, 50, 52
EQEP1_INDEX I/O eQEP-1 Index 0, 9, 13, 17, 23, 31, 32, 43, 53, 59, 67, 72, 76, 80, 236, 242 10, 16, 20, 49, 62, 67, 79, 84, 91, 100, 102, 112, 116, 119, 121, 128 12, 16, 39, 50, 55, 64, 79, 81, 90, 92, 99 2, 12, 28, 35, 40, 49, 54, 63, 65, 75 8, 24, 29, 34, 40, 52, 54, 62 6, 22, 26, 31, 37, 47, 49, 56
EQEP1_STROBE I/O eQEP-1 Strobe 1, 8, 12, 16, 22, 30, 42, 52, 58, 68, 71, 75, 226 15, 19, 63, 66, 72, 82, 83, 94, 95, 99, 104, 111, 127 11, 15, 51, 54, 67, 74, 78, 83, 98 1, 11, 36, 39, 57, 58, 62, 67 7, 30, 33, 47, 51, 56 27, 30, 46, 51
EQEP2_A I eQEP-2 Input A 11, 14, 18, 24, 54, 69, 215 17, 47, 64, 68, 73, 87, 125 13, 52, 56, 68, 96 37, 41, 50, 79 31, 35, 41 28, 32, 38
EQEP2_B I eQEP-2 Input B 15, 16, 19, 25, 33, 55, 70 51, 65, 66, 69, 74, 88, 124 43, 53, 54, 57, 69, 95 38, 39, 42, 51, 78 32, 33, 42 29, 30, 39
EQEP2_INDEX I/O eQEP-2 Index 26, 29, 57, 71 1, 70, 81, 83 58, 66, 100 3, 43 1 2
EQEP2_STROBE I/O eQEP-2 Strobe 4, 27, 28, 56, 64 2, 56, 71, 80, 96 1, 59, 65, 75 4, 44, 59 2, 48 3, 43
EQEP3_A I eQEP-3 Input A 22, 25, 70, 211 43, 69, 74, 104 57, 83 42, 67 56 51
EQEP3_B I eQEP-3 Input B 9, 26, 72, 212 44, 70, 84, 119 58, 90 43, 75 62 56
EQEP3_INDEX I/O eQEP-3 Index 11, 18, 30, 69, 81, 214 46, 64, 73, 87, 117, 127 52, 68, 98 1, 37, 50 31, 41 28, 38
EQEP3_STROBE I/O eQEP-3 Strobe 10, 16, 27, 40, 71, 213 45, 66, 71, 83, 101, 122 54, 59, 80, 93 39, 44, 64, 76 33, 53, 63 30, 48
ERRORSTS O Error Status Output. This signal requires an external pulldown. 24, 28, 29, 55, 64, 73 1, 2, 51, 56, 68, 85 1, 43, 56, 100 3, 4, 41 1, 2, 35 2, 3, 32
FSIRXA_CLK I FSIRX-A Input Clock 0, 4, 13, 30, 33, 54, 57, 67, 70 10, 17, 62, 65, 74, 81, 96, 100, 127 13, 50, 53, 66, 75, 79, 98 1, 35, 38, 59, 63 29, 32, 48, 52 26, 29, 43, 47
FSIRXA_D0 I FSIRX-A Primary Data Input 3, 12, 32, 40, 44, 52, 58, 68 15, 63, 72, 79, 82, 97, 101, 106 11, 51, 64, 67, 76, 80, 85 36, 49, 60, 64, 69 30, 40, 49, 53 27, 37, 44, 48
FSIRXA_D1 I FSIRX-A Optional Additional Data Input 2, 11, 31, 41, 53, 56, 69 16, 64, 73, 80, 98, 103, 128 12, 52, 65, 77, 82, 99 2, 37, 61, 66 31, 50, 55 28, 45, 50
FSITXA_CLK O FSITX-A Output Clock 7, 10, 27, 44, 51, 78 14, 71, 105, 106, 114, 122 10, 59, 84, 85, 93 44, 68, 69, 76 57, 63 52
FSITXA_D0 O FSITX-A Primary Data Output 6, 9, 26, 45, 49, 80 12, 70, 110, 116, 119, 126 8, 58, 90, 97 43, 73, 75, 80 62, 64 1, 56
FSITXA_D1 O FSITX-A Optional Additional Data Output 5, 6, 8, 25, 46, 50, 81 4, 13, 69, 95, 117, 118, 126 9, 57, 74, 89, 97 6, 42, 58, 74, 80 47, 61, 64 1, 55
GPIO0 I/O General-Purpose Input Output 0 0 100 79 63 52 47
GPIO1 I/O General-Purpose Input Output 1 1 99 78 62 51 46
GPIO2 I/O General-Purpose Input Output 2 2 98 77 61 50 45
GPIO3 I/O General-Purpose Input Output 3 3 97 76 60 49 44
GPIO4 I/O General-Purpose Input Output 4 4 96 75 59 48 43
GPIO5 I/O General-Purpose Input Output 5 5 118 89 74 61 55
GPIO6 I/O General-Purpose Input Output 6 6 126 97 80 64 1
GPIO7 I/O General-Purpose Input Output 7 7 105 84 68 57 52
GPIO8 I/O General-Purpose Input Output 8 8 95 74 58 47
GPIO9 I/O General-Purpose Input Output 9 9 119 90 75 62 56
GPIO10 I/O General-Purpose Input Output 10 10 122 93 76 63
GPIO11 I/O General-Purpose Input Output 11 11 64 52 37 31 28
GPIO12 I/O General-Purpose Input Output 12 12 63 51 36 30 27
GPIO13 I/O General-Purpose Input Output 13 13 62 50 35 29 26
GPIO14 I/O General-Purpose Input Output 14 14 125 96 79
GPIO15 I/O General-Purpose Input Output 15 15 124 95 78
GPIO16 I/O General-Purpose Input Output 16 16 66 54 39 33 30
GPIO17 I/O General-Purpose Input Output 17 17 67 55 40 34 31
GPIO18 I/O General-Purpose Input Output 18 18 87 68 50 41 38
GPIO19 I/O General-Purpose Input Output 19 19 88 69 51 42 39
GPIO20 I/O General-Purpose Input Output 20 20 60 48 33 27 24
GPIO21 I/O General-Purpose Input Output 21 21 61 49 34 28 25
GPIO22 I/O General-Purpose Input Output 22 22 104 83 67 56 51
GPIO23 I/O General-Purpose Input Output 23 23 102 81 65 54 49
GPIO24 I/O General-Purpose Input Output 24 24 68 56 41 35 32
GPIO25 I/O General-Purpose Input Output 25 25 69 57 42
GPIO26 I/O General-Purpose Input Output 26 26 70 58 43
GPIO27 I/O General-Purpose Input Output 27 27 71 59 44
GPIO28 I/O General-Purpose Input Output 28 28 2 1 4 2 3
GPIO29 I/O General-Purpose Input Output 29 29 1 100 3 1 2
GPIO30 I/O General-Purpose Input Output 30 30 127 98 1
GPIO31 I/O General-Purpose Input Output 31 31 128 99 2
GPIO32 I/O General-Purpose Input Output 32 32 79 64 49 40 37
GPIO33 I/O General-Purpose Input Output 33 33 65 53 38 32 29
GPIO34 I/O General-Purpose Input Output 34 34 123 94 77
GPIO35 I/O General-Purpose Input Output 35 35 78 63 48 39 36
GPIO37 I/O General-Purpose Input Output 37 37 76 61 46 37 34
GPIO40 I/O General-Purpose Input Output 40 40 101 80 64 53 48
GPIO41 I/O General-Purpose Input Output 41 41 103 82 66 55 50
GPIO42 I/O General-Purpose Input Output 42 42 94 57
GPIO43 I/O General-Purpose Input Output 43 43 91 54
GPIO44 I/O General-Purpose Input Output 44 44 106 85 69
GPIO45 I/O General-Purpose Input Output 45 45 110 73
GPIO46 I/O General-Purpose Input Output 46 46 4 6
GPIO47 I/O General-Purpose Input Output 47 47 8 6
GPIO48 I/O General-Purpose Input Output 48 48 11 7
GPIO49 I/O General-Purpose Input Output 49 49 12 8
GPIO50 I/O General-Purpose Input Output 50 50 13 9
GPIO51 I/O General-Purpose Input Output 51 51 14 10
GPIO52 I/O General-Purpose Input Output 52 52 15 11
GPIO53 I/O General-Purpose Input Output 53 53 16 12
GPIO54 I/O General-Purpose Input Output 54 54 17 13
GPIO55 I/O General-Purpose Input Output 55 55 51 43
GPIO56 I/O General-Purpose Input Output 56 56 80 65
GPIO57 I/O General-Purpose Input Output 57 57 81 66
GPIO58 I/O General-Purpose Input Output 58 58 82 67
GPIO59 I/O General-Purpose Input Output 59 59 121 92
GPIO60 I/O General-Purpose Input Output 60 60 52 44
GPIO61 I/O General-Purpose Input Output 61 61 120 91
GPIO62 I/O General-Purpose Input Output 62 62 58 46 31
GPIO63 I/O General-Purpose Input Output 63 63 59 47 32
GPIO64 I/O General-Purpose Input Output 64 64 56
GPIO65 I/O General-Purpose Input Output 65 65 57
GPIO66 I/O General-Purpose Input Output 66 66 9
GPIO67 I/O General-Purpose Input Output 67 67 10
GPIO68 I/O General-Purpose Input Output 68 68 72
GPIO69 I/O General-Purpose Input Output 69 69 73
GPIO70 I/O General-Purpose Input Output 70 70 74
GPIO71 I/O General-Purpose Input Output 71 71 83
GPIO72 I/O General-Purpose Input Output 72 72 84
GPIO73 I/O General-Purpose Input Output 73 73 85
GPIO74 I/O General-Purpose Input Output 74 74 86
GPIO75 I/O General-Purpose Input Output 75 75 111
GPIO76 I/O General-Purpose Input Output 76 76 112
GPIO77 I/O General-Purpose Input Output 77 77 113
GPIO78 I/O General-Purpose Input Output 78 78 114
GPIO79 I/O General-Purpose Input Output 79 79 115
GPIO80 I/O General-Purpose Input Output 80 80 116
GPIO81 I/O General-Purpose Input Output 81 81 117
GPIO211 I/O General-Purpose Input Output 211 211 43
GPIO212 I/O General-Purpose Input Output 212 212 44
GPIO213 I/O General-Purpose Input Output 213 213 45
GPIO214 I/O General-Purpose Input Output 214 214 46
GPIO215 I/O General-Purpose Input Output 215 215 47
GPIO224 I/O General-Purpose Input Output 224 224 21 17 13 9 7
GPIO226 I/O General-Purpose Input Output 226 226 19 15 11 7
GPIO227 I/O General-Purpose Input Output 227 227 48 38 28 24 22
GPIO228 I/O General-Purpose Input Output 228 228 18 14 10 6
GPIO230 I/O General-Purpose Input Output 230 230 50 40 29 25 23
GPIO236 I/O General-Purpose Input Output 236 236 49 39 28 24 22
GPIO242 I/O General-Purpose Input Output 242 242 20 16 12 8 6
GPIO247 I/O General-Purpose Input Output 247 247 42
GPIO253 I/O General-Purpose Input Output 253 253 41
I2CA_SCL I/OD I2C-A Open-Drain Bidirectional Clock 1, 4, 8, 9, 18, 20, 27, 33, 37, 43, 57, 65, 70 57, 60, 65, 71, 74, 76, 81, 87, 91, 95, 96, 99, 119 48, 53, 59, 61, 66, 68, 74, 75, 78, 90 33, 38, 44, 46, 50, 54, 58, 59, 62, 75 27, 32, 37, 41, 47, 48, 51, 62 24, 29, 34, 38, 43, 46, 56
I2CA_SDA I/OD I2C-A Open-Drain Bidirectional Data 0, 5, 10, 19, 21, 26, 32, 35, 42, 56, 66, 79, 230 9, 50, 61, 70, 78, 79, 80, 88, 94, 100, 115, 118, 122 40, 49, 58, 63, 64, 65, 69, 79, 89, 93 29, 34, 43, 48, 49, 51, 57, 63, 74, 76 25, 28, 39, 40, 42, 52, 61, 63 23, 25, 36, 37, 39, 47, 55
I2CB_SCL I/OD I2C-B Open-Drain Bidirectional Clock 3, 9, 15, 29, 51, 81, 227 1, 14, 48, 97, 117, 119, 124 10, 38, 76, 90, 95, 100 3, 28, 60, 75, 78 1, 24, 49, 62 2, 22, 44, 56
I2CB_SDA I/OD I2C-B Open-Drain Bidirectional Data 2, 14, 28, 34, 50, 64, 80, 230 2, 13, 50, 56, 98, 116, 123, 125 1, 9, 40, 77, 94, 96 4, 29, 61, 77, 79 2, 25, 50 3, 23, 45
LINA_RX I LIN-A Receive 9, 11, 13, 15, 19, 23, 29, 33, 35, 41, 42, 47, 49, 55, 59, 63, 67, 69, 70, 75, 226 1, 8, 10, 12, 19, 51, 59, 62, 64, 65, 73, 74, 78, 88, 94, 102, 103, 111, 119, 121, 124 6, 8, 15, 43, 47, 50, 52, 53, 63, 69, 81, 82, 90, 92, 95, 100 3, 11, 32, 35, 37, 38, 48, 51, 57, 65, 66, 75, 78 1, 7, 29, 31, 32, 39, 42, 54, 55, 62 2, 26, 28, 29, 36, 39, 49, 50, 56
LINA_TX O LIN-A Transmit 10, 12, 14, 18, 22, 24, 28, 32, 37, 40, 44, 46, 54, 58, 64, 68, 73 2, 4, 17, 56, 63, 68, 72, 76, 79, 82, 85, 87, 101, 104, 106, 122, 125 1, 13, 51, 56, 61, 64, 67, 68, 80, 83, 85, 93, 96 4, 6, 36, 41, 46, 49, 50, 64, 67, 69, 76, 79 2, 30, 35, 37, 40, 41, 53, 56, 63 3, 27, 32, 34, 37, 38, 48, 51
MCANA_RX I CAN/CAN FD Receive 0, 5, 11, 12, 21, 30, 47, 49, 51, 57, 61, 63, 66, 68, 70, 76, 79, 80, 230, 242 8, 9, 12, 14, 20, 50, 59, 61, 63, 64, 72, 74, 81, 100, 112, 115, 116, 118, 120, 127 6, 8, 10, 16, 40, 47, 49, 51, 52, 66, 79, 89, 91, 98 1, 12, 29, 32, 34, 36, 37, 63, 74 8, 25, 28, 30, 31, 52, 61 6, 23, 25, 27, 28, 47, 55
MCANA_TX O CAN/CAN FD Transmit 1, 4, 7, 13, 17, 20, 31, 46, 48, 50, 56, 60, 62, 65, 67, 72, 74, 77, 81, 224, 228 4, 10, 11, 13, 18, 21, 52, 57, 58, 60, 62, 67, 80, 84, 86, 96, 99, 105, 113, 117, 128 7, 9, 14, 17, 44, 46, 48, 50, 55, 65, 75, 78, 84, 99 2, 6, 10, 13, 31, 33, 35, 40, 59, 62, 68 6, 9, 27, 29, 34, 48, 51, 57 7, 24, 26, 31, 43, 46, 52
MCANB_RX I CAN/CAN FD Receive 3, 18, 33, 35, 53, 59, 61 16, 65, 78, 87, 97, 120, 121 12, 53, 63, 68, 76, 91, 92 38, 48, 50, 60 32, 39, 41, 49 29, 36, 38, 44
MCANB_TX O CAN/CAN FD Transmit 2, 19, 32, 37, 58 76, 79, 82, 88, 98 61, 64, 67, 69, 77 46, 49, 51, 61 37, 40, 42, 50 34, 37, 39, 45
OUTPUTXBAR1 O Output X-BAR Output 1 2, 24, 34, 58, 73, 78, 227 48, 68, 82, 85, 98, 114, 123 38, 56, 67, 77, 94 28, 41, 61, 77 24, 35, 50 22, 32, 45
OUTPUTXBAR2 O Output X-BAR Output 2 3, 25, 37, 54, 59, 76, 242 17, 20, 69, 76, 97, 112, 121 13, 16, 57, 61, 76, 92 12, 42, 46, 60 8, 37, 49 6, 34, 44
OUTPUTXBAR3 O Output X-BAR Output 3 4, 5, 14, 26, 48, 55, 60, 62, 77, 224 11, 21, 51, 52, 58, 70, 96, 113, 118, 125 7, 17, 43, 44, 46, 58, 75, 89, 96 13, 31, 43, 59, 74, 79 9, 48, 61 7, 43, 55
OUTPUTXBAR4 O Output X-BAR Output 4 6, 15, 27, 33, 49, 61, 63, 70 12, 59, 65, 71, 74, 120, 124, 126 8, 47, 53, 59, 91, 95, 97 32, 38, 44, 78, 80 32, 64 1, 29
OUTPUTXBAR5 O Output X-BAR Output 5 7, 28, 42, 64 2, 56, 94, 105 1, 84 4, 57, 68 2, 57 3, 52
OUTPUTXBAR6 O Output X-BAR Output 6 9, 29, 43, 81 1, 91, 117, 119 90, 100 3, 54, 75 1, 62 2, 56
OUTPUTXBAR7 O Output X-BAR Output 7 0, 11, 16, 30, 44, 69, 71, 80 64, 66, 73, 83, 100, 106, 116, 127 52, 54, 79, 85, 98 1, 37, 39, 63, 69 31, 33, 52 28, 30, 47
OUTPUTXBAR8 O Output X-BAR Output 8 17, 31, 45, 72 67, 84, 110, 128 55, 99 2, 40, 73 34 31
PMBUSA_ALERT I/OD PMBus-A Open-Drain Bidirectional Alert Signal 13, 19, 27, 37, 43, 45, 67 10, 62, 71, 76, 88, 91, 110 50, 59, 61, 69 35, 44, 46, 51, 54, 73 29, 37, 42 26, 34, 39
PMBUSA_CTL I/O PMBus-A Control Signal - Target Input/Controller Output 12, 18, 26, 35, 42, 44, 68 63, 70, 72, 78, 87, 94, 106 51, 58, 63, 68, 85 36, 43, 48, 50, 57, 69 30, 39, 41 27, 36, 38
PMBUSA_SCL I/OD PMBus-A Open-Drain Bidirectional Clock 3, 9, 15, 16, 24, 35, 41, 47, 71, 73, 79, 230 8, 50, 66, 68, 78, 83, 85, 97, 103, 115, 119, 124 6, 40, 54, 56, 63, 76, 82, 90, 95 29, 39, 41, 48, 60, 66, 75, 78 25, 33, 35, 39, 49, 55, 62 23, 30, 32, 36, 44, 50, 56
PMBUSA_SDA I/OD PMBus-A Open-Drain Bidirectional Data 2, 14, 17, 25, 32, 34, 40, 44, 46, 48, 62, 72 4, 11, 58, 67, 69, 79, 84, 98, 101, 106, 123, 125 7, 46, 55, 57, 64, 77, 80, 85, 94, 96 6, 31, 40, 42, 49, 61, 64, 69, 77, 79 34, 40, 50, 53 31, 37, 45, 48
SCIA_RX I SCI-A Receive Data 0, 3, 5, 9, 17, 25, 28, 35, 49, 63, 64, 72, 80 2, 12, 56, 59, 67, 69, 78, 84, 97, 100, 116, 118, 119 1, 8, 47, 55, 57, 63, 76, 79, 89, 90 4, 32, 40, 42, 48, 60, 63, 74, 75 2, 34, 39, 49, 52, 61, 62 3, 31, 36, 44, 47, 55, 56
SCIA_TX O SCI-A Transmit Data 1, 2, 7, 8, 16, 24, 29, 37, 48, 62, 71, 73 1, 11, 58, 66, 68, 76, 83, 85, 95, 98, 99, 105 7, 46, 54, 56, 61, 74, 77, 78, 84, 100 3, 31, 39, 41, 46, 58, 61, 62, 68 1, 33, 35, 37, 47, 50, 51, 57 2, 30, 32, 34, 45, 46, 52
SCIB_RX I SCI-B Receive Data 11, 13, 15, 19, 23, 41, 57, 67, 69 10, 62, 64, 73, 81, 88, 102, 103, 124 50, 52, 66, 69, 81, 82, 95 35, 37, 51, 65, 66, 78 29, 31, 42, 54, 55 26, 28, 39, 49, 50
SCIB_TX O SCI-B Transmit Data 9, 10, 12, 14, 18, 22, 40, 56, 68 63, 72, 80, 87, 101, 104, 119, 122, 125 51, 65, 68, 80, 83, 90, 93, 96 36, 50, 64, 67, 75, 76, 79 30, 41, 53, 56, 62, 63 27, 38, 48, 51, 56
SCIC_RX I SCI-C Receive Data 21, 33, 42, 67, 75, 81, 226 10, 19, 61, 65, 94, 111, 117 15, 49, 53 11, 34, 38, 57 7, 28, 32 25, 29
SCIC_TX O SCI-C Transmit Data 20, 43, 68, 77, 224 21, 60, 72, 91, 113 17, 48 13, 33, 54 9, 27 7, 24
SPIA_CLK I/O SPI-A Clock 3, 9, 12, 18, 56, 68, 75, 226 19, 63, 72, 80, 87, 97, 111, 119 15, 51, 65, 68, 76, 90 11, 36, 50, 60, 75 7, 30, 41, 49, 62 27, 38, 44, 56
SPIA_PICO I/O SPI-A Peripheral In, Controller Out (PICO) 2, 8, 11, 16, 54, 69, 71, 77, 224 17, 21, 64, 66, 73, 83, 95, 98, 113 13, 17, 52, 54, 74, 77 13, 37, 39, 58, 61 9, 31, 33, 47, 50 7, 28, 30, 45
SPIA_POCI I/O SPI-A Peripheral Out, Controller In (POCI) 1, 4, 10, 13, 17, 35, 55, 67, 72, 74, 228 10, 18, 51, 62, 67, 78, 84, 86, 96, 99, 122 14, 43, 50, 55, 63, 75, 78, 93 10, 35, 40, 48, 59, 62, 76 6, 29, 34, 39, 48, 51, 63 26, 31, 36, 43, 46
SPIA_PTE I/O SPI-A Peripheral Transmit Enable (PTE) 0, 5, 11, 19, 24, 37, 57, 69, 73, 76, 80, 242 20, 64, 68, 73, 76, 81, 85, 88, 100, 112, 116, 118 16, 52, 56, 61, 66, 69, 79, 89 12, 37, 41, 46, 51, 63, 74 8, 31, 35, 37, 42, 52, 61 6, 28, 32, 34, 39, 47, 55
SPIB_CLK I/O SPI-B Clock 4, 14, 22, 26, 28, 32, 52, 58, 64, 81 2, 15, 56, 70, 79, 82, 96, 104, 117, 125 1, 11, 58, 64, 67, 75, 83, 96 4, 43, 49, 59, 67, 79 2, 40, 48, 56 3, 37, 43, 51
SPIB_PICO I/O SPI-B Peripheral In, Controller Out (PICO) 7, 20, 24, 30, 40, 50, 56, 60, 65, 73 13, 52, 57, 60, 68, 80, 85, 101, 105, 127 9, 44, 48, 56, 65, 80, 84, 98 1, 33, 41, 64, 68 27, 35, 53, 57 24, 32, 48, 52
SPIB_POCI I/O SPI-B Peripheral Out, Controller In (POCI) 6, 16, 21, 25, 31, 41, 51, 57, 61, 66, 71 9, 14, 61, 66, 69, 81, 83, 103, 120, 126, 128 10, 49, 54, 57, 66, 82, 91, 97, 99 2, 34, 39, 42, 66, 80 28, 33, 55, 64 1, 25, 30, 50
SPIB_PTE I/O SPI-B Peripheral Transmit Enable (PTE) 15, 23, 27, 29, 33, 53, 59, 70 1, 16, 65, 71, 74, 102, 121, 124 12, 53, 59, 81, 92, 95, 100 3, 38, 44, 65, 78 1, 32, 54 2, 29, 49
SYNCOUT O External ePWM Synchronization Pulse 6, 52 15, 126 11, 97 80 64 1
TDI I JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. 35 78 63 48 39 36
TDO O JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. 37 76 61 46 37 34
USB0DM O USB-0 PHY differential data 23 102 81 65 54 49
USB0DP O USB-0 PHY differential data 41 103 82 66 55 50
X1 I/O Crystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. 19 88 69 51 42 39
X2 I/O Crystal oscillator output. 18 87 68 50 41 38
XCLKOUT O External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. 16, 18, 71 66, 83, 87 54, 68 39, 50 33, 41 30, 38