SPRSP85A April 2024 – September 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
PRODMIX
SIGNAL NAME | PIN TYPE | DESCRIPTION | 128 PDT | 100 PZ | 80 PNA | 64 PM | 56 RSH |
---|---|---|---|---|---|---|---|
VDD | 1.2-V Digital Logic Power Pins. TI recommends placing a decoupling capacitor near each VDD pin with a minimum total capacitance of approximately 10 µF. It is also recommended that all VDD pins be externally connected to each other when internal VREG is used. | 6, 54, 90, 108 | 4, 71, 87 | 8, 53, 71 | 4, 44, 59 | 5, 41, 53 | |
VDDA | 3.3-V Analog Power Pins. Place a minimum 2.2‑µF decoupling capacitor on each pin. | 41 | 34 | 26 | 22 | 20 | |
VDDIO | 3.3-V Digital I/O Power Pins. Place a minimum 0.1-µF decoupling capacitor on each pin. | 5, 55, 89, 109 | 3, 70, 88 | 7, 52, 72 | 43, 60 | 40, 54 | |
VREGENZ | I | Internal voltage regulator enable with internal pulldown. Tie low to VSS to enable internal VREG. Tie high to VDDIO to use an external supply. | 93 | 73 | 56 | 46 | 42 |
VSS | Digital Ground | 7, 53, 92, 107 | 5, 45, 72, 86 | 9, 30, 55, 70 | 5, 26, 45, 58 | PAD | |
VSSA | Analog Ground | 40 | 33 | 25 | 21 | 19 |