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AM69x Processors, Silicon Revision 1.0
SPRSP92D
February 2023 – December 2024
AM69
,
AM69A
PRODUCTION DATA
CONTENTS
SEARCH
AM69x Processors, Silicon Revision 1.0
1
1
Features
2
Applications
3
Description
3.1
Functional Block Diagram
4
Device Comparison
5
Terminal Configuration and Functions
5.1
Pin Diagrams
5.2
Pin Attributes
10
11
5.3
Signal Descriptions
13
5.3.1
ADC
5.3.1.1
MCU Domain
16
17
18
5.3.2
DDRSS
5.3.2.1
MAIN Domain
21
22
23
24
5.3.3
GPIO
5.3.3.1
MAIN Domain
27
5.3.3.2
WKUP Domain
29
5.3.4
I2C
5.3.4.1
MAIN Domain
32
33
34
35
36
37
38
5.3.4.2
MCU Domain
40
41
5.3.4.3
WKUP Domain
43
5.3.5
I3C
5.3.5.1
MCU Domain
46
5.3.6
MCAN
5.3.6.1
MAIN Domain
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
5.3.6.2
MCU Domain
68
69
5.3.7
MCSPI
5.3.7.1
MAIN Domain
72
73
74
75
76
77
78
5.3.7.2
MCU Domain
80
81
5.3.8
UART
5.3.8.1
MAIN Domain
84
85
86
87
88
89
90
91
92
93
5.3.8.2
MCU Domain
95
5.3.8.3
WKUP Domain
97
5.3.9
MDIO
5.3.9.1
MAIN Domain
100
101
5.3.9.2
MCU Domain
103
5.3.10
UFS
5.3.10.1
MAIN Domain
106
5.3.11
CPSW2G
5.3.11.1
MAIN Domain
109
5.3.11.2
MCU Domain
111
5.3.12
SGMII
5.3.12.1
MAIN Domain
114
5.3.13
ECAP
5.3.13.1
MAIN Domain
117
118
119
5.3.14
EQEP
5.3.14.1
MAIN Domain
122
123
124
5.3.15
EPWM
5.3.15.1
MAIN Domain
127
128
129
130
131
132
133
5.3.16
USB
5.3.16.1
MAIN Domain
136
5.3.17
Display Port
5.3.17.1
MAIN Domain
139
5.3.18
PCIE
5.3.18.1
MAIN Domain
142
5.3.19
SERDES
5.3.19.1
MAIN Domain
145
146
147
148
5.3.20
DSI
5.3.20.1
MAIN Domain
151
152
5.3.21
CSI
5.3.21.1
MAIN Domain
155
156
157
5.3.22
MCASP
5.3.22.1
MAIN Domain
160
161
162
163
164
5.3.23
DMTIMER
5.3.23.1
MAIN Domain
167
5.3.23.2
MCU Domain
169
5.3.24
CPTS
5.3.24.1
MAIN Domain
172
5.3.24.2
MCU Domain
174
5.3.25
DSS
5.3.25.1
MAIN Domain
177
5.3.26
GPMC
5.3.26.1
MAIN Domain
180
5.3.27
MMC
5.3.27.1
MAIN Domain
183
184
5.3.28
OSPI
5.3.28.1
MCU Domain
187
188
5.3.29
Hyperbus
5.3.29.1
MCU Domain
191
5.3.30
Emulation and Debug
5.3.30.1
MAIN Domain
194
195
5.3.31
System and Miscellaneous
5.3.31.1
Boot Mode configuration
198
5.3.31.2
Clock
200
201
5.3.31.3
System
203
204
5.3.31.4
EFUSE
206
5.3.31.5
VMON
208
5.3.32
Power
210
5.4
Pin Connectivity Requirements
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Power-On-Hour (POH) Limits
6.4
Recommended Operating Conditions
6.5
Operating Performance Points
6.6
Electrical Characteristics
6.6.1
I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics
6.6.2
Fail-Safe Reset (FS Reset) Electrical Characteristics
6.6.3
HFOSC/LFOSC Electrical Characteristics
6.6.4
eMMCPHY Electrical Characteristics
6.6.5
SDIO Electrical Characteristics
6.6.6
CSI2/DSI D-PHY Electrical Characteristics
6.6.7
ADC12B Electrical Characteristics
6.6.8
LVCMOS Electrical Characteristics
6.6.9
USB2PHY Electrical Characteristics
6.6.10
SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
6.6.11
UFS M-PHY Electrical Characteristics
6.6.12
eDP/DP AUX-PHY Electrical Characteristics
6.6.13
DDR0 Electrical Characteristics
6.7
VPP Specifications for One-Time Programmable (OTP) eFuses
6.7.1
Recommended Operating Conditions for OTP eFuse Programming
6.7.2
Hardware Requirements
6.7.3
Programming Sequence
6.7.4
Impact to Your Hardware Warranty
6.8
Thermal Resistance Characteristics
6.8.1
Thermal Resistance Characteristics for ALY Package
6.8.2
Thermal Resistance Characteristics for AND Package
6.9
Temperature Sensor Characteristics
6.10
Timing and Switching Characteristics
6.10.1
Timing Parameters and Information
6.10.2
Power Supply Sequencing
6.10.2.1
Power Supply Slew Rate Requirement
6.10.2.2
Combined MCU and Main Domains Power- Up Sequencing
6.10.2.3
Combined MCU and Main Domains Power- Down Sequencing
6.10.2.4
Isolated MCU and Main Domains Power- Up Sequencing
6.10.2.5
Isolated MCU and Main Domains Power- Down Sequencing
6.10.2.6
Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing
6.10.2.7
Independent MCU and Main Domains, Entry and Exit of DDR Retention State
6.10.2.8
Independent MCU and Main Domains, Entry and Exit of GPIO Retention Sequencing
6.10.3
System Timing
6.10.3.1
Reset Timing
6.10.3.2
Safety Signal Timing
6.10.3.3
Clock Timing
6.10.4
Clock Specifications
6.10.4.1
Input and Output Clocks / Oscillators
6.10.4.1.1
WKUP_OSC0 Internal Oscillator Clock Source
6.10.4.1.1.1
Load Capacitance
6.10.4.1.1.2
Shunt Capacitance
6.10.4.1.2
WKUP_OSC0 LVCMOS Digital Clock Source
6.10.4.1.3
Auxiliary OSC1 Internal Oscillator Clock Source
6.10.4.1.3.1
Load Capacitance
6.10.4.1.3.2
Shunt Capacitance
6.10.4.1.4
Auxiliary OSC1 LVCMOS Digital Clock Source
6.10.4.1.5
Auxiliary OSC1 Not Used
6.10.4.2
Output Clocks
6.10.4.3
PLLs
6.10.4.4
Module and Peripheral Clocks Frequencies
6.10.5
Peripherals
6.10.5.1
ATL
6.10.5.1.1
ATL_PCLK Timing Requirements
6.10.5.1.2
ATL_AWS[x] Timing Requirements
6.10.5.1.3
ATL_BWS[x] Timing Requirements
6.10.5.1.4
ATCLK[x] Switching Characteristics
6.10.5.2
CPSW2G
6.10.5.2.1
CPSW2G MDIO Interface Timings
6.10.5.2.2
CPSW2G RMII Timings
6.10.5.2.2.1
CPSW2G RMII[x]_REF_CLK Timing Requirements – RMII Mode
6.10.5.2.2.2
CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
6.10.5.2.2.3
CPSW2G RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode
6.10.5.2.3
CPSW2G RGMII Timings
6.10.5.2.3.1
RGMII[x]_RXC Timing Requirements – RGMII Mode
6.10.5.2.3.2
CPSW2G Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
6.10.5.2.3.3
CPSW2G RGMII[x]_TXC Switching Characteristics – RGMII Mode
6.10.5.2.3.4
RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode
6.10.5.3
CSI-2
6.10.5.4
DDRSS
6.10.5.5
DSS
6.10.5.6
eCAP
6.10.5.6.1
Timing Requirements for eCAP
6.10.5.6.2
Switching Characteristics for eCAP
6.10.5.7
EPWM
6.10.5.7.1
Timing Requirements for eHRPWM
6.10.5.7.2
Switching Characteristics for eHRPWM
6.10.5.8
eQEP
6.10.5.8.1
Timing Requirements for eQEP
6.10.5.8.2
Switching Characteristics for eQEP
6.10.5.9
GPIO
6.10.5.9.1
GPIO Timing Requirements
6.10.5.9.2
GPIO Switching Characteristics
6.10.5.10
GPMC
6.10.5.10.1
GPMC and NOR Flash — Synchronous Mode
6.10.5.10.1.1
GPMC and NOR Flash Timing Requirements — Synchronous Mode
6.10.5.10.1.2
GPMC and NOR Flash Switching Characteristics – Synchronous Mode
6.10.5.10.2
GPMC and NOR Flash — Asynchronous Mode
6.10.5.10.2.1
GPMC and NOR Flash Timing Requirements – Asynchronous Mode
6.10.5.10.2.2
GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
6.10.5.10.3
GPMC and NAND Flash — Asynchronous Mode
6.10.5.10.3.1
GPMC and NAND Flash Timing Requirements – Asynchronous Mode
6.10.5.10.3.2
GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
6.10.5.10.4
GPMC0 IOSET
6.10.5.11
HyperBus
6.10.5.11.1
Timing Requirements for HyperBus
6.10.5.11.2
HyperBus 166 MHz Switching Characteristics
6.10.5.11.3
HyperBus 100 MHz Switching Characteristics
6.10.5.12
I2C
6.10.5.13
I3C
6.10.5.14
MCAN
6.10.5.15
MCASP
6.10.5.16
MCSPI
6.10.5.16.1
MCSPI — Controller Mode
6.10.5.16.2
MCSPI — Peripheral Mode
6.10.5.17
MMCSD
6.10.5.17.1
MMC0 - eMMC Interface
6.10.5.17.1.1
Legacy SDR Mode
6.10.5.17.1.2
High Speed SDR Mode
6.10.5.17.1.3
High Speed DDR Mode
6.10.5.17.1.4
HS200 Mode
6.10.5.17.1.5
HS400 Mode
6.10.5.17.2
MMC1/2 - SD/SDIO Interface
6.10.5.17.2.1
Default Speed Mode
6.10.5.17.2.2
High Speed Mode
6.10.5.17.2.3
UHS–I SDR12 Mode
6.10.5.17.2.4
UHS–I SDR25 Mode
6.10.5.17.2.5
UHS–I SDR50 Mode
6.10.5.17.2.6
UHS–I DDR50 Mode
6.10.5.17.2.7
UHS–I SDR104 Mode
6.10.5.18
CPTS
6.10.5.18.1
CPTS Timing Requirements
6.10.5.18.2
CPTS Switching Characteristics
6.10.5.19
OSPI
6.10.5.19.1
OSPI0/1 PHY Mode
6.10.5.19.1.1
OSPI0/1 With PHY Data Training
6.10.5.19.1.2
OSPI Without Data Training
6.10.5.19.1.2.1
OSPI Timing Requirements – SDR Mode
6.10.5.19.1.2.2
OSPI Switching Characteristics – SDR Mode
6.10.5.19.1.2.3
OSPI Timing Requirements – DDR Mode
6.10.5.19.1.2.4
OSPI Switching Characteristics – PHY DDR Mode
6.10.5.19.2
OSPI0/1 Tap Mode
6.10.5.19.2.1
OSPI0 Tap SDR Timing
6.10.5.19.2.2
OSPI0 Tap DDR Timing
6.10.5.20
OLDI
6.10.5.20.1
OLDI Switching Characteristics
6.10.5.21
PCIE
6.10.5.22
Timers
6.10.5.22.1
Timing Requirements for Timers
6.10.5.22.2
Switching Characteristics for Timers
6.10.5.23
UART
6.10.5.23.1
Timing Requirements for UART
6.10.5.23.2
UART Switching Characteristics
6.10.5.24
USB
6.10.6
Emulation and Debug
6.10.6.1
Trace
6.10.6.2
JTAG
6.10.6.2.1
JTAG Electrical Data and Timing
6.10.6.2.1.1
JTAG Timing Requirements
6.10.6.2.1.2
JTAG Switching Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Processor Subsystems
7.3.1
Arm Cortex-A72
7.3.2
Arm Cortex-R5F
7.3.3
DSP C71x
7.4
Accelerators and Coprocessors
7.4.1
GPU
7.4.2
VPAC
7.4.3
DMPAC
7.5
Other Subsystems
7.5.1
MSMC
7.5.2
NAVSS
7.5.2.1
NAVSS0
7.5.2.2
MCU_NAVSS
7.5.3
PDMA Controller
7.5.4
Power Supply
7.5.5
Peripherals
7.5.5.1
ADC
7.5.5.2
ATL
7.5.5.3
CSI
7.5.5.3.1
Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
7.5.5.3.2
Camera Streaming Interface Transmitter (CSI_TX_IF)
7.5.5.4
CPSW2G
7.5.5.5
CPSW9G
7.5.5.6
DCC
7.5.5.7
DDRSS
7.5.5.8
DSS
7.5.5.8.1
DSI
7.5.5.8.2
eDP
7.5.5.9
eCAP
7.5.5.10
EPWM
7.5.5.11
ELM
7.5.5.12
ESM
7.5.5.13
eQEP
7.5.5.14
GPIO
7.5.5.15
GPMC
7.5.5.16
Hyperbus
7.5.5.17
I2C
7.5.5.18
I3C
7.5.5.19
MCAN
7.5.5.20
MCASP
7.5.5.21
MCRC Controller
7.5.5.22
MCSPI
7.5.5.23
MMC/SD
7.5.5.24
OSPI
7.5.5.25
PCIE
7.5.5.26
SerDes
7.5.5.27
WWDT
7.5.5.28
Timers
7.5.5.29
UART
7.5.5.30
USB
7.5.5.31
UFS
8
Applications, Implementation, and Layout
9
Device Connection and Layout Fundamentals
9.1
Power Supply Decoupling and Bulk Capacitors
9.1.1
Power Distribution Network Implementation Guidance
9.2
External Oscillator
9.3
JTAG and EMU
9.4
Reset
9.5
Unused Pins
9.6
Hardware Design Guide for JacintoTM 7 Devices
10
Peripheral- and Interface-Specific Design Information
10.1
LPDDR4 Board Design and Layout Guidelines
10.2
OSPI and QSPI Board Design and Layout Guidelines
10.2.1
No Loopback and Internal Pad Loopback
10.2.2
External Board Loopback
10.2.3
DQS (only available in Octal Flash devices)
10.3
USB VBUS Design Guidelines
10.4
System Power Supply Monitor Design Guidelines using VMON/POK
10.5
High Speed Differential Signal Routing Guidance
10.6
Thermal Solution Guidance
11
Device and Documentation Support
11.1
Device Nomenclature
11.1.1
Standard Package Symbolization
11.1.2
Device Naming Convention
11.2
Tools and Software
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Revision History
13
Mechanical, Packaging, and Orderable Information
13.1
Packaging Information
IMPORTANT NOTICE
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AM69x Processors, Silicon Revision 1.0
