6.9.5.19.1.1 OSPI0 With PHY Data Training

Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating frequency. A data training method may be implemented to dynamically configure optimal read and write timing. Implementing data training enables proper operation across temperature with a specific process, voltage, and frequency operating condition, while achieving a higher operating frequency.

Data transmit and receive timing parameters are not defined for the data training use case since they are dynamically adjusted based on the operating condition.

Table 6-113 defines DLL delays required for OSPI0 with Data Training. Table 6-114, Figure 6-95, Figure 6-96, Table 6-115, Figure 6-97, and Figure 6-98 present timing requirements and switching characteristics for OSPI0 with Data Training.

Table 6-113 OSPI0 DLL Delay Mapping for PHY Data Training

MODE	OSPI_PHY_CONFIGURATION_REG BIT FIELD	DELAY VALUE
Transmit
All modes	PHY_CONFIG_TX_DLL_DELAY_FLD	⁽¹⁾
Receive
All modes	PHY_CONFIG_RX_DLL_DELAY_FLD	⁽²⁾

(1) Transmit DLL delay value determined by training software

(2) Receive DLL delay value determined by training software

Table 6-114 OSPI0 Timing Requirements – PHY Data Training see Figure 6-95, and Figure 6-96

NO.			MODE	MIN	UNIT
O15	t_su(D-LBCLK)	Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge	DDR with DQS	⁽¹⁾	ns
O16	t_h(LBCLK-D)	Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge	DDR with DQS	⁽¹⁾	ns
O21	t_su(D-LBCLK)	Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge	SDR with External Board Loopback	⁽¹⁾	ns
O22	t_h(LBCLK-D)	Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge	SDR with External Board Loopback	⁽¹⁾	ns
	t_DVW	Data valid window (O15 + O16)	1.8V, DDR with DQS	1.6	ns
		Data valid window (O15 + O16)	3.3V, DDR with DQS	2.2	ns
		Data valid window (O21 + O22)	1.8V, SDR with External Board Loopback	2.3	ns
		Data valid window (O21 + O22)	3.3V, SDR with External Board Loopback	2.9	ns

(1) Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum data valid window. The t_DVW parameter defines the minimum data invalid window required. This parameter is provided in lieu of minimum setup and minimum hold times, where it must be used to check compatibility with the data valid window provided by an attached device.

TDA4VEN-Q1 TDA4AEN-Q1 OSPI0
Timing Requirements – PHY Data Training, DDR with DQS

Figure 6-95 OSPI0 Timing Requirements – PHY Data Training, DDR with DQS

TDA4VEN-Q1 TDA4AEN-Q1 OSPI0
Timing Requirements – PHY Data Training, SDR with External Board
Loopback

Figure 6-96 OSPI0 Timing Requirements – PHY Data Training, SDR with External Board Loopback

Table 6-115 OSPI Switching Characteristics – PHY Data Training See Figure 6-97 and Figure 6-98

NO.	PARAMETER		MODE	MIN	MAX	UNIT
O1	t_c(CLK)	Cycle time, OSPI0_CLK	1.8V, DDR	6.0	10	ns
O1			3.3V, DDR	7.5	10	ns
O7			1.8V, SDR	6.0	10	ns
O7			3.3V, SDR	7.5	10	ns
O2	t_w(CLKL)	Pulse duration, OSPI0_CLK low	DDR	((0.475P⁽¹⁾) - 0.3)		ns
O8	t_w(CLKL)	Pulse duration, OSPI0_CLK low	SDR	((0.475P⁽¹⁾) - 0.3)		ns
O3	t_w(CLKH)	Pulse duration, OSPI0_CLK high	DDR	((0.475P⁽¹⁾) - 0.3)		ns
O9	t_w(CLKH)	Pulse duration, OSPI0_CLK high	SDR	((0.475P⁽¹⁾) - 0.3)		ns
O4	t_d(CSn-CLK)	Delay time, OSPI0_CSn[3:0] active edge to OSPI0_CLK rising edge	DDR	((0.475P⁽¹⁾) + (0.975M⁽²⁾R⁽⁴⁾) + (0.04TD⁽⁵⁾) - 1)	((0.525P⁽¹⁾) + (1.025M⁽²⁾R⁽⁴⁾) + (0.11TD⁽⁵⁾) + 1)	ns
O10	t_d(CSn-CLK)		SDR	((0.475P⁽¹⁾) + (0.975M⁽²⁾R⁽⁴⁾) + (0.04TD⁽⁵⁾) - 1)	((0.525P⁽¹⁾) + (1.025M⁽²⁾R⁽⁴⁾) + (0.11TD⁽⁵⁾) + 1)	ns
O5	t_d(CLK-CSn)	Delay time, OSPI0_CLK rising edge to OSPI0_CSn[3:0] inactive edge	DDR	((0.475P⁽¹⁾) + (0.975N⁽³⁾R⁽⁴⁾) - (0.04TD⁽⁵⁾) - 1)	((0.525P⁽¹⁾) + (1.025N⁽³⁾R⁽⁴⁾) - (0.11TD⁽⁵⁾) + 1)	ns
O11	t_d(CLK-CSn)		SDR	((0.475P⁽¹⁾) + (0.975N⁽³⁾R⁽⁴⁾) - (0.04TD⁽⁵⁾) - 1)	((0.525P⁽¹⁾) + (1.025N⁽³⁾R⁽⁴⁾) - (0.11TD⁽⁵⁾) + 1)	ns
O6	t_d(CLK-D)	Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition	DDR	⁽⁶⁾	⁽⁶⁾	ns
O12	t_d(CLK-D)		SDR	⁽⁶⁾	⁽⁶⁾	ns
	t_DIVW	Data invalid window (O6 Max - Min)	DDR		1.6	ns
	t_DIVW	Data invalid window (O12 Max - Min)	SDR		1.6	ns

(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4) R = reference clock cycle time in ns

(5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD

(6) Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data valid window. The t_DIVW parameter defines the maximum data invalid window. This parameter is provided in lieu of minimum and maximum delay times, where it must be used to check compatibility with the data valid window requirements of an attached device.

TDA4VEN-Q1 TDA4AEN-Q1 OSPI0 Switching Characteristics – PHY DDR Data
Training

Figure 6-97 OSPI0 Switching Characteristics – PHY DDR Data Training

TDA4VEN-Q1 TDA4AEN-Q1 OSPI0 Switching Characteristics – PHY SDR Data
Training

Figure 6-98 OSPI0 Switching Characteristics – PHY SDR Data Training