6.9.5.2.3 CPSW3G RGMII Timing

Table 6-35, Table 6-36, Table 6-37, Figure 6-31, Table 6-38, Table 6-39, and Figure 6-32 present timing conditions, timing requirements, and switching characteristics for CPSW3G RGMII.

Table 6-35 CPSW3G RGMII Timing Conditions

PARAMETER			MIN	MAX	UNIT
INPUT CONDITIONS
SR_I	Input slew rate	VDD⁽¹⁾ = 1.8V	1.44	5	V/ns
SR_I	Input slew rate	VDD⁽¹⁾ = 3.3V	2.64	5	V/ns
OUTPUT CONDITIONS
C_L	Output load capacitance		2	20	pF
PCB CONNECTIVITY REQUIREMENTS
t_{d(Trace Mismatch Delay)}	Propagation delay mismatch across all traces	RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL		50	ps
t_{d(Trace Mismatch Delay)}	Propagation delay mismatch across all traces	RGMII[x]_TXC, RGMII[x]_TD[3:0], RGMII[x]_TX_CTL		50	ps

(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table.

Table 6-36 RGMII[x]_RXC Timing Requirements – RGMII Mode see Figure 6-31

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
RGMII1	t_c(RXC)	Cycle time, RGMII[x]_RXC	10Mbps	360	440	ns
			100Mbps	36	44	ns
			1000Mbps	7.2	8.8	ns
RGMII2	t_w(RXCH)	Pulse duration, RGMII[x]_RXC high	10Mbps	160	240	ns
			100Mbps	16	24	ns
			1000Mbps	3.6	4.4	ns
RGMII3	t_w(RXCL)	Pulse duration, RGMII[x]_RXC low	10Mbps	160	240	ns
			100Mbps	16	24	ns
			1000Mbps	3.6	4.4	ns

Table 6-37 RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements – RGMII Mode see Figure 6-31

NO.	PARAMETER	DESCRIPTION	MODE	MIN	UNIT
RGMII4	t_su(RD-RXC)	Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC high/low	10Mbps	1	ns
			100Mbps	1	ns
			1000Mbps	1	ns
	t_{su(RX_CTL-RXC)}	Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC high/low	10Mbps	1	ns
			100Mbps	1	ns
			1000Mbps	1	ns
RGMII5	t_h(RXC-RD)	Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC high/low	10Mbps	1	ns
			100Mbps	1	ns
			1000Mbps	1	ns
	t_{h(RXC-RX_CTL)}	Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC high/low	10Mbps	1	ns
			100Mbps	1	ns
			1000Mbps	1	ns

TDA4VEN-Q1 TDA4AEN-Q1 CPSW3G
RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII
Mode

A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.

B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.

Figure 6-31 CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII Mode

Table 6-38 RGMII[x]_TXC Switching Characteristics – RGMII Mode see Figure 6-32

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
RGMII6	t_c(TXC)	Cycle time, RGMII[x]_TXC	10Mbps	360	440	ns
			100Mbps	36	44	ns
			1000Mbps	7.2	8.8	ns
RGMII7	t_w(TXCH)	Pulse duration, RGMII[x]_TXC high	10Mbps	160	240	ns
			100Mbps	16	24	ns
			1000Mbps	3.6	4.4	ns
RGMII8	t_w(TXCL)	Pulse duration, RGMII[x]_TXC low	10Mbps	160	240	ns
			100Mbps	16	24	ns
			1000Mbps	3.6	4.4	ns

Table 6-39 RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode see Figure 6-32

NO.	PARAMETER	DESCRIPTION	MODE	MIN	UNIT
RGMII9	t_osu(TD-TXC)	Output setup time⁽¹⁾, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC high/low	10Mbps	1.2	ns
			100Mbps	1.2	ns
			1000Mbps	1.2	ns
	t_{osu(TX_CTL-TXC)}	Output setup time⁽¹⁾, RGMII[x]_TX_CTL valid to RGMII[x]_TXC high/low	10Mbps	1.2	ns
			100Mbps	1.2	ns
			1000Mbps	1.2	ns
RGMII10	t_oh(TXC-TD)	Output hold time⁽¹⁾, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC high/low	10Mbps	1.2	ns
			100Mbps	1.2	ns
			1000Mbps	1.2	ns
	t_{oh(TXC-TX_CTL)}	Output hold time⁽¹⁾, RGMII[x]_TX_CTL valid after RGMII[x]_TXC high/low	10Mbps	1.2	ns
			100Mbps	1.2	ns
			1000Mbps	1.2	ns

(1) Output setup/hold times are defining a delay relationship of the transmit data and control outputs relative to the transmit clock output, but this output relationship is being presented as the minimum setup/hold times provided to the attached receiver. This approach matches how the output timing relationships are defined in the RGMII specification.

TDA4VEN-Q1 TDA4AEN-Q1 CPSW3G
RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics -
RGMII Mode

A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.

B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.

Figure 6-32 CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics - RGMII Mode