SPRSP98A November   2023  – June 2024 AM625SIP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes and Signal Descriptions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Operating Performance Points
    5. 6.5 Thermal Resistance Characteristics
      1. 6.5.1 Thermal Resistance Characteristics for AMK Package
    6. 6.6 Timing and Switching Characteristics
      1. 6.6.1 Power Supply Requirements
        1. 6.6.1.1 Power Supply Sequencing
  8. 7 Applications, Implementation, and Layout
    1. 7.1 Peripheral- and Interface-Specific Design Information
      1. 7.1.1 Integrated LPDDR4 SDRAM Information
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

6.5.1 Thermal Resistance Characteristics for AMK Package

It is recommended to perform thermal simulations at the system level with the worst case device power consumption.
NO. PARAMETER DESCRIPTION AMK
PACKAGE
°C/W(1)(2)		 AIR
FLOW
(m/s)(3)
T1 RΘJC Junction-to-case 5.1 N/A
T2 RΘJB Junction-to-board 5.2 N/A
T3 RΘJA Junction-to-free air 18.7 0
T4 Junction-to-moving air 12.6 1
T5 11.5 2
T6 11.0 3
T7 ΨJT Junction-to-package top 0.3 0
T8 0.4 1
T9 0.5 2
T10 0.5 3
T11 ΨJB Junction-to-board 5.1 0
T12 4.8 1
T13 4.7 2
T14 4.7 3
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:
  • JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
  • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
  • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-9, Test Boards for Area Array Surface Mount Packages
(3) m/s = meters per second.