SPRT759A October   2023  – June 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4.   Introduction
  5.   Overview of IEC 60730 and UL 1998 Classifications
    1.     C2000 Capability by Device Family
  6.   C2000 Safety Collateral
    1.     Getting Started
    2.     Functional Safety Manuals
    3.     Software Collateral
  7.   Implementing Acceptable Measures on C2000 Real-Time MCUs
    1.     Implementation Steps
    2.     Example Mapping
    3.     Additional Best Practices
  8.   Mapping Acceptable Control Measures to C2000 Unique Identifiers
    1.     Unique Identifier Reference
    2.     CPU Related Faults
    3.     Interrupt Related Faults
    4.     Clock Related Faults
    5.     Memory Related Faults
    6.     Internal Data Path Faults
    7.     Input/Output Related Faults
    8.     Communication, Monitoring Devices, and Custom Chip Faults
  9.   Glossary
  10.   References

CPU Related Faults

Table 9 CPU Faults
CPU
Component		 Class B/1 (1) Class C/2 (1) Acceptable Measure (2) C2000 Unique IDs (3)
Definition Description F2837x
F2807x		 F2838x F28004x F28002x F28003x F280013x F280015x
1.1 Registers rq H.2.16.5
A5.5		 Functional test - - CPU3 - - - CPU3
CLA2 CLA2 CLA2 - CLA2 - -
H.2.16.6
A5.6		 Periodic self-test CPU2 CPU2 - CPU2 CPU2 - -
CLA2 CLA2 CLA2 - CLA2 - -
- - - - - STL_CPU_REG (4) -
rq H.2.18.15
A7.1.19		 Reciprocal comparison CPU1 CPU1 CPU1 - CPU1 - -
CLA1 CLA1 CLA1 - CLA1 - -
H.2.18.3
A7.1.6		 Independent hardware comparator - - - - - - CPU21
H.2.18.9
A7.1.10		 Internal error detection CPU2 CPU2 - CPU2 CPU2 - -
1.2 Instruction decode
and execution		 rq H.2.18.15
A7.1.19		 Reciprocal comparison CPU1 CPU1 CPU1 - CPU1 - -
CLA1 CLA1 CLA1 - CLA1 - -
H.2.18.3
A7.1.6		 Independent hardware comparator - - - - - - CPU21
H.2.18.9
A7.1.10		 Internal error detection CPU2 CPU2 - CPU2 CPU2 - -
CPU7 CPU7 CPU7 CPU7 CPU7 CPU7 CPU7
CLA3 CLA3 CLA3 - CLA3 - -
1.3 Program counter rq H.2.16.5
A5.5		 Functional test - - CPU3 - - - CPU3
CLA2 CLA2 CLA2 - CLA2 - -
H.2.16.6
A5.6		 Periodic self-test CPU2 CPU2 - CPU2 CPU2 - -
H.2.18.10.4
A7.1.13		 Time slot monitoring PIE8 PIE8 PIE8 PIE8 PIE8 PIE8 PIE8
rq H.2.18.10.3
A7.1.14		 Independent time-slot monitoring and logical monitoring PIE8 PIE8 PIE8 PIE8 PIE8 PIE8 PIE8
H.2.18.15
A7.1.19		 Reciprocal comparison CPU1 CPU1 CPU1 - CPU1 - -
CLA1 CLA1 CLA1 - CLA1 - -
H.2.18.3
A7.1.6		 Independent hardware comparator - - - - - - CPU21
1.4 Addressing rq H.2.18.15
A7.1.19		 Reciprocal comparison CPU1 CPU1 CPU1 - CPU1 - -
CLA1 CLA1 CLA1 - CLA1 - -
H.2.18.3
A7.1.6		 Independent HW comparator - - - - - - CPU21
H.2.18.9
A7.1.10		 Internal error detection CPU2 CPU2 - CPU2 CPU2 - -
1.5 Data paths rq H.2.18.15
A7.1.19		 Reciprocal comparison CPU1 CPU1 CPU1 - CPU1 - -
CLA1 CLA1 CLA1 - CLA1 - -
H.2.18.3
A7.1.6		 Independent hardware comparator - - - - - - CPU21
H.2.18.9
A7.1.10		 Internal error detection CPU2 CPU2 - CPU2 CPU2 - -
(1) rq: coverage of the failure mode (see Table 2) is required by the standards for the indicated class. More than one acceptable measure may be available to choose from.
(2) For a complete list of acceptable measures and their definitions, see the IEC/UL specifications.
(3) For a description and implementation suggestions for each ID, see the device-specific Functional Safety Manual.
(4) This device does not include HWBIST (ID CPU2). Therefore, a periodic test of the CPU registers is suggested. STL_CPU_REG refers to an example CPU register test within the diagnostic library. Refer to the diagnostic library documentation.