SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
The QMn Base Address Registers (Figure 4-23) are used to create four logical queue managers that map into a physical queue manager.
31 | 0 |
QM_BASE_ADDR |
R/W-0 |
Legend: R/W = Read/Write; - n = value after reset |
Bit | Field | Description |
---|---|---|
31-0 | QM_BASE_ADDR | This field programs the base address for the nth logical queue manager for the PKTDMA. Typically, these registers point into the Queue Management region of a physical queue manager on the same device, or a remote queue manager on another device. They must be programmed using the VBUSM address, which is 0x34020000 for physical queue 0 (KeyStone I). The reset value for QM0 Base Address Register defaults to this address, but QM1, QM2, and QM3 reset to 0. The most common programming of these registers is the following:
The PKTDMA will obtain the VBUSM address for TX queues via one of these registers. For all KeyStone I devices, QM0 is used. For KeyStone II, QM0 is used for all PKTDMAs that get their queue pend signals from physical Queue Manager 1. QM2 is used for PKTDMAs that get their queue pend signals from physical Queue Manager 2. These registers define a “Navigator Cloud” (see Section 1.9). All PKTDMAs in a given cloud must have these registers set to the same values. The other components of a Navigator Cloud are: 1) Descriptors, and 2) RX Flows. Their qmgr:qnum fields must be compatible with the base addresses defined here or descriptors may be erroneously routed. Keystone II notes:
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