SPRUGR9H November 2010 – April 2015 66AK2E05 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678
Status Register 2 (Figure 4-44) provides read-only status on the High Priority Accumulator Interrupts managed by INTD. Reading this register returns a 1 bit for each interrupt that has been triggered.
31 | 30 | ... | 1 | 0 |
INT31 | INT30 – INT1 | INT0 |
R-0 | R-0 | R-0 |
Legend: R = Read only; - n = value after reset |
Bit | Field | Description |
---|---|---|
31 | INT31 | High Priority Accumulator Interrupt 31 status |
30
... 1 |
INT30
... INT1 |
High Priority Accumulator Interrupt n status |
0 | INT0 | High Priority Accumulator Interrupt 0 status |