SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
Memory-mapped registers in the System Control operate on INTOSC1 clock domain; hence, any CPU writes to these registers requires a delay between subsequent writes otherwise a second write can be lost. The application needs to take this into consideration and add a delay in terms of the number of NOP instructions after every write to these registers that are mentioned in Table 3-19. The formula to compute delay between subsequent writes:
Delay (in SYSCLK cycles) = 3 × (FSYSCLK ÷ FINTOSC1) + 9
For Example - For SYSCLK = 100MHz
Delay (in SYSCLK cycles) = 3 × (100MHz ÷ 10MHz) + 9 = 39 SYSCLK cycles
Registers requiring delay after every write |
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PERCLKDIVSEL |
SYSCLKDIVSEL |
SYSPLLCTL1 |
SYSPLLMULT |
WDCR |
XCLKOUTDIVSEL |
CLKSRCCTL1 |
CLKSRCCTL2 |
CLKSRCCTL3 |
CPU1TMR2CTL (TMR2CLKCTL) |