SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
Table 3-63 lists the memory-mapped registers for the NMI_INTRUPT_REGS registers. All register offset addresses not listed in Table 3-63 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | NMICFG | NMI Configuration Register | EALLOW | Go |
1h | NMIFLG | NMI Flag Register (XRSn Clear) | Go | |
2h | NMIFLGCLR | NMI Flag Clear Register | EALLOW | Go |
3h | NMIFLGFRC | NMI Flag Force Register | EALLOW | Go |
4h | NMIWDCNT | NMI Watchdog Counter Register | Go | |
5h | NMIWDPRD | NMI Watchdog Period Register | EALLOW | Go |
6h | NMISHDFLG | NMI Shadow Flag Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-64 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value |
NMICFG is shown in Figure 3-60 and described in Table 3-65.
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NMI Configuration Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NMIE | ||||||
R-0-0h | R/W1S-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-1 | RESERVED | R-0 | 0h | Reserved |
0 | NMIE | R/W1S | 0h | When set to 1 any condition will generate an NMI interrupt to the C28 CPU and kick off the NMI watchdog counter. As part of boot sequence this bit should be set after the device security related initialization is complete. 0 NMI disabled 1 NMI enabled Reset type: SYSRSn |
NMIFLG is shown in Figure 3-61 and described in Table 3-66.
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NMI Flag Register (XRSn Clear)
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | CLBNMI | |||
R-0-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1HWBISTERR | FLUNCERR | RAMUNCERR | CLOCKFAIL | NMIINT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R-0 | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | CLBNMI | R | 0h | Configurable Logic Block NMI Flag: This bit indicates if an NMI was generated by the Configurable Logic Block. This bit can only be cleared by the user writing to the corresponding clear bit in the NMIFLGCLR register or by an XRSn reset: 0,No Configurable Logic Block NMI pending 1,Configurable Logic Block NMI generated Reset type: XRSn |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | CPU1HWBISTERR | R | 0h | HW BIST Error NMI Flag: This bit indicates if the time out error or a signature mismatch error condition during hardware BIST of C28 CPU1 occurred. This bit can only be cleared by the user writing to the corresponding clear bit in the NMIFLGCLR register or by an XRSn reset: 0,No C28 HWBIST error condition pending 1,C28 BIST error condition generated Reset type: XRSn |
3 | FLUNCERR | R | 0h | Flash Uncorrectable Error NMI Flag: This bit indicates if an uncorrectable error occurred on a C28 Flash access and that condition is latched. This bit can only be cleared by the user writing to the corresponding clear bit in the NMIFLGCLR register or by an XRSn reset: 0,No C28 Flash uncorrectable error condition pending 1,C28 Flash uncorrectable error condition generated Reset type: XRSn |
2 | RAMUNCERR | R | 0h | RAM Uncorrectable Error NMI Flag: This bit indicates if an uncorrectable error occurred on a RAM access (by any master) and that condition is latched. This bit can only be cleared by the user writing to the corresponding clear bit in the NMIFLGCLR register or by an XRSn reset: 0,No RAM uncorrectable error condition pending 1,RAM uncorrectable error condition generated Reset type: XRSn |
1 | CLOCKFAIL | R | 0h | Clock Fail Interrupt Flag: These bits indicates if the CLOCKFAIL condition is latched. These bits can only be cleared by the user writing to the respective bit in the NMIFLGCLR register or by an XRSn reset: 0,No CLOCKFAIL Condition Pending 1,CLOCKFAIL Condition Generated Reset type: XRSn |
0 | NMIINT | R | 0h | NMI Interrupt Flag: This bit indicates if an NMI interrupt was generated. This bit can only be cleared by the user writing to the respective bit in the NMIFLGCLR register or by an XRSn reset: 0 No NMI Interrupt Generated 1 NMI Interrupt Generated No further NMI interrupts pulses are generated until this flag is cleared by the user. Reset type: XRSn |
NMIFLGCLR is shown in Figure 3-62 and described in Table 3-67.
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NMI Flag Clear Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | CLBNMI | |||
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1HWBISTERR | FLUNCERR | RAMUNCERR | CLOCKFAIL | NMIINT |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R-0 | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | CLBNMI | R-0/W1S | 0h | Writing a 1 to the respective bit clears the corresponding flag bit in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. Notes: [1] If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same cycle, hardware has priority. [2] Users should clear the pending FAIL flag first and then clear the NMIINT flag. Reset type: SYSRSn |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | CPU1HWBISTERR | R-0/W1S | 0h | Writing a 1 to the respective bit clears the corresponding flag bit in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. Notes: [1] If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same cycle, hardware has priority. [2] Users should clear the pending FAIL flag first and then clear the NMIINT flag. Reset type: SYSRSn |
3 | FLUNCERR | R-0/W1S | 0h | Writing a 1 to the respective bit clears the corresponding flag bit in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. Notes: [1] If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same cycle, hardware has priority. [2] Users should clear the pending FAIL flag first and then clear the NMIINT flag. Reset type: SYSRSn |
2 | RAMUNCERR | R-0/W1S | 0h | Writing a 1 to the respective bit clears the corresponding flag bit in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. Notes: [1] If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same cycle, hardware has priority. [2] Users should clear the pending FAIL flag first and then clear the NMIINT flag. Reset type: SYSRSn |
1 | CLOCKFAIL | R-0/W1S | 0h | Writing a 1 to the respective bit clears the corresponding flag bit in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. Notes: [1] If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same cycle, hardware has priority. [2] Users should clear the pending FAIL flag first and then clear the NMIINT flag. Reset type: SYSRSn |
0 | NMIINT | R-0/W1S | 0h | Writing a 1 to the respective bit clears the corresponding flag bit in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. Notes: [1] If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same cycle, hardware has priority. [2] Users should clear the pending FAIL flag first and then clear the NMIINT flag. Reset type: SYSRSn |
NMIFLGFRC is shown in Figure 3-63 and described in Table 3-68.
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NMI Flag Force Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | CLBNMI | |||
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1HWBISTERR | FLUNCERR | RAMUNCERR | CLOCKFAIL | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R-0 | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | CLBNMI | R-0/W1S | 0h | Writing a 1 to these bits will set the respective FAIL flag in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. This can be used as a means to test the NMI mechanisms. Reset type: SYSRSn |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | CPU1HWBISTERR | R-0/W1S | 0h | Writing a 1 to these bits will set the respective FAIL flag in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. This can be used as a means to test the NMI mechanisms. Reset type: SYSRSn |
3 | FLUNCERR | R-0/W1S | 0h | Writing a 1 to these bits will set the respective FAIL flag in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. This can be used as a means to test the NMI mechanisms. Reset type: SYSRSn |
2 | RAMUNCERR | R-0/W1S | 0h | Writing a 1 to these bits will set the respective FAIL flag in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. This can be used as a means to test the NMI mechanisms. Reset type: SYSRSn |
1 | CLOCKFAIL | R-0/W1S | 0h | Writing a 1 to these bits will set the respective FAIL flag in the NMIFLG and NMISHDFLG registers. Writes of 0 are ignored. Always reads back 0. This can be used as a means to test the NMI mechanisms. Reset type: SYSRSn |
0 | RESERVED | R-0 | 0h | Reserved |
NMIWDCNT is shown in Figure 3-64 and described in Table 3-69.
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NMI Watchdog Counter Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMIWDCNT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMIWDCNT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | NMIWDCNT | R | 0h | NMI Watchdog Counter: This 16-bit incremental counter will start incrementing whenever any one of the enabled FAIL flags are set. If the counter reaches the period value, an NMIRSn signal is fired which will then resets the system. The counter will reset to zero when it reaches the period value and will then restart counting if any of the enabled FAIL flags are set. If no enabled FAIL flag is set, then the counter will reset to zero and remain at zero until an enabled FAIL flag is set. Normally, the software would respond to the NMI interrupt generated and clear the offending FLAG(s) before the NMI watchdog triggers a reset. In some situations, the software may decide to allow the watchdog to reset the device anyway. The counter is clocked at the SYSCLKOUT rate. Reset type: SYSRSn |
NMIWDPRD is shown in Figure 3-65 and described in Table 3-70.
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NMI Watchdog Period Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMIWDPRD | |||||||
R/W-FFFFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMIWDPRD | |||||||
R/W-FFFFh | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | NMIWDPRD | R/W | FFFFh | NMI Watchdog Period: This 16-bit value contains the period value at which a reset is generated when the watchdog counter matches. At reset this value is set at the maximum. The software can decrease the period value at initialization time. Writing a PERIOD value that is smaller then the current counter value will automatically force an NMIRSn and hence reset the watchdog counter. Reset type: SYSRSn |
NMISHDFLG is shown in Figure 3-66 and described in Table 3-71.
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NMI Shadow Flag Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | CLBNMI | |||
R-0-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CPU1HWBISTERR | FLUNCERR | RAMUNCERR | CLOCKFAIL | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-12 | RESERVED | R-0 | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | CLBNMI | R | 0h | Shadow NMI Flags: When an NMIFLG bit is set due to any of the possible NMI source in the device, the corresponding bit in this register is also set. Note that NMIFLGFRC and NMIFLGCLR register also affects the bits of this register in the same way as they do for the NMIFLG register. This register is only reset by a PORESETn reset. Notes: [1] This register is added to keep the definition of System Control Reset Cause Register Clean. Reset type: PORESETn |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | CPU1HWBISTERR | R | 0h | Shadow NMI Flags: When an NMIFLG bit is set due to any of the possible NMI source in the device, the corresponding bit in this register is also set. Note that NMIFLGFRC and NMIFLGCLR register also affects the bits of this register in the same way as they do for the NMIFLG register. This register is only reset by a PORESETn reset. Notes: [1] This register is added to keep the definition of System Control Reset Cause Register Clean. Reset type: PORESETn |
3 | FLUNCERR | R | 0h | Shadow NMI Flags: When an NMIFLG bit is set due to any of the possible NMI source in the device, the corresponding bit in this register is also set. Note that NMIFLGFRC and NMIFLGCLR register also affects the bits of this register in the same way as they do for the NMIFLG register. This register is only reset by a PORESETn reset. Notes: [1] This register is added to keep the definition of System Control Reset Cause Register Clean. Reset type: PORESETn |
2 | RAMUNCERR | R | 0h | Shadow NMI Flags: When an NMIFLG bit is set due to any of the possible NMI source in the device, the corresponding bit in this register is also set. Note that NMIFLGFRC and NMIFLGCLR register also affects the bits of this register in the same way as they do for the NMIFLG register. This register is only reset by a PORESETn reset. Notes: [1] This register is added to keep the definition of System Control Reset Cause Register Clean. Reset type: PORESETn |
1 | CLOCKFAIL | R | 0h | Shadow NMI Flags: When an NMIFLG bit is set due to any of the possible NMI source in the device, the corresponding bit in this register is also set. Note that NMIFLGFRC and NMIFLGCLR register also affects the bits of this register in the same way as they do for the NMIFLG register. This register is only reset by a PORESETn reset. Notes: [1] This register is added to keep the definition of System Control Reset Cause Register Clean. Reset type: PORESETn |
0 | RESERVED | R-0 | 0h | Reserved |