SPRUHM9H October   2014  – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
  5. 3 System Control and Interrupt
    1. 3.1  Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1  Reset Sources
      2. 3.3.2  External Reset (XRS)
      3. 3.3.3  Power-On Reset (POR)
      4. 3.3.4  Debugger Reset (SYSRS)
      5. 3.3.5  Watchdog Reset (WDRS)
      6. 3.3.6  NMI Watchdog Reset (NMIWDRS)
      7. 3.3.7  DCSM Safe Code Copy Reset (SCCRESET)
      8. 3.3.8  Hibernate Reset (HIBRESET)
      9. 3.3.9  Hardware BIST Reset (HWBISTRS)
      10. 3.3.10 Test Reset (TRST)
    4. 3.4  Peripheral Interrupts
      1. 3.4.1 Interrupt Concepts
      2. 3.4.2 Interrupt Architecture
        1. 3.4.2.1 Peripheral Stage
        2. 3.4.2.2 PIE Stage
        3. 3.4.2.3 CPU Stage
      3. 3.4.3 Interrupt Entry Sequence
      4. 3.4.4 Configuring and Using Interrupts
        1. 3.4.4.1 Enabling Interrupts
        2. 3.4.4.2 Handling Interrupts
        3. 3.4.4.3 Disabling Interrupts
        4. 3.4.4.4 Nesting Interrupts
      5. 3.4.5 PIE Channel Mapping
        1. 3.4.5.1 PIE Interrupt Priority
          1. 3.4.5.1.1 Channel Priority
          2. 3.4.5.1.2 Group Priority
      6. 3.4.6 Vector Tables
    5. 3.5  Exceptions and Non-Maskable Interrupts
      1. 3.5.1 Configuring and Using NMIs
      2. 3.5.2 Emulation Considerations
      3. 3.5.3 NMI Sources
        1. 3.5.3.1 Missing Clock Detection
        2. 3.5.3.2 RAM Uncorrectable ECC Error
        3. 3.5.3.3 Flash Uncorrectable ECC Error
      4. 3.5.4 Illegal Instruction Trap (ITRAP)
    6. 3.6  Safety Features
      1. 3.6.1 Write Protection on Registers
        1. 3.6.1.1 LOCK Protection on System Configuration Registers
        2. 3.6.1.2 EALLOW Protection
      2. 3.6.2 Missing Clock Detection Logic
      3. 3.6.3 PLLSLIP Detection
      4. 3.6.4 CPU Vector Address Validity Check
      5. 3.6.5 NMIWDs
      6. 3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection
      7. 3.6.7 ECC Enabled Flash Memory
      8. 3.6.8 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1 Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
        4. 3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.7.2 Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
        3. 3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
        4. 3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
      3. 3.7.3 Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4 XCLKOUT
      5. 3.7.5 Clock Connectivity
      6. 3.7.6 Clock Source and PLL Setup
        1. 3.7.6.1 Choosing PLL Settings
        2. 3.7.6.2 System Clock Setup
        3. 3.7.6.3 USB Auxiliary Clock Setup
        4. 3.7.6.4 Clock Configuration Examples
      7. 3.7.7 Clock (OSCCLK) Failure Detection
        1. 3.7.7.1 Missing Clock Detection Logic
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timers
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low-Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 IDLE
      2. 3.10.2 STANDBY
      3. 3.10.3 HALT
      4. 3.10.4 Hibernate (HIB)
    11. 3.11 Memory Controller Module
      1. 3.11.1 Functional Description
        1. 3.11.1.1 Dedicated RAM (Dx RAM)
        2. 3.11.1.2 Local Shared RAM (LSx RAM)
        3. 3.11.1.3 Global Shared RAM (GSx RAM)
        4. 3.11.1.4 Message RAM (CLA MSGRAM)
        5. 3.11.1.5 Access Arbitration
        6. 3.11.1.6 Access Protection
          1. 3.11.1.6.1 CPU Fetch Protection
          2. 3.11.1.6.2 CPU Write Protection
          3. 3.11.1.6.3 CPU Read Protection
          4. 3.11.1.6.4 CLA Fetch Protection
          5. 3.11.1.6.5 CLA Write Protection
          6. 3.11.1.6.6 CLA Read Protection
          7. 3.11.1.6.7 DMA Write Protection
        7. 3.11.1.7 Memory Error Detection, Correction and Error Handling
          1. 3.11.1.7.1 Error Detection and Correction
          2. 3.11.1.7.2 Error Handling
        8. 3.11.1.8 Application Test Hooks for Error Detection and Correction
        9. 3.11.1.9 RAM Initialization
    12. 3.12 Flash and OTP Memory
      1. 3.12.1  Features
      2. 3.12.2  Flash Tools
      3. 3.12.3  Default Flash Configuration
      4. 3.12.4  Flash Bank, One-Time Programmable (OTP) Memory, and Flash Pump
      5. 3.12.5  Flash Module Controller (FMC)
      6. 3.12.6  Flash and OTP Memory Power-Down Modes and Wakeup
      7. 3.12.7  Flash and OTP Memory Performance
      8. 3.12.8  Flash Read Interface
        1. 3.12.8.1 FMC Flash Read Interface
          1. 3.12.8.1.1 Standard Read Mode
          2. 3.12.8.1.2 Prefetch Mode
            1. 3.12.8.1.2.1 Data Cache
      9. 3.12.9  Erase/Program Flash
        1. 3.12.9.1 Erase
        2. 3.12.9.2 Program
        3. 3.12.9.3 Verify
      10. 3.12.10 Error Correction Code (ECC) Protection
        1. 3.12.10.1 Single-Bit Data Error
        2. 3.12.10.2 Uncorrectable Error
        3. 3.12.10.3 SECDED Logic Correctness Check
        4. 3.12.10.4 Reading ECC Memory From a Higher Address Space
      11. 3.12.11 Reserved Locations Within Flash and OTP Memory
      12. 3.12.12 Procedure to Change the Flash Control Registers
      13. 3.12.13 Simple Procedure to Modify an Application from RAM Configuration to Flash Configuration
    13. 3.13 Dual Code Security Module (DCSM)
      1. 3.13.1 Functional Description
        1. 3.13.1.1 Emulation Code Security Logic (ECSL)
        2. 3.13.1.2 CPU Secure Logic
        3. 3.13.1.3 Execute-Only Protection
        4. 3.13.1.4 Password Lock
        5. 3.13.1.5 JTAG Lock
        6. 3.13.1.6 Link Pointer and Zone Select
          1. 3.13.1.6.1 C Code Example to get Zone Select Block Addr for Zone1
        7. 3.13.1.7 Flash and OTP Memory Erase/Program
        8. 3.13.1.8 Safe Copy Code
        9. 3.13.1.9 SafeCRC
      2. 3.13.2 CSM Impact on Other On-Chip Resources
      3. 3.13.3 Incorporating Code Security in User Applications
        1. 3.13.3.1 Environments That Require Security Unlocking
        2. 3.13.3.2 CSM Password Match Flow
        3. 3.13.3.3 Unsecuring Considerations for Zones With and Without Code Security
          1. 3.13.3.3.1 C Code Example to Unsecure C28x Zone1
          2. 3.13.3.3.2 C Code Example to Resecure C28x Zone1
        4. 3.13.3.4 Environments That Require ECSL Unlocking
        5. 3.13.3.5 ECSL Password Match Flow
        6. 3.13.3.6 ECSL Disable Considerations for any Zone
          1. 3.13.3.6.1 C Code Example to Disable ECSL for C28x-Zone1
        7. 3.13.3.7 Device Unique ID
    14. 3.14 JTAG
    15. 3.15 System Control Register Configuration Restrictions
    16. 3.16 Software
      1. 3.16.1 SYSCTL Examples
        1. 3.16.1.1 Missing clock detection (MCD)
        2. 3.16.1.2 XCLKOUT (External Clock Output) Configuration
      2. 3.16.2 TIMER Examples
        1. 3.16.2.1 CPU Timers
        2. 3.16.2.2 CPU Timers
      3. 3.16.3 MEMCFG Examples
      4. 3.16.4 INTERRUPT Examples
        1. 3.16.4.1 External Interrupts (ExternalInterrupt)
        2. 3.16.4.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 3.16.4.3 CPU Timer Interrupt Software Prioritization
        4. 3.16.4.4 EPWM Real-Time Interrupt
      5. 3.16.5 LPM Examples
      6. 3.16.6 WATCHDOG Examples
        1. 3.16.6.1 Watchdog
    17. 3.17 System Control Registers
      1. 3.17.1  System Control Base Addresses
      2. 3.17.2  CPUTIMER_REGS Registers
      3. 3.17.3  PIE_CTRL_REGS Registers
      4. 3.17.4  WD_REGS Registers
      5. 3.17.5  NMI_INTRUPT_REGS Registers
      6. 3.17.6  XINT_REGS Registers
      7. 3.17.7  SYNC_SOC_REGS Registers
      8. 3.17.8  DMA_CLA_SRC_SEL_REGS Registers
      9. 3.17.9  DEV_CFG_REGS Registers
      10. 3.17.10 CLK_CFG_REGS Registers
      11. 3.17.11 CPU_SYS_REGS Registers
      12. 3.17.12 ROM_PREFETCH_REGS Registers
      13. 3.17.13 DCSM_Z1_REGS Registers
      14. 3.17.14 DCSM_Z2_REGS Registers
      15. 3.17.15 DCSM_COMMON_REGS Registers
      16. 3.17.16 MEM_CFG_REGS Registers
      17. 3.17.17 ACCESS_PROTECTION_REGS Registers
      18. 3.17.18 MEMORY_ERROR_REGS Registers
      19. 3.17.19 ROM_WAIT_STATE_REGS Registers
      20. 3.17.20 FLASH_CTRL_REGS Registers
      21. 3.17.21 FLASH_ECC_REGS Registers
      22. 3.17.22 UID_REGS Registers
      23. 3.17.23 DCSM_Z1_OTP Registers
      24. 3.17.24 DCSM_Z2_OTP Registers
      25. 3.17.25 Register to Driverlib Function Mapping
        1. 3.17.25.1 CPUTIMER Registers to Driverlib Functions
        2. 3.17.25.2 ASYSCTL Registers to Driverlib Functions
        3. 3.17.25.3 PIE Registers to Driverlib Functions
        4. 3.17.25.4 SYSCTL Registers to Driverlib Functions
        5. 3.17.25.5 NMI Registers to Driverlib Functions
        6. 3.17.25.6 XINT Registers to Driverlib Functions
        7. 3.17.25.7 DCSM Registers to Driverlib Functions
        8. 3.17.25.8 MEMCFG Registers to Driverlib Functions
        9. 3.17.25.9 FLASH Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1  Introduction
    2. 4.2  Boot ROM Registers
    3. 4.3  Device Boot Sequence
    4. 4.4  Device Boot Modes
    5. 4.5  Configuring Boot Mode Pins
    6. 4.6  Configuring Get Boot Options
    7. 4.7  Configuring Emulation Boot Options
    8. 4.8  Device Boot Flow Diagrams
      1. 4.8.1 Emulation Boot Flow Diagrams
      2. 4.8.2 Standalone and Hibernate Boot Flow Diagrams
    9. 4.9  Device Reset and Exception Handling
      1. 4.9.1 Reset Causes and Handling
      2. 4.9.2 Exceptions and Interrupts Handling
    10. 4.10 Boot ROM Description
      1. 4.10.1  Entry Points
      2. 4.10.2  Wait Points
      3. 4.10.3  Memory Maps
        1. 4.10.3.1 Boot ROM Memory Map
        2. 4.10.3.2 CLA Data ROM Memory Map
        3. 4.10.3.3 Reserved RAM and Flash Memory-Map
        4. 4.10.3.4 ROM Tables
          1. 4.10.3.4.1 Boot ROM Tables
          2. 4.10.3.4.2 CLA ROM Tables
      4. 4.10.4  Boot Modes
        1. 4.10.4.1 Wait Boot Mode
        2. 4.10.4.2 SCI Boot Mode
        3. 4.10.4.3 SPI Boot Mode
        4. 4.10.4.4 I2C Boot Mode
        5. 4.10.4.5 Parallel Boot Mode
        6. 4.10.4.6 CAN Boot Mode
        7. 4.10.4.7 USB Boot Mode
      5. 4.10.5  Boot Data Stream Structure
        1. 4.10.5.1 Bootloader Data Stream Structure
          1. 4.10.5.1.1 Data Stream Structure 8-bit
      6. 4.10.6  GPIO Assignments
      7. 4.10.7  Secure ROM Function APIs
      8. 4.10.8  Clock Initializations
      9. 4.10.9  Wait State Configuration
      10. 4.10.10 Boot Status information
        1. 4.10.10.1 CPU Booting Status
      11. 4.10.11 ROM Version
  7. 5 Direct Memory Access (DMA)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
    2. 5.2 Architecture
      1. 5.2.1 Common Peripheral Architecture
      2. 5.2.2 Peripheral Interrupt Event Trigger Sources
      3. 5.2.3 DMA Bus
    3. 5.3 Address Pointer and Transfer Control
    4. 5.4 Pipeline Timing and Throughput
    5. 5.5 CPU and CLA Arbitration
    6. 5.6 Channel Priority
      1. 5.6.1 Round-Robin Mode
      2. 5.6.2 Channel 1 High-Priority Mode
    7. 5.7 Overrun Detection Feature
    8. 5.8 Software
      1. 5.8.1 DMA Examples
        1. 5.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 5.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
        3. 5.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
        4. 5.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 5.9 DMA Registers
      1. 5.9.1 DMA Base Addresses
      2. 5.9.2 DMA_REGS Registers
      3. 5.9.3 DMA_CH_REGS Registers
      4. 5.9.4 DMA Registers to Driverlib Functions
  8. 6 Control Law Accelerator (CLA)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 CLA Related Collateral
      3. 6.1.3 Block Diagram
    2. 6.2 CLA Interface
      1. 6.2.1 CLA Memory
      2. 6.2.2 CLA Memory Bus
      3. 6.2.3 Shared Peripherals and EALLOW Protection
      4. 6.2.4 CLA Tasks and Interrupt Vectors
      5. 6.2.5 CLA Software Interrupt to CPU
    3. 6.3 CLA and CPU Arbitration
      1. 6.3.1 CLA Message RAM
      2. 6.3.2 CLA Program Memory
      3. 6.3.3 CLA Data Memory
      4. 6.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 6.4 CLA Configuration and Debug
      1. 6.4.1 Building a CLA Application
      2. 6.4.2 Typical CLA Initialization Sequence
      3. 6.4.3 Debugging CLA Code
        1. 6.4.3.1 Breakpoint Support (MDEBUGSTOP)
      4. 6.4.4 CLA Illegal Opcode Behavior
      5. 6.4.5 Resetting the CLA
    5. 6.5 Pipeline
      1. 6.5.1 Pipeline Overview
      2. 6.5.2 CLA Pipeline Alignment
        1. 6.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       332
        3. 6.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       334
        5. 6.5.2.3 ADC Early Interrupt to CLA Response
      3. 6.5.3 Parallel Instructions
        1. 6.5.3.1 Math Operation with Parallel Load
        2. 6.5.3.2 Multiply with Parallel Add
      4. 6.5.4 CLA Task Execution Latency
    6. 6.6 Software
      1. 6.6.1 CLA Examples
        1. 6.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 6.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
    7. 6.7 Instruction Set
      1. 6.7.1 Instruction Descriptions
      2. 6.7.2 Addressing Modes and Encoding
      3. 6.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest [, CNDF]
        11.       MCCNDD 16BitDest [, CNDF]
        12.       MCMP32 MRa, MRb
        13.       MCMPF32 MRa, MRb
        14.       MCMPF32 MRa, #16FHi
        15.       MDEBUGSTOP
        16.       MEALLOW
        17.       MEDIS
        18.       MEINVF32 MRa, MRb
        19.       MEISQRTF32 MRa, MRb
        20.       MF32TOI16 MRa, MRb
        21.       MF32TOI16R MRa, MRb
        22.       MF32TOI32 MRa, MRb
        23.       MF32TOUI16 MRa, MRb
        24.       MF32TOUI16R MRa, MRb
        25.       MF32TOUI32 MRa, MRb
        26.       MFRACF32 MRa, MRb
        27.       MI16TOF32 MRa, MRb
        28.       MI16TOF32 MRa, mem16
        29.       MI32TOF32 MRa, mem32
        30.       MI32TOF32 MRa, MRb
        31.       MLSL32 MRa, #SHIFT
        32.       MLSR32 MRa, #SHIFT
        33.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        34.       MMAXF32 MRa, MRb
        35.       MMAXF32 MRa, #16FHi
        36.       MMINF32 MRa, MRb
        37.       MMINF32 MRa, #16FHi
        38.       MMOV16 MARx, MRa, #16I
        39.       MMOV16 MARx, mem16
        40.       MMOV16 mem16, MARx
        41.       MMOV16 mem16, MRa
        42.       MMOV32 mem32, MRa
        43.       MMOV32 mem32, MSTF
        44.       MMOV32 MRa, mem32 [, CNDF]
        45.       MMOV32 MRa, MRb [, CNDF]
        46.       MMOV32 MSTF, mem32
        47.       MMOVD32 MRa, mem32
        48.       MMOVF32 MRa, #32F
        49.       MMOVI16 MARx, #16I
        50.       MMOVI32 MRa, #32FHex
        51.       MMOVIZ MRa, #16FHi
        52.       MMOVZ16 MRa, mem16
        53.       MMOVXI MRa, #16FLoHex
        54.       MMPYF32 MRa, MRb, MRc
        55.       MMPYF32 MRa, #16FHi, MRb
        56.       MMPYF32 MRa, MRb, #16FHi
        57.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        58.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        59.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        60.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        61.       MNEGF32 MRa, MRb[, CNDF]
        62.       MNOP
        63.       MOR32 MRa, MRb, MRc
        64.       MRCNDD [CNDF]
        65.       MSETFLG FLAG, VALUE
        66.       MSTOP
        67.       MSUB32 MRa, MRb, MRc
        68.       MSUBF32 MRa, MRb, MRc
        69.       MSUBF32 MRa, #16FHi, MRb
        70.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        71.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        72.       MSWAPF MRa, MRb [, CNDF]
        73.       MTESTTF CNDF
        74.       MUI16TOF32 MRa, mem16
        75.       MUI16TOF32 MRa, MRb
        76.       MUI32TOF32 MRa, mem32
        77.       MUI32TOF32 MRa, MRb
        78.       MXOR32 MRa, MRb, MRc
    8. 6.8 CLA Registers
      1. 6.8.1 CLA Base Addresses
      2. 6.8.2 CLA_REGS Registers
      3. 6.8.3 CLA_SOFTINT_REGS Registers
      4. 6.8.4 CLA Registers to Driverlib Functions
  9. 7 General-Purpose Input/Output (GPIO)
    1. 7.1  Introduction
      1. 7.1.1 GPIO Related Collateral
    2. 7.2  Configuration Overview
    3. 7.3  Digital General-Purpose I/O Control
    4. 7.4  Input Qualification
      1. 7.4.1 No Synchronization (Asynchronous Input)
      2. 7.4.2 Synchronization to SYSCLKOUT Only
      3. 7.4.3 Qualification Using a Sampling Window
    5. 7.5  USB Signals
    6. 7.6  SPI Signals
    7. 7.7  GPIO and Peripheral Muxing
      1. 7.7.1 GPIO Muxing
      2. 7.7.2 Peripheral Muxing
    8. 7.8  Internal Pullup Configuration Requirements
    9. 7.9  Software
      1. 7.9.1 GPIO Examples
        1. 7.9.1.1 Device GPIO Setup
        2. 7.9.1.2 Device GPIO Toggle
        3. 7.9.1.3 Device GPIO Interrupt
      2. 7.9.2 LED Examples
    10. 7.10 GPIO Registers
      1. 7.10.1 GPIO Base Addresses
      2. 7.10.2 GPIO_CTRL_REGS Registers
      3. 7.10.3 GPIO_DATA_REGS Registers
      4. 7.10.4 GPIO Registers to Driverlib Functions
  10. 8 Crossbar (X-BAR)
    1. 8.1 Input X-BAR
    2. 8.2 ePWM, CLB, and GPIO Output X-BAR
      1. 8.2.1 ePWM X-BAR
        1. 8.2.1.1 ePWM X-BAR Architecture
      2. 8.2.2 CLB X-BAR
        1. 8.2.2.1 CLB X-BAR Architecture
      3. 8.2.3 GPIO Output X-BAR
        1. 8.2.3.1 GPIO Output X-BAR Architecture
      4. 8.2.4 X-BAR Flags
    3. 8.3 XBAR Registers
      1. 8.3.1 XBAR Base Addresses
      2. 8.3.2 INPUT_XBAR_REGS Registers
      3. 8.3.3 XBAR_REGS Registers
      4. 8.3.4 EPWM_XBAR_REGS Registers
      5. 8.3.5 CLB_XBAR_REGS Registers
      6. 8.3.6 OUTPUT_XBAR_REGS Registers
      7. 8.3.7 Register to Driverlib Function Mapping
        1. 8.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 8.3.7.2 XBAR Registers to Driverlib Functions
        3. 8.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 8.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 8.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
  11. 9 Analog Subsystem
    1. 9.1 Introduction
      1. 9.1.1 Features
      2. 9.1.2 Block Diagram
    2. 9.2 Optimizing Power-Up Time
    3. 9.3 Analog Subsystem Registers
      1. 9.3.1 Analog Subsystem Base Addresses
      2. 9.3.2 ANALOG_SUBSYS_REGS Registers
  12. 10Analog-to-Digital Converter (ADC)
    1. 10.1  Introduction
      1. 10.1.1 ADC Related Collateral
      2. 10.1.2 Features
      3. 10.1.3 Block Diagram
    2. 10.2  ADC Configurability
      1. 10.2.1 Clock Configuration
      2. 10.2.2 Resolution
      3. 10.2.3 Voltage Reference
        1. 10.2.3.1 External Reference Mode
      4. 10.2.4 Signal Mode
      5. 10.2.5 Expected Conversion Results
      6. 10.2.6 Interpreting Conversion Results
    3. 10.3  SOC Principle of Operation
      1. 10.3.1 SOC Configuration
      2. 10.3.2 Trigger Operation
      3. 10.3.3 ADC Acquisition (Sample and Hold) Window
      4. 10.3.4 ADC Input Models
      5. 10.3.5 Channel Selection
    4. 10.4  SOC Configuration Examples
      1. 10.4.1 Single Conversion from ePWM Trigger
      2. 10.4.2 Oversampled Conversion from ePWM Trigger
      3. 10.4.3 Multiple Conversions from CPU Timer Trigger
      4. 10.4.4 Software Triggering of SOCs
    5. 10.5  ADC Conversion Priority
    6. 10.6  Burst Mode
      1. 10.6.1 Burst Mode Example
      2. 10.6.2 Burst Mode Priority Example
    7. 10.7  EOC and Interrupt Operation
      1. 10.7.1 Interrupt Overflow
      2. 10.7.2 Continue to Interrupt Mode
      3. 10.7.3 Early Interrupt Configuration Mode
    8. 10.8  Post-Processing Blocks
      1. 10.8.1 PPB Offset Correction
      2. 10.8.2 PPB Error Calculation
      3. 10.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 10.8.4 PPB Sample Delay Capture
    9. 10.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 10.9.1 Implementation
      2. 10.9.2 Detecting an Open Input Pin
      3. 10.9.3 Detecting a Shorted Input Pin
    10. 10.10 Power-Up Sequence
    11. 10.11 ADC Calibration
      1. 10.11.1 ADC Zero Offset Calibration
    12. 10.12 ADC Timings
      1. 10.12.1 ADC Timing Diagrams
    13. 10.13 Additional Information
      1. 10.13.1 Ensuring Synchronous Operation
        1. 10.13.1.1 Basic Synchronous Operation
        2. 10.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 10.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 10.13.1.4 Non-overlapping Conversions
      2. 10.13.2 Choosing an Acquisition Window Duration
      3. 10.13.3 Achieving Simultaneous Sampling
      4. 10.13.4 Result Register Mapping
      5. 10.13.5 Internal Temperature Sensor
      6. 10.13.6 Designing an External Reference Circuit
    14. 10.14 Software
      1. 10.14.1 ADC Examples
        1. 10.14.1.1  ADC Software Triggering
        2. 10.14.1.2  ADC ePWM Triggering
        3. 10.14.1.3  ADC Temperature Sensor Conversion
        4. 10.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 10.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 10.14.1.6  ADC PPB Offset (adc_ppb_offset)
        7. 10.14.1.7  ADC PPB Limits (adc_ppb_limits)
        8. 10.14.1.8  ADC PPB Delay Capture (adc_ppb_delay)
        9. 10.14.1.9  ADC ePWM Triggering Multiple SOC
        10. 10.14.1.10 ADC Burst Mode
        11. 10.14.1.11 ADC Burst Mode Oversampling
        12. 10.14.1.12 ADC SOC Oversampling
        13. 10.14.1.13 ADC PPB PWM trip (adc_ppb_pwm_trip)
    15. 10.15 ADC Registers
      1. 10.15.1 ADC Base Addresses
      2. 10.15.2 ADC_RESULT_REGS Registers
      3. 10.15.3 ADC_REGS Registers
      4. 10.15.4 ADC Registers to Driverlib Functions
  13. 11Buffered Digital-to-Analog Converter (DAC)
    1. 11.1 Introduction
      1. 11.1.1 DAC Related Collateral
      2. 11.1.2 Features
      3. 11.1.3 Block Diagram
    2. 11.2 Using the DAC
      1. 11.2.1 Initialization Sequence
      2. 11.2.2 DAC Offset Adjustment
      3. 11.2.3 EPWMSYNCPER Signal
    3. 11.3 Lock Registers
    4. 11.4 Software
      1. 11.4.1 DAC Examples
        1. 11.4.1.1 Buffered DAC Enable
        2. 11.4.1.2 Buffered DAC Random
        3. 11.4.1.3 Buffered DAC Sine (buffdac_sine)
    5. 11.5 DAC Registers
      1. 11.5.1 DAC Base Addresses
      2. 11.5.2 DAC_REGS Registers
      3. 11.5.3 DAC Registers to Driverlib Functions
  14. 12Comparator Subsystem (CMPSS)
    1. 12.1 Introduction
      1. 12.1.1 CMPSS Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 Block Diagram
    2. 12.2 Comparator
    3. 12.3 Reference DAC
    4. 12.4 Ramp Generator
      1. 12.4.1 Ramp Generator Overview
      2. 12.4.2 Ramp Generator Behavior
      3. 12.4.3 Ramp Generator Behavior at Corner Cases
    5. 12.5 Digital Filter
      1. 12.5.1 Filter Initialization Sequence
    6. 12.6 Using the CMPSS
      1. 12.6.1 LATCHCLR and EPWMSYNCPER Signals
      2. 12.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 12.6.3 Calibrating the CMPSS
      4. 12.6.4 Enabling and Disabling the CMPSS Clock
    7. 12.7 Software
      1. 12.7.1 CMPSS Examples
        1. 12.7.1.1 CMPSS Asynchronous Trip
        2. 12.7.1.2 CMPSS Digital Filter Configuration
    8. 12.8 CMPSS Registers
      1. 12.8.1 CMPSS Base Addresses
      2. 12.8.2 CMPSS_REGS Registers
      3. 12.8.3 CMPSS Registers to Driverlib Functions
  15. 13Sigma Delta Filter Module (SDFM)
    1. 13.1  Introduction
      1. 13.1.1 SDFM Related Collateral
      2. 13.1.2 Features
      3. 13.1.3 Block Diagram
    2. 13.2  Configuring Device Pins
    3. 13.3  Input Control Unit
    4. 13.4  Sinc Filter
      1. 13.4.1 Data Rate and Latency of the Sinc Filter
    5. 13.5  Data (Primary) Filter Unit
      1. 13.5.1 32-bit or 16-bit Data Filter Output Representation
      2. 13.5.2 SDSYNC Event
    6. 13.6  Comparator (Secondary) Filter Unit
      1. 13.6.1 Higher Threshold (HLT) Comparator
      2. 13.6.2 Lower Threshold (LLT) Comparator
    7. 13.7  Theoretical SDFM Filter Output
    8. 13.8  Interrupt Unit
      1. 13.8.1 SDFM (SDINT) Interrupt Sources
    9. 13.9  Register Descriptions
    10. 13.10 Software
      1. 13.10.1 SDFM Examples
    11. 13.11 SDFM Registers
      1. 13.11.1 SDFM Base Addresses
      2. 13.11.2 SDFM_REGS Registers
      3. 13.11.3 SDFM Registers to Driverlib Functions
  16. 14Enhanced Pulse Width Modulator (ePWM)
    1. 14.1  Introduction
      1. 14.1.1 EPWM Related Collateral
      2. 14.1.2 Submodule Overview
    2. 14.2  Configuring Device Pins
    3. 14.3  ePWM Modules Overview
    4. 14.4  Time-Base (TB) Submodule
      1. 14.4.1 Purpose of the Time-Base Submodule
      2. 14.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 14.4.3 Calculating PWM Period and Frequency
        1. 14.4.3.1 Time-Base Period Shadow Register
        2. 14.4.3.2 Time-Base Clock Synchronization
        3. 14.4.3.3 Time-Base Counter Synchronization
      4. 14.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 14.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 14.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 14.4.7 Global Load
        1. 14.4.7.1 Global Load Pulse Pre-Scalar
        2. 14.4.7.2 One-Shot Load Mode
        3. 14.4.7.3 One-Shot Sync Mode
    5. 14.5  Counter-Compare (CC) Submodule
      1. 14.5.1 Purpose of the Counter-Compare Submodule
      2. 14.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 14.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 14.5.4 Count Mode Timing Waveforms
    6. 14.6  Action-Qualifier (AQ) Submodule
      1. 14.6.1 Purpose of the Action-Qualifier Submodule
      2. 14.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 14.6.3 Action-Qualifier Event Priority
      4. 14.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 14.6.5 Configuration Requirements for Common Waveforms
    7. 14.7  Dead-Band Generator (DB) Submodule
      1. 14.7.1 Purpose of the Dead-Band Submodule
      2. 14.7.2 Dead-band Submodule Additional Operating Modes
      3. 14.7.3 Operational Highlights for the Dead-Band Submodule
    8. 14.8  PWM Chopper (PC) Submodule
      1. 14.8.1 Purpose of the PWM Chopper Submodule
      2. 14.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 14.8.3 Waveforms
        1. 14.8.3.1 One-Shot Pulse
        2. 14.8.3.2 Duty Cycle Control
    9. 14.9  Trip-Zone (TZ) Submodule
      1. 14.9.1 Purpose of the Trip-Zone Submodule
      2. 14.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 14.9.2.1 Trip-Zone Configurations
      3. 14.9.3 Generating Trip Event Interrupts
    10. 14.10 Event-Trigger (ET) Submodule
      1. 14.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 14.11 Digital Compare (DC) Submodule
      1. 14.11.1 Purpose of the Digital Compare Submodule
      2. 14.11.2 Enhanced Trip Action Using CMPSS
      3. 14.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 14.11.4 Operation Highlights of the Digital Compare Submodule
        1. 14.11.4.1 Digital Compare Events
        2. 14.11.4.2 Event Filtering
        3. 14.11.4.3 Valley Switching
    12. 14.12 ePWM Crossbar (X-BAR)
    13. 14.13 Applications to Power Topologies
      1. 14.13.1  Overview of Multiple Modules
      2. 14.13.2  Key Configuration Capabilities
      3. 14.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 14.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 14.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 14.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 14.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 14.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 14.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 14.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 14.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 14.14 High-Resolution Pulse Width Modulator (HRPWM)
      1. 14.14.1 Operational Description of HRPWM
        1. 14.14.1.1 Controlling the HRPWM Capabilities
        2. 14.14.1.2 HRPWM Source Clock
        3. 14.14.1.3 Configuring the HRPWM
        4. 14.14.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 14.14.1.5 Principle of Operation
          1. 14.14.1.5.1 Edge Positioning
          2. 14.14.1.5.2 Scaling Considerations
          3. 14.14.1.5.3 Duty Cycle Range Limitation
          4. 14.14.1.5.4 High-Resolution Period
            1. 14.14.1.5.4.1 High-Resolution Period Configuration
        6. 14.14.1.6 Deadband High-Resolution Operation
        7. 14.14.1.7 Scale Factor Optimizing Software (SFO)
        8. 14.14.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 14.14.1.8.1 #Defines for HRPWM Header Files
          2. 14.14.1.8.2 Implementing a Simple Buck Converter
            1. 14.14.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 14.14.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 14.14.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 14.14.1.8.3.1 PWM DAC Function Initialization Code
            2. 14.14.1.8.3.2 PWM DAC Function Run-Time Code
      2. 14.14.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 14.14.2.1 Scale Factor Optimizer Function - int SFO()
        2. 14.14.2.2 Software Usage
          1. 14.14.2.2.1 A Sample of How to Add "Include" Files
          2.        730
          3. 14.14.2.2.2 Declaring an Element
          4.        732
          5. 14.14.2.2.3 Initializing With a Scale Factor Value
          6.        734
          7. 14.14.2.2.4 SFO Function Calls
    15. 14.15 ePWM Registers
      1. 14.15.1 ePWM Base Addresses
      2. 14.15.2 EPWM_REGS Registers
      3. 14.15.3 Register to Driverlib Function Mapping
        1. 14.15.3.1 EPWM Registers to Driverlib Functions
        2. 14.15.3.2 HRPWM Registers to Driverlib Functions
  17. 15Enhanced Capture (eCAP)
    1. 15.1 Introduction
      1. 15.1.1 Features
      2. 15.1.2 ECAP Related Collateral
    2. 15.2 Description
    3. 15.3 Configuring Device Pins for the eCAP
    4. 15.4 Capture and APWM Operating Mode
    5. 15.5 Capture Mode Description
      1. 15.5.1  Event Prescaler
      2. 15.5.2  Edge Polarity Select and Qualifier
      3. 15.5.3  Continuous/One-Shot Control
      4. 15.5.4  32-Bit Counter and Phase Control
      5. 15.5.5  CAP1-CAP4 Registers
      6. 15.5.6  eCAP Synchronization
        1. 15.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 15.5.7  Interrupt Control
      8. 15.5.8  DMA Interrupt
      9. 15.5.9  Shadow Load and Lockout Control
      10. 15.5.10 APWM Mode Operation
    6. 15.6 Application of the eCAP Module
      1. 15.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 15.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 15.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 15.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 15.7 Application of the APWM Mode
      1. 15.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 15.8 Software
      1. 15.8.1 ECAP Examples
        1. 15.8.1.1 eCAP APWM Example
        2. 15.8.1.2 eCAP Capture PWM Example
        3. 15.8.1.3 eCAP APWM Phase-shift Example
        4. 15.8.1.4 eCAP Software Sync Example
    9. 15.9 eCAP Registers
      1. 15.9.1 eCAP Base Addresses
      2. 15.9.2 ECAP_REGS Registers
      3. 15.9.3 ECAP Registers to Driverlib Functions
  18. 16Enhanced Quadrature Encoder Pulse (eQEP)
    1. 16.1  Introduction
      1. 16.1.1 EQEP Related Collateral
    2. 16.2  Configuring Device Pins
    3. 16.3  Description
      1. 16.3.1 EQEP Inputs
      2. 16.3.2 Functional Description
      3. 16.3.3 eQEP Memory Map
    4. 16.4  Quadrature Decoder Unit (QDU)
      1. 16.4.1 Position Counter Input Modes
        1. 16.4.1.1 Quadrature Count Mode
        2. 16.4.1.2 Direction-Count Mode
        3. 16.4.1.3 Up-Count Mode
        4. 16.4.1.4 Down-Count Mode
      2. 16.4.2 eQEP Input Polarity Selection
      3. 16.4.3 Position-Compare Sync Output
    5. 16.5  Position Counter and Control Unit (PCCU)
      1. 16.5.1 Position Counter Operating Modes
        1. 16.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 16.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 16.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 16.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 16.5.2 Position Counter Latch
        1. 16.5.2.1 Index Event Latch
        2. 16.5.2.2 Strobe Event Latch
      3. 16.5.3 Position Counter Initialization
      4. 16.5.4 eQEP Position-compare Unit
    6. 16.6  eQEP Edge Capture Unit
    7. 16.7  eQEP Watchdog
    8. 16.8  eQEP Unit Timer Base
    9. 16.9  eQEP Interrupt Structure
    10. 16.10 eQEP Registers
      1. 16.10.1 eQEP Base Addresses
      2. 16.10.2 EQEP_REGS Registers
      3. 16.10.3 EQEP Registers to Driverlib Functions
  19. 17Serial Peripheral Interface (SPI)
    1. 17.1 Introduction
      1. 17.1.1 Features
      2. 17.1.2 SPI Related Collateral
      3. 17.1.3 Block Diagram
    2. 17.2 System-Level Integration
      1. 17.2.1 SPI Module Signals
      2. 17.2.2 Configuring Device Pins
        1. 17.2.2.1 GPIOs Required for High-Speed Mode
      3. 17.2.3 SPI Interrupts
      4. 17.2.4 DMA Support
    3. 17.3 SPI Operation
      1. 17.3.1  Introduction to Operation
      2. 17.3.2  Master Mode
      3. 17.3.3  Slave Mode
      4. 17.3.4  Data Format
        1. 17.3.4.1 Transmission of Bit from SPIRXBUF
      5. 17.3.5  Baud Rate Selection
        1. 17.3.5.1 Baud Rate Determination
        2. 17.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 17.3.6  SPI Clocking Schemes
      7. 17.3.7  SPI FIFO Description
      8. 17.3.8  SPI DMA Transfers
        1. 17.3.8.1 Transmitting Data Using SPI with DMA
        2. 17.3.8.2 Receiving Data Using SPI with DMA
      9. 17.3.9  SPI High-Speed Mode
      10. 17.3.10 SPI 3-Wire Mode Description
    4. 17.4 Programming Procedure
      1. 17.4.1 Initialization Upon Reset
      2. 17.4.2 Configuring the SPI
      3. 17.4.3 Configuring the SPI for High-Speed Mode
      4. 17.4.4 Data Transfer Example
      5. 17.4.5 SPI 3-Wire Mode Code Examples
        1. 17.4.5.1 3-Wire Master Mode Transmit
        2.       847
          1. 17.4.5.2.1 3-Wire Master Mode Receive
        3.       849
          1. 17.4.5.2.1 3-Wire Slave Mode Transmit
        4.       851
          1. 17.4.5.2.1 3-Wire Slave Mode Receive
      6. 17.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 17.5 Software
      1. 17.5.1 SPI Examples
        1. 17.5.1.1 SPI Digital Loopback
        2. 17.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 17.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 17.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 17.5.1.5 SPI Digital Loopback with DMA
        6. 17.5.1.6 SPI EEPROM
        7. 17.5.1.7 SPI DMA EEPROM
    6. 17.6 SPI Registers
      1. 17.6.1 SPI Base Addresses
      2. 17.6.2 SPI_REGS Registers
      3. 17.6.3 SPI Registers to Driverlib Functions
  20. 18Serial Communications Interface (SCI)
    1. 18.1  Introduction
      1. 18.1.1 Features
      2. 18.1.2 SCI Related Collateral
      3. 18.1.3 Block Diagram
    2. 18.2  Architecture
    3. 18.3  SCI Module Signal Summary
    4. 18.4  Configuring Device Pins
    5. 18.5  Multiprocessor and Asynchronous Communication Modes
    6. 18.6  SCI Programmable Data Format
    7. 18.7  SCI Multiprocessor Communication
      1. 18.7.1 Recognizing the Address Byte
      2. 18.7.2 Controlling the SCI TX and RX Features
      3. 18.7.3 Receipt Sequence
    8. 18.8  Idle-Line Multiprocessor Mode
      1. 18.8.1 Idle-Line Mode Steps
      2. 18.8.2 Block Start Signal
      3. 18.8.3 Wake-Up Temporary (WUT) Flag
        1. 18.8.3.1 Sending a Block Start Signal
      4. 18.8.4 Receiver Operation
    9. 18.9  Address-Bit Multiprocessor Mode
      1. 18.9.1 Sending an Address
    10. 18.10 SCI Communication Format
      1. 18.10.1 Receiver Signals in Communication Modes
      2. 18.10.2 Transmitter Signals in Communication Modes
    11. 18.11 SCI Port Interrupts
      1. 18.11.1 Break Detect
    12. 18.12 SCI Baud Rate Calculations
    13. 18.13 SCI Enhanced Features
      1. 18.13.1 SCI FIFO Description
      2. 18.13.2 SCI Auto-Baud
      3. 18.13.3 Autobaud-Detect Sequence
    14. 18.14 Software
      1. 18.14.1 SCI Examples
    15. 18.15 SCI Registers
      1. 18.15.1 SCI Base Addresses
      2. 18.15.2 SCI_REGS Registers
      3. 18.15.3 SCI Registers to Driverlib Functions
  21. 19Inter-Integrated Circuit Module (I2C)
    1. 19.1 Introduction
      1. 19.1.1 I2C Related Collateral
      2. 19.1.2 Features
      3. 19.1.3 Features Not Supported
      4. 19.1.4 Functional Overview
      5. 19.1.5 Clock Generation
      6. 19.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 19.1.6.1 Formula for the Master Clock Period
    2. 19.2 Configuring Device Pins
    3. 19.3 I2C Module Operational Details
      1. 19.3.1  Input and Output Voltage Levels
      2. 19.3.2  Selecting Pullup Resistors
      3. 19.3.3  Data Validity
      4. 19.3.4  Operating Modes
      5. 19.3.5  I2C Module START and STOP Conditions
      6. 19.3.6  Non-repeat Mode versus Repeat Mode
      7. 19.3.7  Serial Data Formats
        1. 19.3.7.1 7-Bit Addressing Format
        2. 19.3.7.2 10-Bit Addressing Format
        3. 19.3.7.3 Free Data Format
        4. 19.3.7.4 Using a Repeated START Condition
      8. 19.3.8  Clock Synchronization
      9. 19.3.9  Arbitration
      10. 19.3.10 Digital Loopback Mode
      11. 19.3.11 NACK Bit Generation
    4. 19.4 Interrupt Requests Generated by the I2C Module
      1. 19.4.1 Basic I2C Interrupt Requests
      2. 19.4.2 I2C FIFO Interrupts
    5. 19.5 Resetting or Disabling the I2C Module
    6. 19.6 Software
      1. 19.6.1 I2C Examples
        1. 19.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 19.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 19.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 19.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 19.6.1.5 I2C EEPROM
        6. 19.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 19.6.1.7 I2C EEPROM
        8. 19.6.1.8 I2C controller target communication using FIFO interrupts
        9. 19.6.1.9 I2C EEPROM
    7. 19.7 I2C Registers
      1. 19.7.1 I2C Base Addresses
      2. 19.7.2 I2C_REGS Registers
      3. 19.7.3 I2C Registers to Driverlib Functions
  22. 20Multichannel Buffered Serial Port (McBSP)
    1. 20.1  Introduction
      1. 20.1.1 MCBSP Related Collateral
      2. 20.1.2 Features of the McBSPs
      3. 20.1.3 McBSP Pins/Signals
        1. 20.1.3.1 McBSP Generic Block Diagram
    2. 20.2  Configuring Device Pins
    3. 20.3  McBSP Operation
      1. 20.3.1 Data Transfer Process of McBSPs
        1. 20.3.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits
        2. 20.3.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits
      2. 20.3.2 Companding (Compressing and Expanding) Data
        1. 20.3.2.1 Companding Formats
        2. 20.3.2.2 Capability to Compand Internal Data
        3. 20.3.2.3 Reversing Bit Order: Option to Transfer LSB First
      3. 20.3.3 Clocking and Framing Data
        1. 20.3.3.1 Clocking
        2. 20.3.3.2 Serial Words
        3. 20.3.3.3 Frames and Frame Synchronization
        4. 20.3.3.4 Generating Transmit and Receive Interrupts
          1. 20.3.3.4.1 Detecting Frame-Synchronization Pulses, Even in Reset State
        5. 20.3.3.5 Ignoring Frame-Synchronization Pulses
        6. 20.3.3.6 Frame Frequency
        7. 20.3.3.7 Maximum Frame Frequency
      4. 20.3.4 Frame Phases
        1. 20.3.4.1 Number of Phases, Words, and Bits Per Frame
        2. 20.3.4.2 Single-Phase Frame Example
        3. 20.3.4.3 Dual-Phase Frame Example
        4. 20.3.4.4 Implementing the AC97 Standard With a Dual-Phase Frame
      5. 20.3.5 McBSP Reception
      6. 20.3.6 McBSP Transmission
      7. 20.3.7 Interrupts and DMA Events Generated by a McBSP
    4. 20.4  McBSP Sample Rate Generator
      1. 20.4.1 Block Diagram
        1. 20.4.1.1 Clock Generation in the Sample Rate Generator
        2. 20.4.1.2 Choosing an Input Clock
        3. 20.4.1.3 Choosing a Polarity for the Input Clock
        4. 20.4.1.4 Choosing a Frequency for the Output Clock (CLKG)
          1. 20.4.1.4.1 CLKG Frequency
        5. 20.4.1.5 Keeping CLKG Synchronized to External MCLKR
      2. 20.4.2 Frame Synchronization Generation in the Sample Rate Generator
        1. 20.4.2.1 Choosing the Width of the Frame-Synchronization Pulse on FSG
        2. 20.4.2.2 Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
        3. 20.4.2.3 Keeping FSG Synchronized to an External Clock
      3. 20.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock
        1. 20.4.3.1 Operating the Transmitter Synchronously with the Receiver
        2. 20.4.3.2 Synchronization Examples
      4. 20.4.4 Reset and Initialization Procedure for the Sample Rate Generator
    5. 20.5  McBSP Exception/Error Conditions
      1. 20.5.1 Types of Errors
      2. 20.5.2 Overrun in the Receiver
        1. 20.5.2.1 Example of Overrun Condition
        2. 20.5.2.2 Example of Preventing Overrun Condition
      3. 20.5.3 Unexpected Receive Frame-Synchronization Pulse
        1. 20.5.3.1 Possible Responses to Receive Frame-Synchronization Pulses
        2. 20.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
        3. 20.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
      4. 20.5.4 Overwrite in the Transmitter
        1. 20.5.4.1 Example of Overwrite Condition
        2. 20.5.4.2 Preventing Overwrites
      5. 20.5.5 Underflow in the Transmitter
        1. 20.5.5.1 Example of the Underflow Condition
        2. 20.5.5.2 Example of Preventing Underflow Condition
      6. 20.5.6 Unexpected Transmit Frame-Synchronization Pulse
        1. 20.5.6.1 Possible Responses to Transmit Frame-Synchronization Pulses
        2. 20.5.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse
        3. 20.5.6.3 Preventing Unexpected Transmit Frame-Synchronization Pulses
    6. 20.6  Multichannel Selection Modes
      1. 20.6.1 Channels, Blocks, and Partitions
      2. 20.6.2 Multichannel Selection
      3. 20.6.3 Configuring a Frame for Multichannel Selection
      4. 20.6.4 Using Two Partitions
        1. 20.6.4.1 Assigning Blocks to Partitions A and B
        2. 20.6.4.2 Reassigning Blocks During Reception/Transmission
      5. 20.6.5 Using Eight Partitions
      6. 20.6.6 Receive Multichannel Selection Mode
      7. 20.6.7 Transmit Multichannel Selection Modes
        1. 20.6.7.1 Disabling/Enabling Versus Masking/Unmasking
        2. 20.6.7.2 Activity on McBSP Pins for Different Values of XMCM
      8. 20.6.8 Using Interrupts Between Block Transfers
    7. 20.7  SPI Operation Using the Clock Stop Mode
      1. 20.7.1 SPI Protocol
      2. 20.7.2 Clock Stop Mode
      3. 20.7.3 Enable and Configure the Clock Stop Mode
      4. 20.7.4 Clock Stop Mode Timing Diagrams
      5. 20.7.5 Procedure for Configuring a McBSP for SPI Operation
      6. 20.7.6 McBSP as the SPI Master
      7. 20.7.7 McBSP as an SPI Slave
    8. 20.8  Receiver Configuration
      1. 20.8.1  Programming the McBSP Registers for the Desired Receiver Operation
      2. 20.8.2  Resetting and Enabling the Receiver
        1. 20.8.2.1 Reset Considerations
      3. 20.8.3  Set the Receiver Pins to Operate as McBSP Pins
      4. 20.8.4  Digital Loopback Mode
      5. 20.8.5  Clock Stop Mode
      6. 20.8.6  Receive Multichannel Selection Mode
      7. 20.8.7  Receive Frame Phases
      8. 20.8.8  Receive Word Lengths
        1. 20.8.8.1 Word Length Bits
      9. 20.8.9  Receive Frame Length
        1. 20.8.9.1 Selected Frame Length
      10. 20.8.10 Receive Frame-Synchronization Ignore Function
        1. 20.8.10.1 Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
        2. 20.8.10.2 Examples of Effects of RFIG
      11. 20.8.11 Receive Companding Mode
        1. 20.8.11.1 Companding
        2. 20.8.11.2 Format of Expanded Data
        3. 20.8.11.3 Companding Internal Data
        4. 20.8.11.4 Option to Receive LSB First
      12. 20.8.12 Receive Data Delay
        1. 20.8.12.1 Data Delay
        2. 20.8.12.2 0-Bit Data Delay
        3. 20.8.12.3 2-Bit Data Delay
      13. 20.8.13 Receive Sign-Extension and Justification Mode
        1. 20.8.13.1 Sign-Extension and the Justification
      14. 20.8.14 Receive Interrupt Mode
      15. 20.8.15 Receive Frame-Synchronization Mode
        1. 20.8.15.1 Receive Frame-Synchronization Modes
      16. 20.8.16 Receive Frame-Synchronization Polarity
        1. 20.8.16.1 Frame-Synchronization Pulses, Clock Signals, and Their Polarities
        2. 20.8.16.2 Frame-Synchronization Period and the Frame-Synchronization Pulse Width
      17. 20.8.17 Receive Clock Mode
        1. 20.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
      18. 20.8.18 Receive Clock Polarity
        1. 20.8.18.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      19. 20.8.19 SRG Clock Divide-Down Value
        1. 20.8.19.1 Sample Rate Generator Clock Divider
      20. 20.8.20 SRG Clock Synchronization Mode
      21. 20.8.21 SRG Clock Mode (Choose an Input Clock)
      22. 20.8.22 SRG Input Clock Polarity
        1. 20.8.22.1 Using CLKXP/CLKRP to Choose an Input Clock Polarity
    9. 20.9  Transmitter Configuration
      1. 20.9.1  Programming the McBSP Registers for the Desired Transmitter Operation
      2. 20.9.2  Resetting and Enabling the Transmitter
        1. 20.9.2.1 Reset Considerations
      3. 20.9.3  Set the Transmitter Pins to Operate as McBSP Pins
      4. 20.9.4  Digital Loopback Mode
      5. 20.9.5  Clock Stop Mode
      6. 20.9.6  Transmit Multichannel Selection Mode
      7. 20.9.7  XCERs Used in the Transmit Multichannel Selection Mode
      8. 20.9.8  Transmit Frame Phases
      9. 20.9.9  Transmit Word Lengths
        1. 20.9.9.1 Word Length Bits
      10. 20.9.10 Transmit Frame Length
        1. 20.9.10.1 Selected Frame Length
      11. 20.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function
        1. 20.9.11.1 Unexpected Frame-Synchronization Pulses and Frame-Synchronization Ignore
        2. 20.9.11.2 Examples Showing the Effects of XFIG
      12. 20.9.12 Transmit Companding Mode
        1. 20.9.12.1 Companding
        2. 20.9.12.2 Format for Data To Be Compressed
        3. 20.9.12.3 Capability to Compand Internal Data
        4. 20.9.12.4 Option to Transmit LSB First
      13. 20.9.13 Transmit Data Delay
        1. 20.9.13.1 Data Delay
        2. 20.9.13.2 0-Bit Data Delay
        3. 20.9.13.3 2-Bit Data Delay
      14. 20.9.14 Transmit DXENA Mode
      15. 20.9.15 Transmit Interrupt Mode
      16. 20.9.16 Transmit Frame-Synchronization Mode
        1. 20.9.16.1 Other Considerations
      17. 20.9.17 Transmit Frame-Synchronization Polarity
        1. 20.9.17.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      18. 20.9.18 SRG Frame-Synchronization Period and Pulse Width
        1. 20.9.18.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
      19. 20.9.19 Transmit Clock Mode
        1. 20.9.19.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
        2. 20.9.19.2 Other Considerations
      20. 20.9.20 Transmit Clock Polarity
        1. 20.9.20.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
    10. 20.10 Emulation and Reset Considerations
      1. 20.10.1 McBSP Emulation Mode
      2. 20.10.2 Resetting and Initializing McBSPs
        1. 20.10.2.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
        2. 20.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
        3. 20.10.2.3 McBSP Initialization Procedure
        4. 20.10.2.4 Resetting the Transmitter While the Receiver is Running
          1. 20.10.2.4.1 Resetting and Configuring McBSP Transmitter While McBSP Receiver Running
    11. 20.11 Data Packing Examples
      1. 20.11.1 Data Packing Using Frame Length and Word Length
      2. 20.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function
    12. 20.12 Interrupt Generation
      1. 20.12.1 McBSP Receive Interrupt Generation
      2. 20.12.2 McBSP Transmit Interrupt Generation
      3. 20.12.3 Error Flags
    13. 20.13 McBSP Modes
    14. 20.14 Special Case: External Device is the Transmit Frame Master
    15. 20.15 Software
      1. 20.15.1 MCBSP Examples
    16. 20.16 McBSP Registers
      1. 20.16.1 McBSP Base Addresses
      2. 20.16.2 McBSP_REGS Registers
      3. 20.16.3 MCBSP Registers to Driverlib Functions
  23. 21Controller Area Network (CAN)
    1. 21.1  Introduction
      1. 21.1.1 DCAN Related Collateral
      2. 21.1.2 Features
      3. 21.1.3 Block Diagram
        1. 21.1.3.1 CAN Core
        2. 21.1.3.2 Message Handler
        3. 21.1.3.3 Message RAM
        4. 21.1.3.4 Registers and Message Object Access (IFx)
    2. 21.2  Functional Description
      1. 21.2.1 Configuring Device Pins
      2. 21.2.2 Address/Data Bus Bridge
    3. 21.3  Operating Modes
      1. 21.3.1 Initialization
      2. 21.3.2 CAN Message Transfer (Normal Operation)
        1. 21.3.2.1 Disabled Automatic Retransmission
        2. 21.3.2.2 Auto-Bus-On
      3. 21.3.3 Test Modes
        1. 21.3.3.1 Silent Mode
        2. 21.3.3.2 Loopback Mode
        3. 21.3.3.3 External Loopback Mode
        4. 21.3.3.4 Loopback Combined with Silent Mode
    4. 21.4  Multiple Clock Source
    5. 21.5  Interrupt Functionality
      1. 21.5.1 Message Object Interrupts
      2. 21.5.2 Status Change Interrupts
      3. 21.5.3 Error Interrupts
      4. 21.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 21.5.5 Interrupt Topologies
    6. 21.6  Parity Check Mechanism
      1. 21.6.1 Behavior on Parity Error
    7. 21.7  Debug Mode
    8. 21.8  Module Initialization
    9. 21.9  Configuration of Message Objects
      1. 21.9.1 Configuration of a Transmit Object for Data Frames
      2. 21.9.2 Configuration of a Transmit Object for Remote Frames
      3. 21.9.3 Configuration of a Single Receive Object for Data Frames
      4. 21.9.4 Configuration of a Single Receive Object for Remote Frames
      5. 21.9.5 Configuration of a FIFO Buffer
    10. 21.10 Message Handling
      1. 21.10.1  Message Handler Overview
      2. 21.10.2  Receive/Transmit Priority
      3. 21.10.3  Transmission of Messages in Event Driven CAN Communication
      4. 21.10.4  Updating a Transmit Object
      5. 21.10.5  Changing a Transmit Object
      6. 21.10.6  Acceptance Filtering of Received Messages
      7. 21.10.7  Reception of Data Frames
      8. 21.10.8  Reception of Remote Frames
      9. 21.10.9  Reading Received Messages
      10. 21.10.10 Requesting New Data for a Receive Object
      11. 21.10.11 Storing Received Messages in FIFO Buffers
      12. 21.10.12 Reading from a FIFO Buffer
    11. 21.11 CAN Bit Timing
      1. 21.11.1 Bit Time and Bit Rate
        1. 21.11.1.1 Synchronization Segment
        2. 21.11.1.2 Propagation Time Segment
        3. 21.11.1.3 Phase Buffer Segments and Synchronization
        4. 21.11.1.4 Oscillator Tolerance Range
      2. 21.11.2 Configuration of the CAN Bit Timing
        1. 21.11.2.1 Calculation of the Bit Timing Parameters
        2. 21.11.2.2 Example for Bit Timing at High Baudrate
        3. 21.11.2.3 Example for Bit Timing at Low Baudrate
    12. 21.12 Message Interface Register Sets
      1. 21.12.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 21.12.2 Message Interface Register Set 3 (IF3)
    13. 21.13 Message RAM
      1. 21.13.1 Structure of Message Objects
      2. 21.13.2 Addressing Message Objects in RAM
      3. 21.13.3 Message RAM Representation in Debug Mode
    14. 21.14 Software
      1. 21.14.1 CAN Examples
    15. 21.15 CAN Registers
      1. 21.15.1 CAN Base Addresses
      2. 21.15.2 CAN_REGS Registers
      3. 21.15.3 CAN Registers to Driverlib Functions
  24. 22Universal Serial Bus (USB) Controller
    1. 22.1 Introduction
      1. 22.1.1 Features
      2. 22.1.2 USB Related Collateral
      3. 22.1.3 Block Diagram
        1. 22.1.3.1 Signal Description
        2. 22.1.3.2 VBus Recommendations
    2. 22.2 Functional Description
      1. 22.2.1 Operation as a Device
        1. 22.2.1.1 Control and Configurable Endpoints
          1. 22.2.1.1.1 IN Transactions as a Device
          2. 22.2.1.1.2 Out Transactions as a Device
          3. 22.2.1.1.3 Scheduling
          4. 22.2.1.1.4 Additional Actions
          5. 22.2.1.1.5 Device Mode Suspend
          6. 22.2.1.1.6 Start of Frame
          7. 22.2.1.1.7 USB Reset
          8. 22.2.1.1.8 Connect/Disconnect
      2. 22.2.2 Operation as a Host
        1. 22.2.2.1 Endpoint Registers
        2. 22.2.2.2 IN Transactions as a Host
        3. 22.2.2.3 OUT Transactions as a Host
        4. 22.2.2.4 Transaction Scheduling
        5. 22.2.2.5 USB Hubs
        6. 22.2.2.6 Babble
        7. 22.2.2.7 Host SUSPEND
        8. 22.2.2.8 USB RESET
        9. 22.2.2.9 Connect/Disconnect
      3. 22.2.3 DMA Operation
      4. 22.2.4 Address/Data Bus Bridge
    3. 22.3 Initialization and Configuration
      1. 22.3.1 Pin Configuration
      2. 22.3.2 Endpoint Configuration
    4. 22.4 USB Global Interrupts
    5. 22.5 Software
      1. 22.5.1 USB Examples
    6. 22.6 USB Registers
      1. 22.6.1 USB Base Address
      2. 22.6.2 USB Register Map
      3. 22.6.3 Register Descriptions
        1. 22.6.3.1  USB Device Functional Address Register (USBFADDR), offset 0x000
        2. 22.6.3.2  USB Power Management Register (USBPOWER), offset 0x001
        3. 22.6.3.3  USB Transmit Interrupt Status Register
        4. 22.6.3.4  USB Receive Interrupt Status Register
        5. 22.6.3.5  USB Transmit Interrupt Enable Register
        6. 22.6.3.6  USB Receive Interrupt Enable Register
        7. 22.6.3.7  USB General Interrupt Status Register (USBIS), offset 0x00A
        8. 22.6.3.8  USB Interrupt Enable Register (USBIE), offset 0x00B
        9. 22.6.3.9  USB Frame Value Register (USBFRAME), offset 0x00C
        10. 22.6.3.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E
        11. 22.6.3.11 USB Test Mode Register (USBTEST), offset 0x00F
        12. 22.6.3.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[3])
        13. 22.6.3.13 USB Device Control Register (USBDEVCTL), offset 0x060
        14. 22.6.3.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062
        15. 22.6.3.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063
        16. 22.6.3.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064
        17. 22.6.3.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066
        18. 22.6.3.18 USB Connect Timing Register (USBCONTIM), offset 0x07A
        19. 22.6.3.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset 0x07D
        20. 22.6.3.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset 0x07E
        21. 22.6.3.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-USBTXFUNCADDR[n])
        22. 22.6.3.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-USBTXHUBADDR[n])
        23. 22.6.3.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[n])
        24. 22.6.3.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-USBRXFUNCADDR[n)
        25. 22.6.3.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-USBRXHUBADDR[n])
        26. 22.6.3.26 USB Receive Hub Port Endpoint n Register (USBRXHUBPORT[1]-USBRXHUBPORT[n])
        27. 22.6.3.27 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[n])
        28. 22.6.3.28 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102
        29. 22.6.3.29 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103
        30. 22.6.3.30 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108
        31. 22.6.3.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A
        32. 22.6.3.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B
        33. 22.6.3.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[n])
        34. 22.6.3.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-USBTXCSRH[n])
        35. 22.6.3.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[n])
        36. 22.6.3.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-USBRXCSRL[n])
        37. 22.6.3.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-USBRXCSRH[n])
        38. 22.6.3.38 USB Receive Byte Count Endpoint n Register (USBRXCOUNT[1]-USBRXCOUNT[n])
        39. 22.6.3.39 USB Host Transmit Configure Type Endpoint n Registers (USBTXTYPE[1]-USBTXTYPE[n])
        40. 22.6.3.40 USB Host Transmit Interval Endpoint n Registers (USBTXINTERVAL[1]-USBTXINTERVAL[n])
        41. 22.6.3.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[n])
        42. 22.6.3.42 USB Host Receive Polling Interval Endpoint n Registers (USBRXINTERVAL[1]-USBRXINTERVAL[n])
        43. 22.6.3.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-USBRQPKTCOUNT[n])
        44. 22.6.3.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340
        45. 22.6.3.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342
        46. 22.6.3.46 USB External Power Control Register (USBEPC), offset 0x400
        47. 22.6.3.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404
        48. 22.6.3.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408
        49. 22.6.3.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C
        50. 22.6.3.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410
        51. 22.6.3.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414
        52. 22.6.3.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418
        53. 22.6.3.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C
        54. 22.6.3.54 USB DMA Select Register (USBDMASEL), offset 0x450
      4. 22.6.4 USB Registers to Driverlib Functions
  25. 23External Memory Interface (EMIF)
    1. 23.1 Introduction
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 EMIF Related Collateral
      3. 23.1.3 Features
        1. 23.1.3.1 Asynchronous Memory Support
        2. 23.1.3.2 Synchronous DRAM Memory Support
      4. 23.1.4 Functional Block Diagram
      5. 23.1.5 Configuring Device Pins
    2. 23.2 EMIF Module Architecture
      1. 23.2.1  EMIF Clock Control
      2. 23.2.2  EMIF Requests
      3. 23.2.3  EMIF Signal Descriptions
      4. 23.2.4  EMIF Signal Multiplexing Control
      5. 23.2.5  SDRAM Controller and Interface
        1. 23.2.5.1  SDRAM Commands
        2. 23.2.5.2  Interfacing to SDRAM
        3. 23.2.5.3  SDRAM Configuration Registers
        4. 23.2.5.4  SDRAM Auto-Initialization Sequence
        5. 23.2.5.5  SDRAM Configuration Procedure
        6. 23.2.5.6  EMIF Refresh Controller
          1. 23.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 23.2.5.7  Self-Refresh Mode
        8. 23.2.5.8  Power-Down Mode
        9. 23.2.5.9  SDRAM Read Operation
        10. 23.2.5.10 SDRAM Write Operations
        11. 23.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 23.2.6  Asynchronous Controller and Interface
        1. 23.2.6.1 Interfacing to Asynchronous Memory
        2. 23.2.6.2 Accessing Larger Asynchronous Memories
        3. 23.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 23.2.6.4 Read and Write Operations in Normal Mode
          1. 23.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 23.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 23.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 23.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 23.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 23.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 23.2.7  Data Bus Parking
      8. 23.2.8  Reset and Initialization Considerations
      9. 23.2.9  Interrupt Support
        1. 23.2.9.1 Interrupt Events
      10. 23.2.10 DMA Event Support
      11. 23.2.11 EMIF Signal Multiplexing
      12. 23.2.12 Memory Map
      13. 23.2.13 Priority and Arbitration
      14. 23.2.14 System Considerations
        1. 23.2.14.1 Asynchronous Request Times
      15. 23.2.15 Power Management
        1. 23.2.15.1 Power Management Using Self-Refresh Mode
        2. 23.2.15.2 Power Management Using Power Down Mode
      16. 23.2.16 Emulation Considerations
    3. 23.3 Example Configuration
      1. 23.3.1 Hardware Interface
      2. 23.3.2 Software Configuration
        1. 23.3.2.1 Configuring the SDRAM Interface
          1. 23.3.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 23.3.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 23.3.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 23.3.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 23.3.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 23.3.2.2 Configuring the Flash Interface
          1. 23.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    4. 23.4 EMIF Registers
      1. 23.4.1 EMIF Base Addresses
      2. 23.4.2 EMIF_REGS Registers
      3. 23.4.3 EMIF1_CONFIG_REGS Registers
      4. 23.4.4 EMIF2_CONFIG_REGS Registers
      5. 23.4.5 EMIF Registers to Driverlib Functions
  26. 24Configurable Logic Block (CLB)
    1. 24.1 Introduction
      1. 24.1.1 CLB Related Collateral
    2. 24.2 Description
      1. 24.2.1 CLB Clock
    3. 24.3 CLB Input/Output Connection
      1. 24.3.1 Overview
      2. 24.3.2 CLB Input Selection
      3. 24.3.3 CLB Output Selection
      4. 24.3.4 CLB Output Signal Multiplexer
    4. 24.4 CLB Tile
      1. 24.4.1 Static Switch Block
      2. 24.4.2 Counter Block
        1. 24.4.2.1 Counter Description
        2. 24.4.2.2 Counter Operation
      3. 24.4.3 FSM Block
      4. 24.4.4 LUT4 Block
      5. 24.4.5 Output LUT Block
      6. 24.4.6 High Level Controller (HLC)
        1. 24.4.6.1 High Level Controller Events
        2. 24.4.6.2 High Level Controller Instructions
        3. 24.4.6.3 <Src> and <Dest>
        4. 24.4.6.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 24.5 CPU Interface
      1. 24.5.1 Register Description
      2. 24.5.2 Non-Memory Mapped Registers
    6. 24.6 DMA Access
    7. 24.7 Software
      1. 24.7.1 CLB Examples
        1. 24.7.1.1  CLB Empty Project
        2. 24.7.1.2  CLB Combinational Logic
        3. 24.7.1.3  CLB GPIO Input Filter
        4. 24.7.1.4  CLB Auxilary PWM
        5. 24.7.1.5  CLB PWM Protection
        6. 24.7.1.6  CLB Event Window
        7. 24.7.1.7  CLB Signal Generator
        8. 24.7.1.8  CLB State Machine
        9. 24.7.1.9  CLB External Signal AND Gate
        10. 24.7.1.10 CLB Timer
        11. 24.7.1.11 CLB Timer Two States
        12. 24.7.1.12 CLB Interrupt Tag
        13. 24.7.1.13 CLB Output Intersect
        14. 24.7.1.14 CLB PUSH PULL
        15. 24.7.1.15 CLB Multi Tile
        16. 24.7.1.16 CLB Tile to Tile Delay
        17. 24.7.1.17 CLB based One-shot PWM
        18. 24.7.1.18 CLB Trip Zone Timestamp
    8. 24.8 CLB Registers
      1. 24.8.1 CLB Base Addresses
      2. 24.8.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 24.8.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 24.8.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 24.8.5 CLB Registers to Driverlib Functions
  27. 25Revision History

7.10.3 GPIO_DATA_REGS Registers

Table 7-112 lists the memory-mapped registers for the GPIO_DATA_REGS registers. All register offset addresses not listed in Table 7-112 should be considered as reserved locations and the register contents should not be modified.

Table 7-112 GPIO_DATA_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hGPADATGPIO A Data Register (GPIO0 to 31)Go
2hGPASETGPIO A Data Set Register (GPIO0 to 31)Go
4hGPACLEARGPIO A Data Clear Register (GPIO0 to 31)Go
6hGPATOGGLEGPIO A Data Toggle Register (GPIO0 to 31)Go
8hGPBDATGPIO B Data Register (GPIO32 to 63)Go
AhGPBSETGPIO B Data Set Register (GPIO32 to 63)Go
ChGPBCLEARGPIO B Data Clear Register (GPIO32 to 63)Go
EhGPBTOGGLEGPIO B Data Toggle Register (GPIO32 to 63)Go
10hGPCDATGPIO C Data Register (GPIO64 to 95)Go
12hGPCSETGPIO C Data Set Register (GPIO64 to 95)Go
14hGPCCLEARGPIO C Data Clear Register (GPIO64 to 95)Go
16hGPCTOGGLEGPIO C Data Toggle Register (GPIO64 to 95)Go
18hGPDDATGPIO D Data Register (GPIO96 to 127)Go
1AhGPDSETGPIO D Data Set Register (GPIO96 to 127)Go
1ChGPDCLEARGPIO D Data Clear Register (GPIO96 to 127)Go
1EhGPDTOGGLEGPIO D Data Toggle Register (GPIO96 to 127)Go
20hGPEDATGPIO E Data Register (GPIO128 to 159)Go
22hGPESETGPIO E Data Set Register (GPIO128 to 159)Go
24hGPECLEARGPIO E Data Clear Register (GPIO128 to 159)Go
26hGPETOGGLEGPIO E Data Toggle Register (GPIO128 to 159)Go
28hGPFDATGPIO F Data Register (GPIO160 to 168)Go
2AhGPFSETGPIO F Data Set Register (GPIO160 to 168)Go
2ChGPFCLEARGPIO F Data Clear Register (GPIO160 to 168)Go
2EhGPFTOGGLEGPIO F Data Toggle Register (GPIO160 to 168)Go

Complex bit access types are encoded to fit into small table cells. Table 7-113 shows the codes that are used for access types in this section.

Table 7-113 GPIO_DATA_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

7.10.3.1 GPADAT Register (Offset = 0h) [Reset = 00000000h]

GPADAT is shown in Figure 7-102 and described in Table 7-114.

Return to the Summary Table.

GPIO A Data Register (GPIO0 to 31)

Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.

Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO Output mode

A system reset will clear all bits and latched values to zero.

NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are necessary, the entire register should be written at one time.

Figure 7-102 GPADAT Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-114 GPADAT Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hData Register for this pin

Reset type: SYSRSn

30GPIO30R/W0hData Register for this pin

Reset type: SYSRSn

29GPIO29R/W0hData Register for this pin

Reset type: SYSRSn

28GPIO28R/W0hData Register for this pin

Reset type: SYSRSn

27GPIO27R/W0hData Register for this pin

Reset type: SYSRSn

26GPIO26R/W0hData Register for this pin

Reset type: SYSRSn

25GPIO25R/W0hData Register for this pin

Reset type: SYSRSn

24GPIO24R/W0hData Register for this pin

Reset type: SYSRSn

23GPIO23R/W0hData Register for this pin

Reset type: SYSRSn

22GPIO22R/W0hData Register for this pin

Reset type: SYSRSn

21GPIO21R/W0hData Register for this pin

Reset type: SYSRSn

20GPIO20R/W0hData Register for this pin

Reset type: SYSRSn

19GPIO19R/W0hData Register for this pin

Reset type: SYSRSn

18GPIO18R/W0hData Register for this pin

Reset type: SYSRSn

17GPIO17R/W0hData Register for this pin

Reset type: SYSRSn

16GPIO16R/W0hData Register for this pin

Reset type: SYSRSn

15GPIO15R/W0hData Register for this pin

Reset type: SYSRSn

14GPIO14R/W0hData Register for this pin

Reset type: SYSRSn

13GPIO13R/W0hData Register for this pin

Reset type: SYSRSn

12GPIO12R/W0hData Register for this pin

Reset type: SYSRSn

11GPIO11R/W0hData Register for this pin

Reset type: SYSRSn

10GPIO10R/W0hData Register for this pin

Reset type: SYSRSn

9GPIO9R/W0hData Register for this pin

Reset type: SYSRSn

8GPIO8R/W0hData Register for this pin

Reset type: SYSRSn

7GPIO7R/W0hData Register for this pin

Reset type: SYSRSn

6GPIO6R/W0hData Register for this pin

Reset type: SYSRSn

5GPIO5R/W0hData Register for this pin

Reset type: SYSRSn

4GPIO4R/W0hData Register for this pin

Reset type: SYSRSn

3GPIO3R/W0hData Register for this pin

Reset type: SYSRSn

2GPIO2R/W0hData Register for this pin

Reset type: SYSRSn

1GPIO1R/W0hData Register for this pin

Reset type: SYSRSn

0GPIO0R/W0hData Register for this pin

Reset type: SYSRSn

7.10.3.2 GPASET Register (Offset = 2h) [Reset = 00000000h]

GPASET is shown in Figure 7-103 and described in Table 7-115.

Return to the Summary Table.

GPIO A Data Set Register (GPIO0 to 31)

Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-103 GPASET Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-115 GPASET Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hOutput Set bit for this pin

Reset type: SYSRSn

30GPIO30R/W0hOutput Set bit for this pin

Reset type: SYSRSn

29GPIO29R/W0hOutput Set bit for this pin

Reset type: SYSRSn

28GPIO28R/W0hOutput Set bit for this pin

Reset type: SYSRSn

27GPIO27R/W0hOutput Set bit for this pin

Reset type: SYSRSn

26GPIO26R/W0hOutput Set bit for this pin

Reset type: SYSRSn

25GPIO25R/W0hOutput Set bit for this pin

Reset type: SYSRSn

24GPIO24R/W0hOutput Set bit for this pin

Reset type: SYSRSn

23GPIO23R/W0hOutput Set bit for this pin

Reset type: SYSRSn

22GPIO22R/W0hOutput Set bit for this pin

Reset type: SYSRSn

21GPIO21R/W0hOutput Set bit for this pin

Reset type: SYSRSn

20GPIO20R/W0hOutput Set bit for this pin

Reset type: SYSRSn

19GPIO19R/W0hOutput Set bit for this pin

Reset type: SYSRSn

18GPIO18R/W0hOutput Set bit for this pin

Reset type: SYSRSn

17GPIO17R/W0hOutput Set bit for this pin

Reset type: SYSRSn

16GPIO16R/W0hOutput Set bit for this pin

Reset type: SYSRSn

15GPIO15R/W0hOutput Set bit for this pin

Reset type: SYSRSn

14GPIO14R/W0hOutput Set bit for this pin

Reset type: SYSRSn

13GPIO13R/W0hOutput Set bit for this pin

Reset type: SYSRSn

12GPIO12R/W0hOutput Set bit for this pin

Reset type: SYSRSn

11GPIO11R/W0hOutput Set bit for this pin

Reset type: SYSRSn

10GPIO10R/W0hOutput Set bit for this pin

Reset type: SYSRSn

9GPIO9R/W0hOutput Set bit for this pin

Reset type: SYSRSn

8GPIO8R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7GPIO7R/W0hOutput Set bit for this pin

Reset type: SYSRSn

6GPIO6R/W0hOutput Set bit for this pin

Reset type: SYSRSn

5GPIO5R/W0hOutput Set bit for this pin

Reset type: SYSRSn

4GPIO4R/W0hOutput Set bit for this pin

Reset type: SYSRSn

3GPIO3R/W0hOutput Set bit for this pin

Reset type: SYSRSn

2GPIO2R/W0hOutput Set bit for this pin

Reset type: SYSRSn

1GPIO1R/W0hOutput Set bit for this pin

Reset type: SYSRSn

0GPIO0R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7.10.3.3 GPACLEAR Register (Offset = 4h) [Reset = 00000000h]

GPACLEAR is shown in Figure 7-104 and described in Table 7-116.

Return to the Summary Table.

GPIO A Data Clear Register (GPIO0 to 31)

Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-104 GPACLEAR Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-116 GPACLEAR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

30GPIO30R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

29GPIO29R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

28GPIO28R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

27GPIO27R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

26GPIO26R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

25GPIO25R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

24GPIO24R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

23GPIO23R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

22GPIO22R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

21GPIO21R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

20GPIO20R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

19GPIO19R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

18GPIO18R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

17GPIO17R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

16GPIO16R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

15GPIO15R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

14GPIO14R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

13GPIO13R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

12GPIO12R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

11GPIO11R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

10GPIO10R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

9GPIO9R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

8GPIO8R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7GPIO7R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

6GPIO6R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

5GPIO5R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

4GPIO4R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

3GPIO3R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

2GPIO2R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

1GPIO1R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

0GPIO0R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7.10.3.4 GPATOGGLE Register (Offset = 6h) [Reset = 00000000h]

GPATOGGLE is shown in Figure 7-105 and described in Table 7-117.

Return to the Summary Table.

GPIO A Data Toggle Register (GPIO0 to 31)

Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-105 GPATOGGLE Register
3130292827262524
GPIO31GPIO30GPIO29GPIO28GPIO27GPIO26GPIO25GPIO24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO23GPIO22GPIO21GPIO20GPIO19GPIO18GPIO17GPIO16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10GPIO9GPIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-117 GPATOGGLE Register Field Descriptions
BitFieldTypeResetDescription
31GPIO31R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

30GPIO30R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

29GPIO29R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

28GPIO28R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

27GPIO27R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

26GPIO26R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

25GPIO25R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

24GPIO24R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

23GPIO23R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

22GPIO22R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

21GPIO21R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

20GPIO20R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

19GPIO19R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

18GPIO18R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

17GPIO17R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

16GPIO16R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

15GPIO15R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

14GPIO14R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

13GPIO13R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

12GPIO12R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

11GPIO11R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

10GPIO10R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

9GPIO9R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

8GPIO8R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7GPIO7R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

6GPIO6R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

5GPIO5R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

4GPIO4R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

3GPIO3R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

2GPIO2R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

1GPIO1R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

0GPIO0R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7.10.3.5 GPBDAT Register (Offset = 8h) [Reset = 00000000h]

GPBDAT is shown in Figure 7-106 and described in Table 7-118.

Return to the Summary Table.

GPIO B Data Register (GPIO32 to 63)

Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.

Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO Output mode

A system reset will clear all bits and latched values to zero.

NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are necessary, the entire register should be written at one time.

Figure 7-106 GPBDAT Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-118 GPBDAT Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hData Register for this pin

Reset type: SYSRSn

30GPIO62R/W0hData Register for this pin

Reset type: SYSRSn

29GPIO61R/W0hData Register for this pin

Reset type: SYSRSn

28GPIO60R/W0hData Register for this pin

Reset type: SYSRSn

27GPIO59R/W0hData Register for this pin

Reset type: SYSRSn

26GPIO58R/W0hData Register for this pin

Reset type: SYSRSn

25GPIO57R/W0hData Register for this pin

Reset type: SYSRSn

24GPIO56R/W0hData Register for this pin

Reset type: SYSRSn

23GPIO55R/W0hData Register for this pin

Reset type: SYSRSn

22GPIO54R/W0hData Register for this pin

Reset type: SYSRSn

21GPIO53R/W0hData Register for this pin

Reset type: SYSRSn

20GPIO52R/W0hData Register for this pin

Reset type: SYSRSn

19GPIO51R/W0hData Register for this pin

Reset type: SYSRSn

18GPIO50R/W0hData Register for this pin

Reset type: SYSRSn

17GPIO49R/W0hData Register for this pin

Reset type: SYSRSn

16GPIO48R/W0hData Register for this pin

Reset type: SYSRSn

15GPIO47R/W0hData Register for this pin

Reset type: SYSRSn

14GPIO46R/W0hData Register for this pin

Reset type: SYSRSn

13GPIO45R/W0hData Register for this pin

Reset type: SYSRSn

12GPIO44R/W0hData Register for this pin

Reset type: SYSRSn

11GPIO43R/W0hData Register for this pin

Reset type: SYSRSn

10GPIO42R/W0hData Register for this pin

Reset type: SYSRSn

9GPIO41R/W0hData Register for this pin

Reset type: SYSRSn

8GPIO40R/W0hData Register for this pin

Reset type: SYSRSn

7GPIO39R/W0hData Register for this pin

Reset type: SYSRSn

6GPIO38R/W0hData Register for this pin

Reset type: SYSRSn

5GPIO37R/W0hData Register for this pin

Reset type: SYSRSn

4GPIO36R/W0hData Register for this pin

Reset type: SYSRSn

3GPIO35R/W0hData Register for this pin

Reset type: SYSRSn

2GPIO34R/W0hData Register for this pin

Reset type: SYSRSn

1GPIO33R/W0hData Register for this pin

Reset type: SYSRSn

0GPIO32R/W0hData Register for this pin

Reset type: SYSRSn

7.10.3.6 GPBSET Register (Offset = Ah) [Reset = 00000000h]

GPBSET is shown in Figure 7-107 and described in Table 7-119.

Return to the Summary Table.

GPIO B Data Set Register (GPIO32 to 63)

Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-107 GPBSET Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-119 GPBSET Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hOutput Set bit for this pin

Reset type: SYSRSn

30GPIO62R/W0hOutput Set bit for this pin

Reset type: SYSRSn

29GPIO61R/W0hOutput Set bit for this pin

Reset type: SYSRSn

28GPIO60R/W0hOutput Set bit for this pin

Reset type: SYSRSn

27GPIO59R/W0hOutput Set bit for this pin

Reset type: SYSRSn

26GPIO58R/W0hOutput Set bit for this pin

Reset type: SYSRSn

25GPIO57R/W0hOutput Set bit for this pin

Reset type: SYSRSn

24GPIO56R/W0hOutput Set bit for this pin

Reset type: SYSRSn

23GPIO55R/W0hOutput Set bit for this pin

Reset type: SYSRSn

22GPIO54R/W0hOutput Set bit for this pin

Reset type: SYSRSn

21GPIO53R/W0hOutput Set bit for this pin

Reset type: SYSRSn

20GPIO52R/W0hOutput Set bit for this pin

Reset type: SYSRSn

19GPIO51R/W0hOutput Set bit for this pin

Reset type: SYSRSn

18GPIO50R/W0hOutput Set bit for this pin

Reset type: SYSRSn

17GPIO49R/W0hOutput Set bit for this pin

Reset type: SYSRSn

16GPIO48R/W0hOutput Set bit for this pin

Reset type: SYSRSn

15GPIO47R/W0hOutput Set bit for this pin

Reset type: SYSRSn

14GPIO46R/W0hOutput Set bit for this pin

Reset type: SYSRSn

13GPIO45R/W0hOutput Set bit for this pin

Reset type: SYSRSn

12GPIO44R/W0hOutput Set bit for this pin

Reset type: SYSRSn

11GPIO43R/W0hOutput Set bit for this pin

Reset type: SYSRSn

10GPIO42R/W0hOutput Set bit for this pin

Reset type: SYSRSn

9GPIO41R/W0hOutput Set bit for this pin

Reset type: SYSRSn

8GPIO40R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7GPIO39R/W0hOutput Set bit for this pin

Reset type: SYSRSn

6GPIO38R/W0hOutput Set bit for this pin

Reset type: SYSRSn

5GPIO37R/W0hOutput Set bit for this pin

Reset type: SYSRSn

4GPIO36R/W0hOutput Set bit for this pin

Reset type: SYSRSn

3GPIO35R/W0hOutput Set bit for this pin

Reset type: SYSRSn

2GPIO34R/W0hOutput Set bit for this pin

Reset type: SYSRSn

1GPIO33R/W0hOutput Set bit for this pin

Reset type: SYSRSn

0GPIO32R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7.10.3.7 GPBCLEAR Register (Offset = Ch) [Reset = 00000000h]

GPBCLEAR is shown in Figure 7-108 and described in Table 7-120.

Return to the Summary Table.

GPIO B Data Clear Register (GPIO32 to 63)

Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-108 GPBCLEAR Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-120 GPBCLEAR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

30GPIO62R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

29GPIO61R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

28GPIO60R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

27GPIO59R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

26GPIO58R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

25GPIO57R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

24GPIO56R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

23GPIO55R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

22GPIO54R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

21GPIO53R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

20GPIO52R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

19GPIO51R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

18GPIO50R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

17GPIO49R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

16GPIO48R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

15GPIO47R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

14GPIO46R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

13GPIO45R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

12GPIO44R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

11GPIO43R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

10GPIO42R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

9GPIO41R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

8GPIO40R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7GPIO39R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

6GPIO38R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

5GPIO37R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

4GPIO36R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

3GPIO35R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

2GPIO34R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

1GPIO33R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

0GPIO32R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7.10.3.8 GPBTOGGLE Register (Offset = Eh) [Reset = 00000000h]

GPBTOGGLE is shown in Figure 7-109 and described in Table 7-121.

Return to the Summary Table.

GPIO B Data Toggle Register (GPIO32 to 63)

Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-109 GPBTOGGLE Register
3130292827262524
GPIO63GPIO62GPIO61GPIO60GPIO59GPIO58GPIO57GPIO56
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO55GPIO54GPIO53GPIO52GPIO51GPIO50GPIO49GPIO48
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO47GPIO46GPIO45GPIO44GPIO43GPIO42GPIO41GPIO40
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO39GPIO38GPIO37GPIO36GPIO35GPIO34GPIO33GPIO32
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-121 GPBTOGGLE Register Field Descriptions
BitFieldTypeResetDescription
31GPIO63R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

30GPIO62R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

29GPIO61R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

28GPIO60R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

27GPIO59R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

26GPIO58R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

25GPIO57R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

24GPIO56R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

23GPIO55R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

22GPIO54R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

21GPIO53R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

20GPIO52R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

19GPIO51R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

18GPIO50R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

17GPIO49R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

16GPIO48R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

15GPIO47R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

14GPIO46R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

13GPIO45R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

12GPIO44R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

11GPIO43R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

10GPIO42R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

9GPIO41R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

8GPIO40R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7GPIO39R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

6GPIO38R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

5GPIO37R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

4GPIO36R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

3GPIO35R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

2GPIO34R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

1GPIO33R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

0GPIO32R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7.10.3.9 GPCDAT Register (Offset = 10h) [Reset = 00000000h]

GPCDAT is shown in Figure 7-110 and described in Table 7-122.

Return to the Summary Table.

GPIO C Data Register (GPIO64 to 95)

Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.

Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO Output mode

A system reset will clear all bits and latched values to zero.

NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are necessary, the entire register should be written at one time.

Figure 7-110 GPCDAT Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-122 GPCDAT Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hData Register for this pin

Reset type: SYSRSn

30GPIO94R/W0hData Register for this pin

Reset type: SYSRSn

29GPIO93R/W0hData Register for this pin

Reset type: SYSRSn

28GPIO92R/W0hData Register for this pin

Reset type: SYSRSn

27GPIO91R/W0hData Register for this pin

Reset type: SYSRSn

26GPIO90R/W0hData Register for this pin

Reset type: SYSRSn

25GPIO89R/W0hData Register for this pin

Reset type: SYSRSn

24GPIO88R/W0hData Register for this pin

Reset type: SYSRSn

23GPIO87R/W0hData Register for this pin

Reset type: SYSRSn

22GPIO86R/W0hData Register for this pin

Reset type: SYSRSn

21GPIO85R/W0hData Register for this pin

Reset type: SYSRSn

20GPIO84R/W0hData Register for this pin

Reset type: SYSRSn

19GPIO83R/W0hData Register for this pin

Reset type: SYSRSn

18GPIO82R/W0hData Register for this pin

Reset type: SYSRSn

17GPIO81R/W0hData Register for this pin

Reset type: SYSRSn

16GPIO80R/W0hData Register for this pin

Reset type: SYSRSn

15GPIO79R/W0hData Register for this pin

Reset type: SYSRSn

14GPIO78R/W0hData Register for this pin

Reset type: SYSRSn

13GPIO77R/W0hData Register for this pin

Reset type: SYSRSn

12GPIO76R/W0hData Register for this pin

Reset type: SYSRSn

11GPIO75R/W0hData Register for this pin

Reset type: SYSRSn

10GPIO74R/W0hData Register for this pin

Reset type: SYSRSn

9GPIO73R/W0hData Register for this pin

Reset type: SYSRSn

8GPIO72R/W0hData Register for this pin

Reset type: SYSRSn

7GPIO71R/W0hData Register for this pin

Reset type: SYSRSn

6GPIO70R/W0hData Register for this pin

Reset type: SYSRSn

5GPIO69R/W0hData Register for this pin

Reset type: SYSRSn

4GPIO68R/W0hData Register for this pin

Reset type: SYSRSn

3GPIO67R/W0hData Register for this pin

Reset type: SYSRSn

2GPIO66R/W0hData Register for this pin

Reset type: SYSRSn

1GPIO65R/W0hData Register for this pin

Reset type: SYSRSn

0GPIO64R/W0hData Register for this pin

Reset type: SYSRSn

7.10.3.10 GPCSET Register (Offset = 12h) [Reset = 00000000h]

GPCSET is shown in Figure 7-111 and described in Table 7-123.

Return to the Summary Table.

GPIO C Data Set Register (GPIO64 to 95)

Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-111 GPCSET Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-123 GPCSET Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hOutput Set bit for this pin

Reset type: SYSRSn

30GPIO94R/W0hOutput Set bit for this pin

Reset type: SYSRSn

29GPIO93R/W0hOutput Set bit for this pin

Reset type: SYSRSn

28GPIO92R/W0hOutput Set bit for this pin

Reset type: SYSRSn

27GPIO91R/W0hOutput Set bit for this pin

Reset type: SYSRSn

26GPIO90R/W0hOutput Set bit for this pin

Reset type: SYSRSn

25GPIO89R/W0hOutput Set bit for this pin

Reset type: SYSRSn

24GPIO88R/W0hOutput Set bit for this pin

Reset type: SYSRSn

23GPIO87R/W0hOutput Set bit for this pin

Reset type: SYSRSn

22GPIO86R/W0hOutput Set bit for this pin

Reset type: SYSRSn

21GPIO85R/W0hOutput Set bit for this pin

Reset type: SYSRSn

20GPIO84R/W0hOutput Set bit for this pin

Reset type: SYSRSn

19GPIO83R/W0hOutput Set bit for this pin

Reset type: SYSRSn

18GPIO82R/W0hOutput Set bit for this pin

Reset type: SYSRSn

17GPIO81R/W0hOutput Set bit for this pin

Reset type: SYSRSn

16GPIO80R/W0hOutput Set bit for this pin

Reset type: SYSRSn

15GPIO79R/W0hOutput Set bit for this pin

Reset type: SYSRSn

14GPIO78R/W0hOutput Set bit for this pin

Reset type: SYSRSn

13GPIO77R/W0hOutput Set bit for this pin

Reset type: SYSRSn

12GPIO76R/W0hOutput Set bit for this pin

Reset type: SYSRSn

11GPIO75R/W0hOutput Set bit for this pin

Reset type: SYSRSn

10GPIO74R/W0hOutput Set bit for this pin

Reset type: SYSRSn

9GPIO73R/W0hOutput Set bit for this pin

Reset type: SYSRSn

8GPIO72R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7GPIO71R/W0hOutput Set bit for this pin

Reset type: SYSRSn

6GPIO70R/W0hOutput Set bit for this pin

Reset type: SYSRSn

5GPIO69R/W0hOutput Set bit for this pin

Reset type: SYSRSn

4GPIO68R/W0hOutput Set bit for this pin

Reset type: SYSRSn

3GPIO67R/W0hOutput Set bit for this pin

Reset type: SYSRSn

2GPIO66R/W0hOutput Set bit for this pin

Reset type: SYSRSn

1GPIO65R/W0hOutput Set bit for this pin

Reset type: SYSRSn

0GPIO64R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7.10.3.11 GPCCLEAR Register (Offset = 14h) [Reset = 00000000h]

GPCCLEAR is shown in Figure 7-112 and described in Table 7-124.

Return to the Summary Table.

GPIO C Data Clear Register (GPIO64 to 95)

Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-112 GPCCLEAR Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-124 GPCCLEAR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

30GPIO94R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

29GPIO93R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

28GPIO92R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

27GPIO91R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

26GPIO90R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

25GPIO89R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

24GPIO88R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

23GPIO87R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

22GPIO86R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

21GPIO85R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

20GPIO84R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

19GPIO83R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

18GPIO82R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

17GPIO81R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

16GPIO80R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

15GPIO79R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

14GPIO78R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

13GPIO77R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

12GPIO76R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

11GPIO75R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

10GPIO74R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

9GPIO73R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

8GPIO72R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7GPIO71R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

6GPIO70R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

5GPIO69R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

4GPIO68R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

3GPIO67R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

2GPIO66R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

1GPIO65R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

0GPIO64R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7.10.3.12 GPCTOGGLE Register (Offset = 16h) [Reset = 00000000h]

GPCTOGGLE is shown in Figure 7-113 and described in Table 7-125.

Return to the Summary Table.

GPIO C Data Toggle Register (GPIO64 to 95)

Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-113 GPCTOGGLE Register
3130292827262524
GPIO95GPIO94GPIO93GPIO92GPIO91GPIO90GPIO89GPIO88
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO87GPIO86GPIO85GPIO84GPIO83GPIO82GPIO81GPIO80
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO79GPIO78GPIO77GPIO76GPIO75GPIO74GPIO73GPIO72
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO71GPIO70GPIO69GPIO68GPIO67GPIO66GPIO65GPIO64
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-125 GPCTOGGLE Register Field Descriptions
BitFieldTypeResetDescription
31GPIO95R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

30GPIO94R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

29GPIO93R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

28GPIO92R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

27GPIO91R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

26GPIO90R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

25GPIO89R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

24GPIO88R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

23GPIO87R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

22GPIO86R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

21GPIO85R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

20GPIO84R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

19GPIO83R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

18GPIO82R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

17GPIO81R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

16GPIO80R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

15GPIO79R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

14GPIO78R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

13GPIO77R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

12GPIO76R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

11GPIO75R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

10GPIO74R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

9GPIO73R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

8GPIO72R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7GPIO71R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

6GPIO70R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

5GPIO69R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

4GPIO68R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

3GPIO67R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

2GPIO66R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

1GPIO65R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

0GPIO64R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7.10.3.13 GPDDAT Register (Offset = 18h) [Reset = 00000000h]

GPDDAT is shown in Figure 7-114 and described in Table 7-126.

Return to the Summary Table.

GPIO D Data Register (GPIO96 to 127)

Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.

Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO Output mode

A system reset will clear all bits and latched values to zero.

NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are necessary, the entire register should be written at one time.

Figure 7-114 GPDDAT Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122GPIO121GPIO120
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO119GPIO118GPIO117GPIO116GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-126 GPDDAT Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hData Register for this pin

Reset type: SYSRSn

30GPIO126R/W0hData Register for this pin

Reset type: SYSRSn

29GPIO125R/W0hData Register for this pin

Reset type: SYSRSn

28GPIO124R/W0hData Register for this pin

Reset type: SYSRSn

27GPIO123R/W0hData Register for this pin

Reset type: SYSRSn

26GPIO122R/W0hData Register for this pin

Reset type: SYSRSn

25GPIO121R/W0hData Register for this pin

Reset type: SYSRSn

24GPIO120R/W0hData Register for this pin

Reset type: SYSRSn

23GPIO119R/W0hData Register for this pin

Reset type: SYSRSn

22GPIO118R/W0hData Register for this pin

Reset type: SYSRSn

21GPIO117R/W0hData Register for this pin

Reset type: SYSRSn

20GPIO116R/W0hData Register for this pin

Reset type: SYSRSn

19GPIO115R/W0hData Register for this pin

Reset type: SYSRSn

18GPIO114R/W0hData Register for this pin

Reset type: SYSRSn

17GPIO113R/W0hData Register for this pin

Reset type: SYSRSn

16GPIO112R/W0hData Register for this pin

Reset type: SYSRSn

15GPIO111R/W0hData Register for this pin

Reset type: SYSRSn

14GPIO110R/W0hData Register for this pin

Reset type: SYSRSn

13GPIO109R/W0hData Register for this pin

Reset type: SYSRSn

12GPIO108R/W0hData Register for this pin

Reset type: SYSRSn

11GPIO107R/W0hData Register for this pin

Reset type: SYSRSn

10GPIO106R/W0hData Register for this pin

Reset type: SYSRSn

9GPIO105R/W0hData Register for this pin

Reset type: SYSRSn

8GPIO104R/W0hData Register for this pin

Reset type: SYSRSn

7GPIO103R/W0hData Register for this pin

Reset type: SYSRSn

6GPIO102R/W0hData Register for this pin

Reset type: SYSRSn

5GPIO101R/W0hData Register for this pin

Reset type: SYSRSn

4GPIO100R/W0hData Register for this pin

Reset type: SYSRSn

3GPIO99R/W0hData Register for this pin

Reset type: SYSRSn

2GPIO98R/W0hData Register for this pin

Reset type: SYSRSn

1GPIO97R/W0hData Register for this pin

Reset type: SYSRSn

0GPIO96R/W0hData Register for this pin

Reset type: SYSRSn

7.10.3.14 GPDSET Register (Offset = 1Ah) [Reset = 00000000h]

GPDSET is shown in Figure 7-115 and described in Table 7-127.

Return to the Summary Table.

GPIO D Data Set Register (GPIO96 to 127)

Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-115 GPDSET Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122GPIO121GPIO120
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO119GPIO118GPIO117GPIO116GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-127 GPDSET Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hOutput Set bit for this pin

Reset type: SYSRSn

30GPIO126R/W0hOutput Set bit for this pin

Reset type: SYSRSn

29GPIO125R/W0hOutput Set bit for this pin

Reset type: SYSRSn

28GPIO124R/W0hOutput Set bit for this pin

Reset type: SYSRSn

27GPIO123R/W0hOutput Set bit for this pin

Reset type: SYSRSn

26GPIO122R/W0hOutput Set bit for this pin

Reset type: SYSRSn

25GPIO121R/W0hOutput Set bit for this pin

Reset type: SYSRSn

24GPIO120R/W0hOutput Set bit for this pin

Reset type: SYSRSn

23GPIO119R/W0hOutput Set bit for this pin

Reset type: SYSRSn

22GPIO118R/W0hOutput Set bit for this pin

Reset type: SYSRSn

21GPIO117R/W0hOutput Set bit for this pin

Reset type: SYSRSn

20GPIO116R/W0hOutput Set bit for this pin

Reset type: SYSRSn

19GPIO115R/W0hOutput Set bit for this pin

Reset type: SYSRSn

18GPIO114R/W0hOutput Set bit for this pin

Reset type: SYSRSn

17GPIO113R/W0hOutput Set bit for this pin

Reset type: SYSRSn

16GPIO112R/W0hOutput Set bit for this pin

Reset type: SYSRSn

15GPIO111R/W0hOutput Set bit for this pin

Reset type: SYSRSn

14GPIO110R/W0hOutput Set bit for this pin

Reset type: SYSRSn

13GPIO109R/W0hOutput Set bit for this pin

Reset type: SYSRSn

12GPIO108R/W0hOutput Set bit for this pin

Reset type: SYSRSn

11GPIO107R/W0hOutput Set bit for this pin

Reset type: SYSRSn

10GPIO106R/W0hOutput Set bit for this pin

Reset type: SYSRSn

9GPIO105R/W0hOutput Set bit for this pin

Reset type: SYSRSn

8GPIO104R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7GPIO103R/W0hOutput Set bit for this pin

Reset type: SYSRSn

6GPIO102R/W0hOutput Set bit for this pin

Reset type: SYSRSn

5GPIO101R/W0hOutput Set bit for this pin

Reset type: SYSRSn

4GPIO100R/W0hOutput Set bit for this pin

Reset type: SYSRSn

3GPIO99R/W0hOutput Set bit for this pin

Reset type: SYSRSn

2GPIO98R/W0hOutput Set bit for this pin

Reset type: SYSRSn

1GPIO97R/W0hOutput Set bit for this pin

Reset type: SYSRSn

0GPIO96R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7.10.3.15 GPDCLEAR Register (Offset = 1Ch) [Reset = 00000000h]

GPDCLEAR is shown in Figure 7-116 and described in Table 7-128.

Return to the Summary Table.

GPIO D Data Clear Register (GPIO96 to 127)

Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-116 GPDCLEAR Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122GPIO121GPIO120
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO119GPIO118GPIO117GPIO116GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-128 GPDCLEAR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

30GPIO126R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

29GPIO125R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

28GPIO124R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

27GPIO123R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

26GPIO122R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

25GPIO121R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

24GPIO120R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

23GPIO119R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

22GPIO118R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

21GPIO117R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

20GPIO116R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

19GPIO115R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

18GPIO114R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

17GPIO113R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

16GPIO112R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

15GPIO111R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

14GPIO110R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

13GPIO109R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

12GPIO108R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

11GPIO107R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

10GPIO106R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

9GPIO105R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

8GPIO104R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7GPIO103R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

6GPIO102R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

5GPIO101R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

4GPIO100R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

3GPIO99R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

2GPIO98R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

1GPIO97R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

0GPIO96R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7.10.3.16 GPDTOGGLE Register (Offset = 1Eh) [Reset = 00000000h]

GPDTOGGLE is shown in Figure 7-117 and described in Table 7-129.

Return to the Summary Table.

GPIO D Data Toggle Register (GPIO96 to 127)

Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-117 GPDTOGGLE Register
3130292827262524
GPIO127GPIO126GPIO125GPIO124GPIO123GPIO122GPIO121GPIO120
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO119GPIO118GPIO117GPIO116GPIO115GPIO114GPIO113GPIO112
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO111GPIO110GPIO109GPIO108GPIO107GPIO106GPIO105GPIO104
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO103GPIO102GPIO101GPIO100GPIO99GPIO98GPIO97GPIO96
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-129 GPDTOGGLE Register Field Descriptions
BitFieldTypeResetDescription
31GPIO127R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

30GPIO126R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

29GPIO125R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

28GPIO124R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

27GPIO123R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

26GPIO122R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

25GPIO121R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

24GPIO120R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

23GPIO119R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

22GPIO118R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

21GPIO117R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

20GPIO116R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

19GPIO115R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

18GPIO114R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

17GPIO113R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

16GPIO112R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

15GPIO111R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

14GPIO110R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

13GPIO109R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

12GPIO108R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

11GPIO107R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

10GPIO106R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

9GPIO105R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

8GPIO104R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7GPIO103R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

6GPIO102R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

5GPIO101R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

4GPIO100R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

3GPIO99R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

2GPIO98R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

1GPIO97R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

0GPIO96R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7.10.3.17 GPEDAT Register (Offset = 20h) [Reset = 00000000h]

GPEDAT is shown in Figure 7-118 and described in Table 7-130.

Return to the Summary Table.

GPIO E Data Register (GPIO128 to 159)

Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.

Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO Output mode

A system reset will clear all bits and latched values to zero.

NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are necessary, the entire register should be written at one time.

Figure 7-118 GPEDAT Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145GPIO144
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO143GPIO142GPIO141GPIO140GPIO139GPIO138GPIO137GPIO136
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO135GPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-130 GPEDAT Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/W0hData Register for this pin

Reset type: SYSRSn

30GPIO158R/W0hData Register for this pin

Reset type: SYSRSn

29GPIO157R/W0hData Register for this pin

Reset type: SYSRSn

28GPIO156R/W0hData Register for this pin

Reset type: SYSRSn

27GPIO155R/W0hData Register for this pin

Reset type: SYSRSn

26GPIO154R/W0hData Register for this pin

Reset type: SYSRSn

25GPIO153R/W0hData Register for this pin

Reset type: SYSRSn

24GPIO152R/W0hData Register for this pin

Reset type: SYSRSn

23GPIO151R/W0hData Register for this pin

Reset type: SYSRSn

22GPIO150R/W0hData Register for this pin

Reset type: SYSRSn

21GPIO149R/W0hData Register for this pin

Reset type: SYSRSn

20GPIO148R/W0hData Register for this pin

Reset type: SYSRSn

19GPIO147R/W0hData Register for this pin

Reset type: SYSRSn

18GPIO146R/W0hData Register for this pin

Reset type: SYSRSn

17GPIO145R/W0hData Register for this pin

Reset type: SYSRSn

16GPIO144R/W0hData Register for this pin

Reset type: SYSRSn

15GPIO143R/W0hData Register for this pin

Reset type: SYSRSn

14GPIO142R/W0hData Register for this pin

Reset type: SYSRSn

13GPIO141R/W0hData Register for this pin

Reset type: SYSRSn

12GPIO140R/W0hData Register for this pin

Reset type: SYSRSn

11GPIO139R/W0hData Register for this pin

Reset type: SYSRSn

10GPIO138R/W0hData Register for this pin

Reset type: SYSRSn

9GPIO137R/W0hData Register for this pin

Reset type: SYSRSn

8GPIO136R/W0hData Register for this pin

Reset type: SYSRSn

7GPIO135R/W0hData Register for this pin

Reset type: SYSRSn

6GPIO134R/W0hData Register for this pin

Reset type: SYSRSn

5GPIO133R/W0hData Register for this pin

Reset type: SYSRSn

4GPIO132R/W0hData Register for this pin

Reset type: SYSRSn

3GPIO131R/W0hData Register for this pin

Reset type: SYSRSn

2GPIO130R/W0hData Register for this pin

Reset type: SYSRSn

1GPIO129R/W0hData Register for this pin

Reset type: SYSRSn

0GPIO128R/W0hData Register for this pin

Reset type: SYSRSn

7.10.3.18 GPESET Register (Offset = 22h) [Reset = 00000000h]

GPESET is shown in Figure 7-119 and described in Table 7-131.

Return to the Summary Table.

GPIO E Data Set Register (GPIO128 to 159)

Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-119 GPESET Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145GPIO144
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO143GPIO142GPIO141GPIO140GPIO139GPIO138GPIO137GPIO136
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO135GPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-131 GPESET Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/W0hOutput Set bit for this pin

Reset type: SYSRSn

30GPIO158R/W0hOutput Set bit for this pin

Reset type: SYSRSn

29GPIO157R/W0hOutput Set bit for this pin

Reset type: SYSRSn

28GPIO156R/W0hOutput Set bit for this pin

Reset type: SYSRSn

27GPIO155R/W0hOutput Set bit for this pin

Reset type: SYSRSn

26GPIO154R/W0hOutput Set bit for this pin

Reset type: SYSRSn

25GPIO153R/W0hOutput Set bit for this pin

Reset type: SYSRSn

24GPIO152R/W0hOutput Set bit for this pin

Reset type: SYSRSn

23GPIO151R/W0hOutput Set bit for this pin

Reset type: SYSRSn

22GPIO150R/W0hOutput Set bit for this pin

Reset type: SYSRSn

21GPIO149R/W0hOutput Set bit for this pin

Reset type: SYSRSn

20GPIO148R/W0hOutput Set bit for this pin

Reset type: SYSRSn

19GPIO147R/W0hOutput Set bit for this pin

Reset type: SYSRSn

18GPIO146R/W0hOutput Set bit for this pin

Reset type: SYSRSn

17GPIO145R/W0hOutput Set bit for this pin

Reset type: SYSRSn

16GPIO144R/W0hOutput Set bit for this pin

Reset type: SYSRSn

15GPIO143R/W0hOutput Set bit for this pin

Reset type: SYSRSn

14GPIO142R/W0hOutput Set bit for this pin

Reset type: SYSRSn

13GPIO141R/W0hOutput Set bit for this pin

Reset type: SYSRSn

12GPIO140R/W0hOutput Set bit for this pin

Reset type: SYSRSn

11GPIO139R/W0hOutput Set bit for this pin

Reset type: SYSRSn

10GPIO138R/W0hOutput Set bit for this pin

Reset type: SYSRSn

9GPIO137R/W0hOutput Set bit for this pin

Reset type: SYSRSn

8GPIO136R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7GPIO135R/W0hOutput Set bit for this pin

Reset type: SYSRSn

6GPIO134R/W0hOutput Set bit for this pin

Reset type: SYSRSn

5GPIO133R/W0hOutput Set bit for this pin

Reset type: SYSRSn

4GPIO132R/W0hOutput Set bit for this pin

Reset type: SYSRSn

3GPIO131R/W0hOutput Set bit for this pin

Reset type: SYSRSn

2GPIO130R/W0hOutput Set bit for this pin

Reset type: SYSRSn

1GPIO129R/W0hOutput Set bit for this pin

Reset type: SYSRSn

0GPIO128R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7.10.3.19 GPECLEAR Register (Offset = 24h) [Reset = 00000000h]

GPECLEAR is shown in Figure 7-120 and described in Table 7-132.

Return to the Summary Table.

GPIO E Data Clear Register (GPIO128 to 159)

Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-120 GPECLEAR Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145GPIO144
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO143GPIO142GPIO141GPIO140GPIO139GPIO138GPIO137GPIO136
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO135GPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-132 GPECLEAR Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

30GPIO158R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

29GPIO157R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

28GPIO156R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

27GPIO155R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

26GPIO154R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

25GPIO153R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

24GPIO152R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

23GPIO151R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

22GPIO150R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

21GPIO149R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

20GPIO148R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

19GPIO147R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

18GPIO146R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

17GPIO145R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

16GPIO144R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

15GPIO143R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

14GPIO142R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

13GPIO141R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

12GPIO140R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

11GPIO139R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

10GPIO138R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

9GPIO137R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

8GPIO136R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7GPIO135R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

6GPIO134R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

5GPIO133R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

4GPIO132R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

3GPIO131R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

2GPIO130R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

1GPIO129R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

0GPIO128R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7.10.3.20 GPETOGGLE Register (Offset = 26h) [Reset = 00000000h]

GPETOGGLE is shown in Figure 7-121 and described in Table 7-133.

Return to the Summary Table.

GPIO E Data Toggle Register (GPIO128 to 159)

Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-121 GPETOGGLE Register
3130292827262524
GPIO159GPIO158GPIO157GPIO156GPIO155GPIO154GPIO153GPIO152
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
GPIO151GPIO150GPIO149GPIO148GPIO147GPIO146GPIO145GPIO144
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
GPIO143GPIO142GPIO141GPIO140GPIO139GPIO138GPIO137GPIO136
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO135GPIO134GPIO133GPIO132GPIO131GPIO130GPIO129GPIO128
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-133 GPETOGGLE Register Field Descriptions
BitFieldTypeResetDescription
31GPIO159R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

30GPIO158R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

29GPIO157R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

28GPIO156R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

27GPIO155R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

26GPIO154R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

25GPIO153R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

24GPIO152R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

23GPIO151R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

22GPIO150R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

21GPIO149R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

20GPIO148R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

19GPIO147R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

18GPIO146R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

17GPIO145R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

16GPIO144R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

15GPIO143R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

14GPIO142R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

13GPIO141R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

12GPIO140R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

11GPIO139R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

10GPIO138R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

9GPIO137R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

8GPIO136R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7GPIO135R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

6GPIO134R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

5GPIO133R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

4GPIO132R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

3GPIO131R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

2GPIO130R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

1GPIO129R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

0GPIO128R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7.10.3.21 GPFDAT Register (Offset = 28h) [Reset = 00000000h]

GPFDAT is shown in Figure 7-122 and described in Table 7-134.

Return to the Summary Table.

GPIO F Data Register (GPIO160 to 168)
Reading this register reflects the current state of the GPIO pin regardless of which mode the GPIO is in.

Writing to this register will set the GPIO pin high or low if the pin is enabled for GPIO output mode. If the GPIO is not in output mode the value written is latched but will not be reflected on the GPIO pin or reads of the GPxDAT register. The written value latched will become active when the GPIO is put into GPIO Output mode

A system reset will clear all bits and latched values to zero.

NOTE: Bit-wise read-modify-write operations should not be performed on this register. For bit-wise operations the GPxSET, GPxCLEAR, or GPxTOGGLE registers should be used instead. If direct writes to GPxDAT are necessary, the entire register should be written at one time.

Figure 7-122 GPFDAT Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-134 GPFDAT Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8GPIO168R/W0hData Register for this pin

Reset type: SYSRSn

7GPIO167R/W0hData Register for this pin

Reset type: SYSRSn

6GPIO166R/W0hData Register for this pin

Reset type: SYSRSn

5GPIO165R/W0hData Register for this pin

Reset type: SYSRSn

4GPIO164R/W0hData Register for this pin

Reset type: SYSRSn

3GPIO163R/W0hData Register for this pin

Reset type: SYSRSn

2GPIO162R/W0hData Register for this pin

Reset type: SYSRSn

1GPIO161R/W0hData Register for this pin

Reset type: SYSRSn

0GPIO160R/W0hData Register for this pin

Reset type: SYSRSn

7.10.3.22 GPFSET Register (Offset = 2Ah) [Reset = 00000000h]

GPFSET is shown in Figure 7-123 and described in Table 7-135.

Return to the Summary Table.

GPIO F Data Set Register (GPIO160 to 168)

Writing a 1 will force GPIO output data latch to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-123 GPFSET Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-135 GPFSET Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8GPIO168R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7GPIO167R/W0hOutput Set bit for this pin

Reset type: SYSRSn

6GPIO166R/W0hOutput Set bit for this pin

Reset type: SYSRSn

5GPIO165R/W0hOutput Set bit for this pin

Reset type: SYSRSn

4GPIO164R/W0hOutput Set bit for this pin

Reset type: SYSRSn

3GPIO163R/W0hOutput Set bit for this pin

Reset type: SYSRSn

2GPIO162R/W0hOutput Set bit for this pin

Reset type: SYSRSn

1GPIO161R/W0hOutput Set bit for this pin

Reset type: SYSRSn

0GPIO160R/W0hOutput Set bit for this pin

Reset type: SYSRSn

7.10.3.23 GPFCLEAR Register (Offset = 2Ch) [Reset = 00000000h]

GPFCLEAR is shown in Figure 7-124 and described in Table 7-136.

Return to the Summary Table.

GPIO F Data Clear Register (GPIO160 to 168)

Writing a 1 will force GPIO0 output data latch to 0.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-124 GPFCLEAR Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-136 GPFCLEAR Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8GPIO168R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7GPIO167R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

6GPIO166R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

5GPIO165R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

4GPIO164R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

3GPIO163R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

2GPIO162R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

1GPIO161R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

0GPIO160R/W0hOutput Clear bit for this pin

Reset type: SYSRSn

7.10.3.24 GPFTOGGLE Register (Offset = 2Eh) [Reset = 00000000h]

GPFTOGGLE is shown in Figure 7-125 and described in Table 7-137.

Return to the Summary Table.

GPIO F Data Toggle Register (GPIO160 to 168)

Writing a 1 will toggle GPIO0 output data latch 1 to 0 or 0 to 1.
Writes of 0 are ignored.
Always reads back a 0.

Figure 7-125 GPFTOGGLE Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDGPIO168
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
GPIO167GPIO166GPIO165GPIO164GPIO163GPIO162GPIO161GPIO160
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-137 GPFTOGGLE Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27RESERVEDR/W0hReserved
26RESERVEDR/W0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21RESERVEDR/W0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11RESERVEDR/W0hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8GPIO168R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

7GPIO167R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

6GPIO166R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

5GPIO165R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

4GPIO164R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

3GPIO163R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

2GPIO162R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

1GPIO161R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn

0GPIO160R/W0hOutput Toggle Register GPIO pin

Reset type: SYSRSn