SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
Table 24-46 lists the memory-mapped registers for the CLB_LOGIC_CONTROL_REGS registers. All register offset addresses not listed in Table 24-46 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CLB_LOAD_EN | Global enable & indirect load enable control, only Global Enable Bit is LOCK protected | LOCK | Go |
2h | CLB_LOAD_ADDR | Indirect address | Go | |
4h | CLB_LOAD_DATA | Data for indirect loads | Go | |
6h | CLB_INPUT_FILTER | Input filter selection for both edge detection and synchronizers | LOCK | Go |
8h | CLB_IN_MUX_SEL_0 | Input selection to decide between Signals and GP register | LOCK | Go |
Ah | CLB_LCL_MUX_SEL_1 | Input Mux selection for local mux | LOCK | Go |
Ch | CLB_LCL_MUX_SEL_2 | Input Mux selection for local mux | LOCK | Go |
Eh | CLB_BUF_PTR | PUSH and PULL pointers | Go | |
10h | CLB_GP_REG | General purpose register for CELL inputs | Go | |
12h | CLB_OUT_EN | CELL output enable register | Go | |
14h | CLB_GLBL_MUX_SEL_1 | Global Mux select for CELL inputs | LOCK | Go |
16h | CLB_GLBL_MUX_SEL_2 | Global Mux select for CELL inputs | LOCK | Go |
20h | CLB_INTR_TAG_REG | Interrupt Tag register | Go | |
22h | CLB_LOCK | Lock control register | EALLOW | Go |
30h | CLB_DBG_R0 | R0 of High level Controller | Go | |
32h | CLB_DBG_R1 | R1 of High level Controller | Go | |
34h | CLB_DBG_R2 | R2 of High level Controller | Go | |
36h | CLB_DBG_R3 | R3 of High level Controller | Go | |
38h | CLB_DBG_C0 | Count of Unit 0 | Go | |
3Ah | CLB_DBG_C1 | Count of Unit 1 | Go | |
3Ch | CLB_DBG_C2 | Count of Unit 2 | Go | |
3Eh | CLB_DBG_OUT | Outputs of various units in the Cell | Go |
Complex bit access types are encoded to fit into small table cells. Table 24-47 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
R-1 | R -1 | Read Returns 1s |
Write Type | ||
W | W | Write |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CLB_LOAD_EN is shown in Figure 24-45 and described in Table 24-48.
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Global enable & indirect load enable control, only Global Enable Bit is LOCK protected
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STOP | GLOBAL_EN | LOAD_EN | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | RESERVED | R-0 | 0h | Reserved |
2 | STOP | R/W | 0h | This bit defines the behaviour of the sequential elements in the CELL during debug HALTs of the CPU. If this bit is set to 0, the debug HALT condition is ignored. Reset type: SYSRSn |
1 | GLOBAL_EN | R/W | 0h | This bit is a global enable signal for the logic in the CELL. This also acts as a soft reset for the CELL logic. CLB outputs (including LUTs and OUTLUTs) will be gated when this bit is cleared from 1 to 0, i.e., the CLB outputs will be low when GLOBAL_EN is low. Additionally, the FSM and AOC blocks will also be reset. Note that when this bit goes low, the COUNTER blocks and HLC are simply halted, but they will NOT be reset internally. This allows the ability to preload these submodules when GLOBAL_EN is 0. This bit is normally set after all the other configuration settings are completed. This bit is LOCK protected. Reset type: SYSRSn |
0 | LOAD_EN | R/W | 0h | A write with this bit set to 1 will pulse the Load Enable signal for the indirect register loads in the CELL. Reset type: SYSRSn |
CLB_LOAD_ADDR is shown in Figure 24-46 and described in Table 24-49.
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Indirect address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||||||||||||||||||||||||||
R-0-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R-0 | 0h | Reserved |
5-0 | ADDR | R/W | 0h | These are the address bits used for writing to the indirect address space of the CELL. Reset type: SYSRSn |
CLB_LOAD_DATA is shown in Figure 24-47 and described in Table 24-50.
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Data for indirect loads
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | This register holds the 32-bit data for writing to the indirect address space of the CELL. Reset type: SYSRSn |
CLB_INPUT_FILTER is shown in Figure 24-48 and described in Table 24-51.
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Input filter selection for both edge detection and synchronizers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SYNC7 | SYNC6 | SYNC5 | SYNC4 | SYNC3 | SYNC2 | SYNC1 | SYNC0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FIN7 | FIN6 | FIN5 | FIN4 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIN3 | FIN2 | FIN1 | FIN0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R-0 | 0h | Reserved |
23 | SYNC7 | R/W | 0h | Synchronizer Select Control for Input 7 Reset type: SYSRSn |
22 | SYNC6 | R/W | 0h | Synchronizer Select Control for Input 6 Reset type: SYSRSn |
21 | SYNC5 | R/W | 0h | Synchronizer Select Control for Input 5 Reset type: SYSRSn |
20 | SYNC4 | R/W | 0h | Synchronizer Select Control for Input 4 Reset type: SYSRSn |
19 | SYNC3 | R/W | 0h | Synchronizer Select Control for Input 3 Reset type: SYSRSn |
18 | SYNC2 | R/W | 0h | Synchronizer Select Control for Input 2 Reset type: SYSRSn |
17 | SYNC1 | R/W | 0h | Synchronizer Select Control for Input 1 Reset type: SYSRSn |
16 | SYNC0 | R/W | 0h | Synchronizer Select Control for Input 0 Reset type: SYSRSn |
15-14 | FIN7 | R/W | 0h | Input filter selection for CELL Input 7 2 bits are used to define the edge filtering . 00 : No filtering 01 : Rising edge detect 10 : Falling edge detect 11 : Any edge detect Reset type: SYSRSn |
13-12 | FIN6 | R/W | 0h | Input filter selection for CELL Input 6 2 bits are used to define the edge filtering . 00 : No filtering 01 : Rising edge detect 10 : Falling edge detect 11 : Any edge detect Reset type: SYSRSn |
11-10 | FIN5 | R/W | 0h | Input filter selection for CELL Input 5 2 bits are used to define the edge filtering . 00 : No filtering 01 : Rising edge detect 10 : Falling edge detect 11 : Any edge detect Reset type: SYSRSn |
9-8 | FIN4 | R/W | 0h | Input filter selection for CELL Input 4 2 bits are used to define the edge filtering . 00 : No filtering 01 : Rising edge detect 10 : Falling edge detect 11 : Any edge detect Reset type: SYSRSn |
7-6 | FIN3 | R/W | 0h | Input filter selection for CELL Input 3 2 bits are used to define the edge filtering . 00 : No filtering 01 : Rising edge detect 10 : Falling edge detect 11 : Any edge detect Reset type: SYSRSn |
5-4 | FIN2 | R/W | 0h | Input filter selection for CELL Input 2 2 bits are used to define the edge filtering . 00 : No filtering 01 : Rising edge detect 10 : Falling edge detect 11 : Any edge detect Reset type: SYSRSn |
3-2 | FIN1 | R/W | 0h | Input filter selection for CELL Input 1 2 bits are used to define the edge filtering . 00 : No filtering 01 : Rising edge detect 10 : Falling edge detect 11 : Any edge detect Reset type: SYSRSn |
1-0 | FIN0 | R/W | 0h | Input filter selection for CELL Input 0 2 bits are used to define the edge filtering . 00 : No filtering 01 : Rising edge detect 10 : Falling edge detect 11 : Any edge detect Reset type: SYSRSn |
CLB_IN_MUX_SEL_0 is shown in Figure 24-49 and described in Table 24-52.
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Input selection to decide between Signals and GP register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEL_GP_IN_7 | SEL_GP_IN_6 | SEL_GP_IN_5 | SEL_GP_IN_4 | SEL_GP_IN_3 | SEL_GP_IN_2 | SEL_GP_IN_1 | SEL_GP_IN_0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | SEL_GP_IN_7 | R/W | 0h | Select control for Input 7 to decide between external input and CLB_GP_REG[7] 0 : Input comes from selected external input 1 : Input comes from CLB_GP_REG[7] Reset type: SYSRSn |
6 | SEL_GP_IN_6 | R/W | 0h | Select control for Input 6 to decide between external input and CLB_GP_REG[6] 0 : Input comes from selected external input 1 : Input comes from CLB_GP_REG[6] Reset type: SYSRSn |
5 | SEL_GP_IN_5 | R/W | 0h | Select control for Input 5 to decide between external input and CLB_GP_REG[5] 0 : Input comes from selected external input 1 : Input comes from CLB_GP_REG[5] Reset type: SYSRSn |
4 | SEL_GP_IN_4 | R/W | 0h | Select control for Input 4 to decide between external input and CLB_GP_REG[4] 0 : Input comes from selected external input 1 : Input comes from CLB_GP_REG[4] Reset type: SYSRSn |
3 | SEL_GP_IN_3 | R/W | 0h | Select control for Input 3 to decide between external input and CLB_GP_REG[3] 0 : Input comes from selected external input 1 : Input comes from CLB_GP_REG[3] Reset type: SYSRSn |
2 | SEL_GP_IN_2 | R/W | 0h | Select control for Input 2 to decide between external input and CLB_GP_REG[2] 0 : Input comes from selected external input 1 : Input comes from CLB_GP_REG[2] Reset type: SYSRSn |
1 | SEL_GP_IN_1 | R/W | 0h | Select control for Input 1 to decide between external input and CLB_GP_REG[1] 0 : Input comes from selected external input 1 : Input comes from CLB_GP_REG[1] Reset type: SYSRSn |
0 | SEL_GP_IN_0 | R/W | 0h | Select control for Input 0 to decide between external input and CLB_GP_REG[0] 0 : Input comes from selected external input 1 : Input comes from CLB_GP_REG[0] Reset type: SYSRSn |
CLB_LCL_MUX_SEL_1 is shown in Figure 24-50 and described in Table 24-53.
Return to the Summary Table.
Input Mux selection for local mux
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | LCL_MUX_SEL_IN_3 | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LCL_MUX_SEL_IN_3 | LCL_MUX_SEL_IN_2 | LCL_MUX_SEL_IN_1 | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCL_MUX_SEL_IN_1 | LCL_MUX_SEL_IN_0 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19-15 | LCL_MUX_SEL_IN_3 | R/W | 0h | 5 bit MUX Select for Local MUX control for Input 3 See Local Signals and Mux Selection Table Reset type: SYSRSn |
14-10 | LCL_MUX_SEL_IN_2 | R/W | 0h | 5 bit MUX Select for Local MUX control for Input 2 See Local Signals and Mux Selection Table Reset type: SYSRSn |
9-5 | LCL_MUX_SEL_IN_1 | R/W | 0h | 5 bit MUX Select for Local MUX control for Input 1 See Local Signals and Mux Selection Table Reset type: SYSRSn |
4-0 | LCL_MUX_SEL_IN_0 | R/W | 0h | 5 bit MUX Select for Local MUX control for Input 0 See Local Signals and Mux Selection Table Reset type: SYSRSn |
CLB_LCL_MUX_SEL_2 is shown in Figure 24-51 and described in Table 24-54.
Return to the Summary Table.
Input Mux selection for local mux
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | LCL_MUX_SEL_IN_7 | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LCL_MUX_SEL_IN_7 | LCL_MUX_SEL_IN_6 | LCL_MUX_SEL_IN_5 | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCL_MUX_SEL_IN_5 | LCL_MUX_SEL_IN_4 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19-15 | LCL_MUX_SEL_IN_7 | R/W | 0h | 5 bit MUX Select for Local MUX control for Input 7 See Local Signals and Mux Selection Table Reset type: SYSRSn |
14-10 | LCL_MUX_SEL_IN_6 | R/W | 0h | 5 bit MUX Select for Local MUX control for Input 6 See Local Signals and Mux Selection Table Reset type: SYSRSn |
9-5 | LCL_MUX_SEL_IN_5 | R/W | 0h | 5 bit MUX Select for Local MUX control for Input 5 See Local Signals and Mux Selection Table Reset type: SYSRSn |
4-0 | LCL_MUX_SEL_IN_4 | R/W | 0h | 5 bit MUX Select for Local MUX control for Input 4 See Local Signals and Mux Selection Table Reset type: SYSRSn |
CLB_BUF_PTR is shown in Figure 24-52 and described in Table 24-55.
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PUSH and PULL pointers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PUSH | RESERVED | PULL | ||||||||||||||||||||||||||||
R-0-0h | R/W-0h | R-0-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R-0 | 0h | Reserved |
23-16 | PUSH | R/W | 0h | 8 bit pointer which indicates the number of data values which have been pulled from the buffer by the High Level Controller. This counter will wrap around after 0xff. The Least significant 2 bits are used as the actual pointer for the operation. Reset type: SYSRSn |
15-8 | RESERVED | R-0 | 0h | Reserved |
7-0 | PULL | R/W | 0h | 8 bit pointer which indicates the number of data values that have been written by the High Level controller into the buffer. The Least significant 2 bits are used as the actual pointer for the operation. Reset type: SYSRSn |
CLB_GP_REG is shown in Figure 24-53 and described in Table 24-56.
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General purpose register for CELL inputs
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REG | ||||||||||||||||||||||||||||||
R-0-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7-0 | REG | R/W | 0h | 8 bits which are directly connected to the 8 inputs of the CELL if that corresponding bit is selected in the CLB_IN_MUX_SEL_0 register Reset type: SYSRSn |
CLB_OUT_EN is shown in Figure 24-54 and described in Table 24-57.
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CELL output enable register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUT0 | ||||||||||||||||||||||||||||||
R-0-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-0 | OUT0 | R/W | 0h | 16 bits which are directly driven out as OUTPUT_EN signals. Enabling bit x (x = 0:15) will override the corresponding peripheral signal muxed on the CLB OUTx. Reset type: SYSRSn |
CLB_GLBL_MUX_SEL_1 is shown in Figure 24-55 and described in Table 24-58.
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Global Mux select for CELL inputs
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | GLBL_MUX_SEL_IN_3 | GLBL_MUX_SEL_IN_2 | |||||||||||||
R-0-0h | R/W-0h | R/W-0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GLBL_MUX_SEL_IN_2 | GLBL_MUX_SEL_IN_1 | GLBL_MUX_SEL_IN_0 | |||||||||||||
R/W-0h | R/W-0h | R/W-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R-0 | 0h | Reserved |
27-21 | GLBL_MUX_SEL_IN_3 | R/W | 0h | 7 bit MUX Select for Global MUX control for Input 3 See Global Signals and Mux Selection Table Reset type: SYSRSn |
20-14 | GLBL_MUX_SEL_IN_2 | R/W | 0h | 7 bit MUX Select for Global MUX control for Input 2 See Global Signals and Mux Selection Table Reset type: SYSRSn |
13-7 | GLBL_MUX_SEL_IN_1 | R/W | 0h | 7 bit MUX Select for Global MUX control for Input 1 See Global Signals and Mux Selection Table Reset type: SYSRSn |
6-0 | GLBL_MUX_SEL_IN_0 | R/W | 0h | 7 bit MUX Select for Global MUX control for Input 0 See Global Signals and Mux Selection Table Reset type: SYSRSn |
CLB_GLBL_MUX_SEL_2 is shown in Figure 24-56 and described in Table 24-59.
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Global Mux select for CELL inputs
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | GLBL_MUX_SEL_IN_7 | GLBL_MUX_SEL_IN_6 | |||||||||||||
R-0-0h | R/W-0h | R/W-0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GLBL_MUX_SEL_IN_6 | GLBL_MUX_SEL_IN_5 | GLBL_MUX_SEL_IN_4 | |||||||||||||
R/W-0h | R/W-0h | R/W-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R-0 | 0h | Reserved |
27-21 | GLBL_MUX_SEL_IN_7 | R/W | 0h | 7 bit MUX Select for Global MUX control for Input 7 See Global Signals and Mux Selection Table Reset type: SYSRSn |
20-14 | GLBL_MUX_SEL_IN_6 | R/W | 0h | 7 bit MUX Select for Global MUX control for Input 6 See Global Signals and Mux Selection Table Reset type: SYSRSn |
13-7 | GLBL_MUX_SEL_IN_5 | R/W | 0h | 7 bit MUX Select for Global MUX control for Input 5 See Global Signals and Mux Selection Table Reset type: SYSRSn |
6-0 | GLBL_MUX_SEL_IN_4 | R/W | 0h | 7 bit MUX Select for Global MUX control for Input 4 See Global Signals and Mux Selection Table Reset type: SYSRSn |
CLB_INTR_TAG_REG is shown in Figure 24-57 and described in Table 24-60.
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Interrupt Tag register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TAG | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-6 | RESERVED | R-0 | 0h | Reserved |
5-0 | TAG | R/W | 0h | 6 bits which are used by the High Level Controller to set a tag value on flagging interrupts. This can be cleared through the VBUS interface since it is writeable through the VBUS. Reset type: SYSRSn |
CLB_LOCK is shown in Figure 24-58 and described in Table 24-61.
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Lock control register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
WSonce-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
WSonce-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | WSonce | 0h | These 16 bits act as a key to enable writes to Bit 0 of this register. The only time a '1' can be written to Bit 0 is by a single 32-bit write where bits 31:16 equal 0x5a5a and bit 0 is '1'. All other writes are ignored including separate 16-bit writes. This is EALLOW protected. Reset type: SYSRSn |
15-1 | RESERVED | R-0 | 0h | Reserved |
0 | LOCK | R/W | 0h | This bit is used as a one-time write bit (Set Once). Once it is set to '1', only a reset (SYSRSN 0) will clear this bit back to 0. Reset type: SYSRSn |
CLB_DBG_R0 is shown in Figure 24-59 and described in Table 24-62.
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R0 of High level Controller
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBG | R | 0h | CLB_DBG_R0 Reset type: SYSRSn |
CLB_DBG_R1 is shown in Figure 24-60 and described in Table 24-63.
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R1 of High level Controller
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBG | R | 0h | CLB_DBG_R1 Reset type: SYSRSn |
CLB_DBG_R2 is shown in Figure 24-61 and described in Table 24-64.
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R2 of High level Controller
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBG | R | 0h | CLB_DBG_R2 Reset type: SYSRSn |
CLB_DBG_R3 is shown in Figure 24-62 and described in Table 24-65.
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R3 of High level Controller
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBG | R | 0h | CLB_DBG_R3 Reset type: SYSRSn |
CLB_DBG_C0 is shown in Figure 24-63 and described in Table 24-66.
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Count of Unit 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBG | R | 0h | CLB_DBG_C0 Reset type: SYSRSn |
CLB_DBG_C1 is shown in Figure 24-64 and described in Table 24-67.
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Count of Unit 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBG | R | 0h | CLB_DBG_C1 Reset type: SYSRSn |
CLB_DBG_C2 is shown in Figure 24-65 and described in Table 24-68.
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Count of Unit 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBG | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBG | R | 0h | CLB_DBG_C2 Reset type: SYSRSn |
CLB_DBG_OUT is shown in Figure 24-66 and described in Table 24-69.
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Outputs of various units in the Cell
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
OUT7 | OUT6 | OUT5 | OUT4 | OUT3 | OUT2 | OUT1 | OUT0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
LUT42_OUT | FSM2_LUTOUT | FSM2_S1 | FSM2_S0 | COUNT2_MATCH1 | COUNT2_ZERO | COUNT2_MATCH2 | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-1-1h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LUT41_OUT | FSM1_LUTOUT | FSM1_S1 | FSM1_S0 | COUNT1_MATCH1 | COUNT1_ZERO | COUNT1_MATCH2 | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-1-1h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LUT40_OUT | FSM0_LUTOUT | FSM0_S1 | FSM0_S0 | COUNT0_MATCH1 | COUNT0_ZERO | COUNT0_MATCH2 | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | OUT7 | R | 0h | CELL Output 7 Reset type: SYSRSn |
30 | OUT6 | R | 0h | CELL Output 6 Reset type: SYSRSn |
29 | OUT5 | R | 0h | CELL Output 5 Reset type: SYSRSn |
28 | OUT4 | R | 0h | CELL Output 4 Reset type: SYSRSn |
27 | OUT3 | R | 0h | CELL Output 3 Reset type: SYSRSn |
26 | OUT2 | R | 0h | CELL Output 2 Reset type: SYSRSn |
25 | OUT1 | R | 0h | CELL Output 1 Reset type: SYSRSn |
24 | OUT0 | R | 0h | CELL Output 0 Reset type: SYSRSn |
23 | LUT42_OUT | R | 0h | LUT4_OUT UNIT 2 Reset type: SYSRSn |
22 | FSM2_LUTOUT | R | 0h | FSM_LUT_OUT UNIT 2 Reset type: SYSRSn |
21 | FSM2_S1 | R | 0h | FSM_S1 UNIT 2 Reset type: SYSRSn |
20 | FSM2_S0 | R | 0h | FSM_S0 UNIT 2 Reset type: SYSRSn |
19 | COUNT2_MATCH1 | R | 0h | COUNT_MATCH1 UNIT 2 Reset type: SYSRSn |
18 | COUNT2_ZERO | R | 0h | COUNT_ZERO UNIT 2 Reset type: SYSRSn |
17 | COUNT2_MATCH2 | R | 0h | COUNT_MATCH2 UNIT 2 Reset type: SYSRSn |
16 | RESERVED | R-1 | 1h | Reserved |
15 | LUT41_OUT | R | 0h | LUT4_OUT UNIT 1 Reset type: SYSRSn |
14 | FSM1_LUTOUT | R | 0h | FSM_LUT_OUT UNIT 1 Reset type: SYSRSn |
13 | FSM1_S1 | R | 0h | FSM_S1 UNIT 1 Reset type: SYSRSn |
12 | FSM1_S0 | R | 0h | FSM_S0 UNIT 1 Reset type: SYSRSn |
11 | COUNT1_MATCH1 | R | 0h | COUNT_MATCH1 UNIT 1 Reset type: SYSRSn |
10 | COUNT1_ZERO | R | 0h | COUNT_ZERO UNIT 1 Reset type: SYSRSn |
9 | COUNT1_MATCH2 | R | 0h | COUNT_MATCH2 UNIT 1 Reset type: SYSRSn |
8 | RESERVED | R-1 | 1h | Reserved |
7 | LUT40_OUT | R | 0h | LUT4_OUT UNIT 0 Reset type: SYSRSn |
6 | FSM0_LUTOUT | R | 0h | FSM_LUT_OUT UNIT 0 Reset type: SYSRSn |
5 | FSM0_S1 | R | 0h | FSM_S1 UNIT 0 Reset type: SYSRSn |
4 | FSM0_S0 | R | 0h | FSM_S0 UNIT 0 Reset type: SYSRSn |
3 | COUNT0_MATCH1 | R | 0h | COUNT_MATCH1 UNIT 0 Reset type: SYSRSn |
2 | COUNT0_ZERO | R | 0h | COUNT_ZERO UNIT 0 Reset type: SYSRSn |
1 | COUNT0_MATCH2 | R | 0h | COUNT_MATCH2 UNIT 0 Reset type: SYSRSn |
0 | RESERVED | R-0 | 0h | Reserved |