SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
Table 3-56 lists the memory-mapped registers for the WD_REGS registers. All register offset addresses not listed in Table 3-56 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
22h | SCSR | System Control & Status Register | EALLOW | Go |
23h | WDCNTR | Watchdog Counter Register | EALLOW | Go |
25h | WDKEY | Watchdog Reset Key Register | EALLOW | Go |
29h | WDCR | Watchdog Control Register Note: IORSn reset type is asserted when XRSn or CPU1.SYSRSn or CPU1.WDRSn or CPU1.NMIRSn is asserted. | EALLOW | Go |
2Ah | WDWCR | Watchdog Windowed Control Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-57 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
SCSR is shown in Figure 3-55 and described in Table 3-58.
Return to the Summary Table.
It is recommended to only use 16 bit accesses to write to this register. Use a read-modify-write instruction may inadvertently clear other bits.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDINTS | WDENINT | WDOVERRIDE | ||||
R-0-0h | R-1h | R/W-0h | R/W1C-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-3 | RESERVED | R-0 | 0h | Reserved |
2 | WDINTS | R | 1h | Watchdog interrupt (WDINTn) status signal. This is a read only bit reflecting the current state of the WDINTn signal from the watchdog block (after synchronization with SYSCLKOUT). If this bit is 1, the watchdog interrupt is not active. If this bit is 0, then the watchdog interrupt is active. Note: ,If the WDINTn signal is used to wake up from IDLE or STANDBY condition, then the user should make sure that the WDINTn signal goes back high again before attempting to go back into IDLE or STANDBY mode. Reading this bit will tell the user the current state of this signal. Reset type: SYSRSn |
1 | WDENINT | R/W | 0h | If this bit is set to 1, the watchdog reset (WDRSTn) output signal is disabled and the watchdog interrupt (WDINTn) output signal is enabled. If this bit is zero, then the WDRSTn output signal is enabled and the WDINTn output signal is disabled. This is the default state on system reset (SYSRSn). Reset type: SYSRSn |
0 | WDOVERRIDE | R/W1C | 1h | If this bit is set to 1, the user is allowed to change the state of the Watchdog disable (WDDIS) bit in the Watchdog Control (WDCR) register. If the WDOVERRIDE bit is cleared, by writing a 1 the WDDIS bit cannot be modified by the user. Writing a 0 will have no effect. If this bit is cleared, then it will remain in this state until a reset occurs. The current state of this bit is readable by the user. Reset type: SYSRSn |
WDCNTR is shown in Figure 3-56 and described in Table 3-59.
Return to the Summary Table.
Watchdog Counter Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDCNTR | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R-0 | 0h | Reserved |
7-0 | WDCNTR | R | 0h | These bits contain the current value of the WD counter. The 8-bit counter continually increments at the WDCLK rate. If the counter overflows, then a watchdog output pulse (WDOUTn) is generated. If the WDKEY register is written with a valid combination, then the counter is reset to zero. Reset type: IORSn |
WDKEY is shown in Figure 3-57 and described in Table 3-60.
Return to the Summary Table.
Watchdog Reset Key Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDKEY | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R-0 | 0h | Reserved |
7-0 | WDKEY | R/W | 0h | Writing 0x55 followed by 0xAA will cause the WDCNTR bits to be cleared. Note: [1] Reads from the WDKEY return the value of WDCR register. Reset type: IORSn |
WDCR is shown in Figure 3-58 and described in Table 3-61.
Return to the Summary Table.
Watchdog Control Register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDDIS | WDCHK | WDPS | ||||
R/W1S-0h | R/W-0h | R-0/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W1S | 0h | Reserved |
6 | WDDIS | R/W | 0h | Writing a 1 to this bit will disable the watchdog module. Writing a 0 will enable the module. This bit can only be modified if the WDOVERRIDE bit in the SCSR2 register is set to 1. On reset, the watchdog module is enabled. Reset type: IORSn |
5-3 | WDCHK | R-0/W | 0h | The user must ALWAYS write 1,0,1 to these bits whenever a write to this register is performed. Writing any other value will cause an immediate reset to the core (if WD enabled). Reset type: IORSn |
2-0 | WDPS | R/W | 0h | These bits configure the watchdog counter clock (WDCLK) rate relative to INTOSC1/512: 000 WDCLK = INTOSC1/512/1 001 WDCLK = INTOSC1/512/1 010 WDCLK = INTOSC1/512/2 011 WDCLK = INTOSC1/512/4 100 WDCLK = INTOSC1/512/8 101 WDCLK = INTOSC1/512/16 110 WDCLK = INTOSC1/512/32 111 WDCLK = INTOSC1/512/64 Reset type: IORSn |
WDWCR is shown in Figure 3-59 and described in Table 3-62.
Return to the Summary Table.
Watchdog Windowed Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FIRSTKEY | ||||||
R-0-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MIN | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R-0 | 0h | Reserved |
8 | FIRSTKEY | R | 0h | This bit indicates if the 1st valid WDKEY (0x55 + 0xAA) got detected after MIN was configured to a non-zero value 0: First Valid Key after non-zero MIN configuration has not happened yet 1: First Valid key after non-zero MIN configuration got detected Notes: [1] If MIN = 0, this bit is never set [2] If MIN is changed back to 0x0 from a non-zero value, this bit is auto-cleared [3] This bit is added for debug purposes only Reset type: IORSn |
7-0 | MIN | R/W | 0h | Watchdog Window Threshold These bits specify the lower limit of the watchdog counter reset window. If the counter reset via the WDKEY register before the counter value reaches the value in this register, the watchdog immediately triggers a reset or interrupt. Reset type: IORSn |