SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
Table 23-34 lists the memory-mapped registers for the EMIF_REGS registers. All register offset addresses not listed in Table 23-34 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | RCSR | Revision Code and Status Register | Go | |
2h | ASYNC_WCCR | Async Wait Cycle Config Register | Go | |
4h | SDRAM_CR | SDRAM (EMxCS0n) Config Register | Go | |
6h | SDRAM_RCR | SDRAM Refresh Control Register | Go | |
8h | ASYNC_CS2_CR | Async 1 (EMxCS2n) Config Register | Go | |
Ah | ASYNC_CS3_CR | Async 2 (EMxCS3n) Config Register | Go | |
Ch | ASYNC_CS4_CR | Async 3 (EMxCS4n) Config Register | Go | |
10h | SDRAM_TR | SDRAM Timing Register | Go | |
18h | TOTAL_SDRAM_AR | Total SDRAM Accesses Register | Go | |
1Ah | TOTAL_SDRAM_ACTR | Total SDRAM Activate Register | Go | |
1Eh | SDR_EXT_TMNG | SDRAM SR/PD Exit Timing Register | Go | |
20h | INT_RAW | Interrupt Raw Register | Go | |
22h | INT_MSK | Interrupt Masked Register | Go | |
24h | INT_MSK_SET | Interrupt Mask Set Register | Go | |
26h | INT_MSK_CLR | Interrupt Mask Clear Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 23-35 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
RCSR is shown in Figure 23-23 and described in Table 23-36.
Return to the Summary Table.
Revision Code and Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BE | FR | MODULE_ID | |||||||||||||
R-0h | R-1h | R-0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAJOR_REVISION | MINOR_REVISION | ||||||||||||||
R-2h | R-5h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | BE | R | 0h | EMIF endian mode. 0: Little Endian. 1: Big Endian. Reset type: SYSRSn |
30 | FR | R | 1h | EMIF operating rate. 0: Half Rate. 1: Full Rate. Reset type: SYSRSn |
29-16 | MODULE_ID | R | 0h | EMIF module ID. 0x0000: EMIF_24. 0x000E: EMIF_24 SDRAM. 0x000F: EMIF_24 ASYNC. Reset type: SYSRSn |
15-8 | MAJOR_REVISION | R | 2h | Major Revision. EMIF code revisions are indicated by a revision code taking the format major_revision.minor_revision. Reset type: SYSRSn |
7-0 | MINOR_REVISION | R | 5h | Minor Revision. See major_revision field description. Reset type: SYSRSn |
ASYNC_WCCR is shown in Figure 23-24 and described in Table 23-37.
Return to the Summary Table.
Async Wait Cycle Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | WP0 | RESERVED | |||
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAX_EXT_WAIT | |||||||
R/W-80h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 1h | Reserved |
30 | RESERVED | R/W | 1h | Reserved |
29 | RESERVED | R/W | 1h | Reserved |
28 | WP0 | R/W | 1h | Defines the polarity of the EMxWAIT port.: 0: Wait if EMxWAIT port is low. 1: Wait if EMxWAIT port is high. Reset type: SYSRSn |
27-24 | RESERVED | R | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | MAX_EXT_WAIT | R/W | 80h | The EMIF will wait for (max_ext_wait + 1) * 16 clock cycles before an extended asynchronous cycle is terminated. Reset type: SYSRSn |
SDRAM_CR is shown in Figure 23-25 and described in Table 23-38.
Return to the Summary Table.
SDRAM (EMxCS0n) Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SR | PD | PDWR | RESERVED | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | NM | RESERVED | RESERVED | CL | BIT_11_9_LOCK | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-3h | R-0/W1S-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IBANK | RESERVED | PAGESIGE | ||||
R-0h | R/W-2h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SR | R/W | 0h | Self Refresh. Writing a 1 to this bit will cause connected SDRAM devices to be placed into Self Refresh mode and the EMIF to enter the self refresh state. In this state the EMIF will service all asynchronous memory accesses immediately but any SDRAM access will take at least t_ras + 1 cycles due to the time required for the SDRAM devices to out of Self Refresh mode. If an SDRAM access immediately follows the setting of the sr bit, the access will take t_ras + t_xs + 2 cycles. If both sr and pd bits are set, the EMIF will go into Self Refresh. Reset type: SYSRSn |
30 | PD | R/W | 0h | Power Down. Writing a 1 to this bit will cause connected SDRAM devices to be placed into Power Down mode. If both sr and pd bits are set, the EMIF will go into Self Refresh. Reset type: SYSRSn |
29 | PDWR | R/W | 0h | Perform refreshes during Power Down. Writing a 1 to this bit will cause the EMIF to exit the power down state and issue an AUTO REFRESH command every time Refresh May level is set. Reset type: SYSRSn |
28-26 | RESERVED | R | 0h | Reserved |
25-23 | RESERVED | R/W | 0h | Reserved |
22-20 | RESERVED | R/W | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18-17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R | 0h | Reserved |
14 | NM | R/W | 0h | Narrow mode. Set to 1 when system bus width to memory bus width is 2:1 for SDR SDRAM. Set to 0 when system bus width to memory bus width is 1:1 for SDR SDRAM. A write to this field will cause the EMIF to start the SDRAM initialization sequence. Reset type: SYSRSn |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11-9 | CL | R/W | 3h | The value of this field defines the CAS latency to be used when accessing connected SDRAM devices. Only CAS latencies of 2 (cl = 2) and 3 (cl = 3) are supported. A write to this field will cause the EMIF to start the SDRAM initialization sequence. Reset type: SYSRSn |
8 | BIT_11_9_LOCK | R-0/W1S | 0h | Bits 11 to 9 can only be written if this bit is set to 1. Reset type: SYSRSn |
7 | RESERVED | R | 0h | Reserved |
6-4 | IBANK | R/W | 2h | Defines number of banks inside connected SDRAM devices: 000: 1 bank SDRAM devices. 001: 2 bank SDRAM devices. 010: 4 bank SDRAM devices. 011: Reserved. 1xx: Reserved. A write to this field will cause the EMIF to start the SDRAM initialization sequence. Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2-0 | PAGESIGE | R/W | 0h | Defines the internal page size of connected SDRAM devices: 000: 256-word pages requiring 8 column address bits. 001: 512-word pages requiring 9 column address bits. 010: 1024-word pages requiring 10 column address bits. 011: 2048-word pages requiring 11 column address bits. 1xx: Reserved. A write to this field will cause the EMIF to start the SDRAM initialization sequence. Reset type: SYSRSn |
SDRAM_RCR is shown in Figure 23-26 and described in Table 23-39.
Return to the Summary Table.
SDRAM Refresh Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | REFRESH_RATE | ||||||
R-0h | R/W-80h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REFRESH_RATE | |||||||
R/W-80h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | RESERVED | R/W | 0h | Reserved |
15-13 | RESERVED | R | 0h | Reserved |
12-0 | REFRESH_RATE | R/W | 80h | Value in this field is used to define the rate at which connected SDRAM devices will be refreshed, as follows: SDRAM refresh rate = EMIF rate/refresh_rate where EMIF rate=clk rate when full_rate=1, or EMIF rate=1/2 clk rate when full_rate=0. Writing a value < 0x0020 to this field will cause it to be loaded with (2 * t_rfc) + 1 value from SDRAM Timing register. Reset type: SYSRSn |
ASYNC_CS2_CR is shown in Figure 23-27 and described in Table 23-40.
Return to the Summary Table.
Async 1 (EMxCS2n) Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SS | EW | W_SETUP | W_STROBE | W_HOLD | R_SETUP | ||||||||||
R/W-0h | R/W-0h | R/W-Fh | R/W-3Fh | R/W-7h | R/W-Fh | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R_SETUP | R_STROBE | R_HOLD | TA | ASIZE | |||||||||||
R/W-Fh | R/W-3Fh | R/W-7h | R/W-3h | R/W-1h | |||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SS | R/W | 0h | Select Strobe mode. Set to 1 if chip selects need to have write or read strobe timing. Reset type: SYSRSn |
30 | EW | R/W | 0h | Extend Wait mode. Set to 1 if extended asynchronous cycles are required based on EMxWAIT. Reset type: SYSRSn |
29-26 | W_SETUP | R/W | Fh | Write Strobe Setup cycles. Number of EMxCLK cycles from EMxAy, EMxBAy, EMxDQMy, and EMxCS2n being set to EMxWEn asserted, minus one cycle. The reset value is 16 cycles. Reset type: SYSRSn |
25-20 | W_STROBE | R/W | 3Fh | Write Strobe Duration cycles. Number of EMxCLK cycles for which EMxWEn is held active, minus one cycle. The reset value is 64 cycles. This field cannot be zero when ew = 1. Reset type: SYSRSn |
19-17 | W_HOLD | R/W | 7h | Write Strobe Hold cycles. Number of EMxCLK cycles for which EMxAy, EMxBAy, EMxDQMy, and EMxCS2n are held after EMxWEn has been deasserted, minus one cycle. The reset value is 8 cycles. Reset type: SYSRSn |
16-13 | R_SETUP | R/W | Fh | Read Strobe Setup cycles. Number of EMxCLK cycles from EMxAy, EMxBAy, EMxDQMy, and EMxCS2n being set to EMxOEn asserted, minus one cycle. The reset value is 16 cycles. Reset type: SYSRSn |
12-7 | R_STROBE | R/W | 3Fh | Read Strobe Duration cycles. Number of EMxCLK cycles for which EMxOEn is held active, minus one cycle. The reset value is 64 cycles. This field cannot be zero when ew = 1. Reset type: SYSRSn |
6-4 | R_HOLD | R/W | 7h | Read Strobe Hold cycles. Number of EMxCLK cycles for which EMxAy, EMxBAy, EMxDQMy, and EMxCS2n are held after EMxOEn has been deasserted, minus one cycle. The reset value is 8 cycles. Reset type: SYSRSn |
3-2 | TA | R/W | 3h | Turn Around cycles. Number of EMxCLK cycles between the end of one asynchronous memory access and the start of another asynchronous memory access, minus one cycle. This delay is not incurred between a read followed by a read, or a write followed by a write to the same chip select. The reset value is 4 cycles. Reset type: SYSRSn |
1-0 | ASIZE | R/W | 1h | Asynchronous Memory Size. Defines the width of the asynchronous device's data bus : 00: 8 Bit data bus. 01: 16 Bit data bus. 10: 32 Bit data bus. 11: Reserved. Reset type: SYSRSn |
ASYNC_CS3_CR is shown in Figure 23-28 and described in Table 23-41.
Return to the Summary Table.
Async 2 (EMxCS3n) Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SS | EW | W_SETUP | W_STROBE | W_HOLD | R_SETUP | ||||||||||
R/W-0h | R/W-0h | R/W-Fh | R/W-3Fh | R/W-7h | R/W-Fh | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R_SETUP | R_STROBE | R_HOLD | TA | ASIZE | |||||||||||
R/W-Fh | R/W-3Fh | R/W-7h | R/W-3h | R/W-1h | |||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SS | R/W | 0h | Select Strobe mode. Set to 1 if chip selects need to have write or read strobe timing. Reset type: SYSRSn |
30 | EW | R/W | 0h | Extend Wait mode. Set to 1 if extended asynchronous cycles are required based on EMxWAIT. Reset type: SYSRSn |
29-26 | W_SETUP | R/W | Fh | Write Strobe Setup cycles. Number of EMxCLK cycles from EMxAy, EMxBAy, EMxDQMy, and EMxCS3n being set to EMxWEn asserted, minus one cycle. The reset value is 16 cycles. Reset type: SYSRSn |
25-20 | W_STROBE | R/W | 3Fh | Write Strobe Duration cycles. Number of EMxCLK cycles for which EMxWEn is held active, minus one cycle. The reset value is 64 cycles. This field cannot be zero when ew = 1. Reset type: SYSRSn |
19-17 | W_HOLD | R/W | 7h | Write Strobe Hold cycles. Number of EMxCLK cycles for which EMxAy, EMxBAy, EMxDQMy, and EMxCS3n are held after EMxWEn has been deasserted, minus one cycle. The reset value is 8 cycles. Reset type: SYSRSn |
16-13 | R_SETUP | R/W | Fh | Read Strobe Setup cycles. Number of EMxCLK cycles from EMxAy, EMxBAy, EMxDQMy, and EMxCS3n being set to EMxOEn asserted, minus one cycle. The reset value is 16 cycles. Reset type: SYSRSn |
12-7 | R_STROBE | R/W | 3Fh | Read Strobe Duration cycles. Number of EMxCLK cycles for which EMxOEn is held active, minus one cycle. The reset value is 64 cycles. This field cannot be zero when ew = 1. Reset type: SYSRSn |
6-4 | R_HOLD | R/W | 7h | Read Strobe Hold cycles. Number of EMxCLK cycles for which EMxAy, EMxBAy, EMxDQMy, and EMxCS3n are held after EMxOEn has been deasserted, minus one cycle. The reset value is 8 cycles. Reset type: SYSRSn |
3-2 | TA | R/W | 3h | Turn Around cycles. Number of EMxCLK cycles between the end of one asynchronous memory access and the start of another asynchronous memory access, minus one cycle. This delay is not incurred between a read followed by a read, or a write followed by a write to the same chip select. The reset value is 4 cycles. Reset type: SYSRSn |
1-0 | ASIZE | R/W | 1h | Asynchronous Memory Size. Defines the width of the asynchronous device's data bus : 00: 8 Bit data bus. 01: 16 Bit data bus. 10: 32 Bit data bus. 11: Reserved. Reset type: SYSRSn |
ASYNC_CS4_CR is shown in Figure 23-29 and described in Table 23-42.
Return to the Summary Table.
Async 3 (EMxCS4n) Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SS | EW | W_SETUP | W_STROBE | W_HOLD | R_SETUP | ||||||||||
R/W-0h | R/W-0h | R/W-Fh | R/W-3Fh | R/W-7h | R/W-Fh | ||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
R_SETUP | R_STROBE | R_HOLD | TA | ASIZE | |||||||||||
R/W-Fh | R/W-3Fh | R/W-7h | R/W-3h | R/W-1h | |||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SS | R/W | 0h | Select Strobe mode. Set to 1 if chip selects need to have write or read strobe timing. Reset type: SYSRSn |
30 | EW | R/W | 0h | Extend Wait mode. Set to 1 if extended asynchronous cycles are required based on EMxWAIT. Reset type: SYSRSn |
29-26 | W_SETUP | R/W | Fh | Write Strobe Setup cycles. Number of EMxCLK cycles from EMxAy, EMxBAy, EMxDQMy, and EMxCS4n being set to EMxWEn asserted, minus one cycle. The reset value is 16 cycles. Reset type: SYSRSn |
25-20 | W_STROBE | R/W | 3Fh | Write Strobe Duration cycles. Number of EMxCLK cycles for which EMxWEn is held active, minus one cycle. The reset value is 64 cycles. This field cannot be zero when ew = 1. Reset type: SYSRSn |
19-17 | W_HOLD | R/W | 7h | Write Strobe Hold cycles. Number of EMxCLK cycles for which EMxAy, EMxBAy, EMxDQMy, and EMxCS4n are held after EMxWEn has been deasserted, minus one cycle. The reset value is 8 cycles. Reset type: SYSRSn |
16-13 | R_SETUP | R/W | Fh | Read Strobe Setup cycles. Number of EMxCLK cycles from EMxAy, EMxBAy, EMxDQMy, and EMxCS4n being set to EMxOEn asserted, minus one cycle. The reset value is 16 cycles. Reset type: SYSRSn |
12-7 | R_STROBE | R/W | 3Fh | Read Strobe Duration cycles. Number of EMxCLK cycles for which EMxOEn is held active, minus one cycle. The reset value is 64 cycles. This field cannot be zero when ew = 1. Reset type: SYSRSn |
6-4 | R_HOLD | R/W | 7h | Read Strobe Hold cycles. Number of EMxCLK cycles for which EMxAy, EMxBAy, EMxDQMy, and EMxCS4n are held after EMxOEn has been deasserted, minus one cycle. The reset value is 8 cycles. Reset type: SYSRSn |
3-2 | TA | R/W | 3h | Turn Around cycles. Number of EMxCLK cycles between the end of one asynchronous memory access and the start of another asynchronous memory access, minus one cycle. This delay is not incurred between a read followed by a read, or a write followed by a write to the same chip select. The reset value is 4 cycles. Reset type: SYSRSn |
1-0 | ASIZE | R/W | 1h | Asynchronous Memory Size. Defines the width of the asynchronous device's data bus : 00: 8 Bit data bus. 01: 16 Bit data bus. 10: 32 Bit data bus. 11: Reserved. Reset type: SYSRSn |
SDRAM_TR is shown in Figure 23-30 and described in Table 23-43.
Return to the Summary Table.
SDRAM Timing Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
T_RFC | T_RP | ||||||
R/W-3h | R/W-1h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | T_RCD | RESERVED | T_WR | ||||
R-0h | R/W-2h | R-0h | R/W-1h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
T_RAS | T_RC | ||||||
R/W-4h | R/W-6h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | T_RRD | RESERVED | |||||
R-0h | R/W-1h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | T_RFC | R/W | 3h | Minimum number of EMxCLK cycles from Refresh or Load Mode to Refresh or Activate, minus one. Reset type: SYSRSn |
26-24 | T_RP | R/W | 1h | Minimum number of EMxCLK cycles from Precharge to Activate or Refresh, minus one. Reset type: SYSRSn |
23 | RESERVED | R | 0h | Reserved |
22-20 | T_RCD | R/W | 2h | Minimum number of EMxCLK cycles from Activate to Read or Write, minus one. Reset type: SYSRSn |
19 | RESERVED | R | 0h | Reserved |
18-16 | T_WR | R/W | 1h | For SDR, this is equal to minimum number of EMxCLK cycles from last Write transfer to Precharge, minus one. Reset type: SYSRSn |
15-12 | T_RAS | R/W | 4h | Minimum number of EMxCLK cycles from Activate to Precharge, minus one. t_ras >= t_rcd. Reset type: SYSRSn |
11-8 | T_RC | R/W | 6h | Minimum number of EMxCLK cycles from Activate to Activate minus one. Reset type: SYSRSn |
7 | RESERVED | R | 0h | Reserved |
6-4 | T_RRD | R/W | 1h | Minimum number of EMxCLK cycles from Activate to Activate for a different bank, minus one. Reset type: SYSRSn |
3-0 | RESERVED | R | 0h | Reserved |
TOTAL_SDRAM_AR is shown in Figure 23-31 and described in Table 23-44.
Return to the Summary Table.
Total SDRAM Accesses Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOTAL_SDRAM_AR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TOTAL_SDRAM_AR | R | 0h | Indicates the total number of accesses to SDRAM from a master (CPUx/CPUX.DMA). This counter is incremented by two for a single access crossing page boundaries. Reset type: SYSRSn |
TOTAL_SDRAM_ACTR is shown in Figure 23-32 and described in Table 23-45.
Return to the Summary Table.
Total SDRAM Activate Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TOTAL_SDRAM_ACTR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TOTAL_SDRAM_ACTR | R | 0h | Indicates the total number of SDRAM accesses which require an activate command. Reset type: SYSRSn |
SDR_EXT_TMNG is shown in Figure 23-33 and described in Table 23-46.
Return to the Summary Table.
SDRAM SR/PD Exit Timing Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | T_XS | |||||||||||||||||||||||||||||
R-0h | R-0h | R/W-7h | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-5 | RESERVED | R | 0h | Reserved |
4-0 | T_XS | R/W | 7h | This is equal to minimum number of EMxCLK cycles from Self Refresh exit to any command, minus one. For SDR SDRAM, this count should satisfy tXSR. Reset type: SYSRSn |
INT_RAW is shown in Figure 23-34 and described in Table 23-47.
Return to the Summary Table.
Interrupt Raw Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WR | LT | AT | ||||||||||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-6 | RESERVED | R | 0h | Reserved |
5-2 | WR | R/W1S | 0h | Wait Rise. Set to 1 by hardware to indicate rising edge on the corresponding EMxWAIT has been detected. The WPx bits in the Async Wait Cycle Config register has no effect on these bits. Writing a 1 will clear these bits as well as the wr_masked bits in the Interrupt Masked register. Writing a 0 has no effect. Reset type: SYSRSn |
1 | LT | R/W1S | 0h | Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. Writing a 1 will clear this bit as well as the lt_masked bit in the Interrupt Masked register. Writing a 0 has no effect. Reset type: SYSRSn |
0 | AT | R/W1S | 0h | Asynchronous Timeout. Set to 1 by hardware to indicate that during an extended asynchronous memory access cycle, the EMxWAIT signal did not go inactive within the number of cycles defined by the max_ext_wait field in Async Wait Cycle Config register. Writing a 1 will clear this bit as well as the at_masked bit in the Interrupt Masked register. Writing a 0 has no effect. Reset type: SYSRSn |
INT_MSK is shown in Figure 23-35 and described in Table 23-48.
Return to the Summary Table.
Interrupt Masked Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WR_MASKED | LT_MASKED | AT_MASKED | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-6 | RESERVED | R | 0h | Reserved |
5-2 | WR_MASKED | R/W1S | 0h | Masked Wait Rise. Set to 1 by hardware to indicate rising edge on the corresponding EMxWAIT has been detected, only if the wr_mask_set bit in the Interrupt Mask Set register is set to 1. The WPx bits in the Async Wait Cycle Config register has no effect on these bits. Writing a 1 will clear these bits as well as the wr bits in the Interrupt Raw register. Writing a 0 has no effect. Reset type: SYSRSn |
1 | LT_MASKED | R/W1S | 0h | Masked Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size, only if the lt_mask_set bit in the Interrupt Mask Set register is set to 1. Writing a 1 will clear this bit as well as the lt bit in the Interrupt Raw register. Writing a 0 has no effect. Reset type: SYSRSn |
0 | AT_MASKED | R/W1S | 0h | Masked Asynchronous Timeout. Set to 1 by hardware to indicate that during an extended asynchronous memory access cycle, the EMxWAIT signal did not go inactive within the number of cycles defined by the max_ext_wait field in Async Wait Cycle Config register, only if the at_mask_set bit in the Interrupt Mask Set register is set to 1. Writing a 1 will clear this bit as well as the at bit in the Interrupt Raw register. Writing a 0 has no effect. Reset type: SYSRSn |
INT_MSK_SET is shown in Figure 23-36 and described in Table 23-49.
Return to the Summary Table.
Interrupt Mask Set Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WR_MASK_SET | LT_MASK_SET | AT_MASK_SET | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-6 | RESERVED | R | 0h | Reserved |
5-2 | WR_MASK_SET | R/W1S | 0h | Mask set for wr_masked bits in the Interrupt Masked Register. Writing a 1 will enable the interrupts, and set these bits as well as the wr_mask_clr bits in the Interrupt Mask Clear register. Writing a 0 has no effect. Reset type: SYSRSn |
1 | LT_MASK_SET | R/W1S | 0h | Mask set for lt_masked bit in the Interrupt Masked Register. Writing a 1 will enable the interrupt, and set this bit as well as the lt_mask_clr bit in the Interrupt Mask Clear register. Writing a 0 has no effect. Reset type: SYSRSn |
0 | AT_MASK_SET | R/W1S | 0h | Mask set for at_masked bit in the Interrupt Masked Register. Writing a 1 will enable the interrupt, and set this bit as well as the at_mask_clr bit in the Interrupt Mask Clear register. Writing a 0 has no effect. Reset type: SYSRSn |
INT_MSK_CLR is shown in Figure 23-37 and described in Table 23-50.
Return to the Summary Table.
Interrupt Mask Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WR_MASK_CLR | LT_MASK_CLR | AT_MASK_CLR | ||||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-6 | RESERVED | R | 0h | Reserved |
5-2 | WR_MASK_CLR | R/W1S | 0h | Mask clear for wr_masked bits in the Interrupt Masked Register. Writing a 1 will disable the interrupts, and clear these bits as well as the wr_mask_set bits in the Interrupt Mask Set register. Writing a 0 has no effect. Reset type: SYSRSn |
1 | LT_MASK_CLR | R/W1S | 0h | Mask clear for lt_masked bit in the Interrupt Masked Register. Writing a 1 will disable the interrupt, and clear this bit as well as the lt_mask_set bit in the Interrupt Mask Set register. Writing a 0 has no effect. Reset type: SYSRSn |
0 | AT_MASK_CLR | R/W1S | 0h | Mask clear for at_masked bit in the Interrupt Masked Register. Writing a 1 will disable the interrupt, and clear this bit as well as the at_mask_set bit in the Interrupt Mask Set register. Writing a 0 has no effect. Reset type: SYSRSn |