SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
The USB FIFO endpoint n 32-bit registers (USBFIFO[n]) provide an address for CPU access to the FIFOs for each endpoint. Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint. Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint.
Transfers to and from FIFOs can be 8-bit, 16-bit or 32-bit as required, and any combination of accesses is allowed provided the data accessed is contiguous. All transfers associated with one packet must be of the same width so that the data is consistently byte-, halfword- or word-aligned. However, the last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support either single-packet or double-packet buffering (see Single-Packet Buffering in Section 22.2.1.1.2). Burst writing of multiple packets is not supported as flags must be set after each packet is written.
Following a STALL response or a transmit error on endpoint 1–3, the associated FIFO is completely flushed.
Mode(s): | Host | Device |
USBFIFO0-3 are shown in Figure 22-18 and described in Table 22-20.
31 | 0 |
EPDATA |
R/W-0 |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Reset | Description |
---|---|---|---|
31-0 | EPDATA | 0x0000.0000 | Endpoint Data. Writing to this register loads the data into the Transmit FIFO and reading unloads data from the Receive FIFO. |