SPRUHM9H
October 2014 – May 2024
TMS320F28075
,
TMS320F28075-Q1
,
TMS320F28076
1
Read This First
About This Manual
Notational Conventions
Glossary
Related Documentation From Texas Instruments
Support Resources
Trademarks
1
C2000™ Microcontrollers Software Support
1.1
Introduction
1.2
C2000Ware Structure
1.3
Documentation
1.4
Devices
1.5
Libraries
1.6
Code Composer Studio™ Integrated Development Environment (IDE)
1.7
SysConfig and PinMUX Tool
2
C28x Processor
2.1
Introduction
2.2
C28X Related Collateral
2.3
Features
2.4
Floating-Point Unit
2.5
Trigonometric Math Unit (TMU)
3
System Control and Interrupt
3.1
Introduction
3.2
System Control Functional Description
3.2.1
Device Identification
3.2.2
Device Configuration Registers
3.3
Resets
3.3.1
Reset Sources
3.3.2
External Reset (XRS)
3.3.3
Power-On Reset (POR)
3.3.4
Debugger Reset (SYSRS)
3.3.5
Watchdog Reset (WDRS)
3.3.6
NMI Watchdog Reset (NMIWDRS)
3.3.7
DCSM Safe Code Copy Reset (SCCRESET)
3.3.8
Hibernate Reset (HIBRESET)
3.3.9
Hardware BIST Reset (HWBISTRS)
3.3.10
Test Reset (TRST)
3.4
Peripheral Interrupts
3.4.1
Interrupt Concepts
3.4.2
Interrupt Architecture
3.4.2.1
Peripheral Stage
3.4.2.2
PIE Stage
3.4.2.3
CPU Stage
3.4.3
Interrupt Entry Sequence
3.4.4
Configuring and Using Interrupts
3.4.4.1
Enabling Interrupts
3.4.4.2
Handling Interrupts
3.4.4.3
Disabling Interrupts
3.4.4.4
Nesting Interrupts
3.4.5
PIE Channel Mapping
3.4.5.1
PIE Interrupt Priority
3.4.5.1.1
Channel Priority
3.4.5.1.2
Group Priority
3.4.6
Vector Tables
3.5
Exceptions and Non-Maskable Interrupts
3.5.1
Configuring and Using NMIs
3.5.2
Emulation Considerations
3.5.3
NMI Sources
3.5.3.1
Missing Clock Detection
3.5.3.2
RAM Uncorrectable ECC Error
3.5.3.3
Flash Uncorrectable ECC Error
3.5.4
Illegal Instruction Trap (ITRAP)
3.6
Safety Features
3.6.1
Write Protection on Registers
3.6.1.1
LOCK Protection on System Configuration Registers
3.6.1.2
EALLOW Protection
3.6.2
Missing Clock Detection Logic
3.6.3
PLLSLIP Detection
3.6.4
CPU Vector Address Validity Check
3.6.5
NMIWDs
3.6.6
ECC and Parity Enabled RAMs, Shared RAMs Protection
3.6.7
ECC Enabled Flash Memory
3.6.8
ERRORSTS Pin
3.7
Clocking
3.7.1
Clock Sources
3.7.1.1
Primary Internal Oscillator (INTOSC2)
3.7.1.2
Backup Internal Oscillator (INTOSC1)
3.7.1.3
External Oscillator (XTAL)
3.7.1.4
Auxiliary Clock Input (AUXCLKIN)
3.7.2
Derived Clocks
3.7.2.1
Oscillator Clock (OSCCLK)
3.7.2.2
System PLL Output Clock (PLLRAWCLK)
3.7.2.3
Auxiliary Oscillator Clock (AUXOSCCLK)
3.7.2.4
Auxiliary PLL Output Clock (AUXPLLRAWCLK)
3.7.3
Device Clock Domains
3.7.3.1
System Clock (PLLSYSCLK)
3.7.3.2
CPU Clock (CPUCLK)
3.7.3.3
CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
3.7.3.4
Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
3.7.3.5
USB Auxiliary Clock (AUXPLLCLK)
3.7.3.6
CAN Bit Clock
3.7.3.7
CPU Timer2 Clock (TIMER2CLK)
3.7.4
XCLKOUT
3.7.5
Clock Connectivity
3.7.6
Clock Source and PLL Setup
3.7.6.1
Choosing PLL Settings
3.7.6.2
System Clock Setup
3.7.6.3
USB Auxiliary Clock Setup
3.7.6.4
Clock Configuration Examples
3.7.7
Clock (OSCCLK) Failure Detection
3.7.7.1
Missing Clock Detection Logic
3.8
32-Bit CPU Timers 0/1/2
3.9
Watchdog Timers
3.9.1
Servicing the Watchdog Timer
3.9.2
Minimum Window Check
3.9.3
Watchdog Reset or Watchdog Interrupt Mode
3.9.4
Watchdog Operation in Low-Power Modes
3.9.5
Emulation Considerations
3.10
Low-Power Modes
3.10.1
IDLE
3.10.2
STANDBY
3.10.3
HALT
3.10.4
Hibernate (HIB)
3.11
Memory Controller Module
3.11.1
Functional Description
3.11.1.1
Dedicated RAM (Dx RAM)
3.11.1.2
Local Shared RAM (LSx RAM)
3.11.1.3
Global Shared RAM (GSx RAM)
3.11.1.4
Message RAM (CLA MSGRAM)
3.11.1.5
Access Arbitration
3.11.1.6
Access Protection
3.11.1.6.1
CPU Fetch Protection
3.11.1.6.2
CPU Write Protection
3.11.1.6.3
CPU Read Protection
3.11.1.6.4
CLA Fetch Protection
3.11.1.6.5
CLA Write Protection
3.11.1.6.6
CLA Read Protection
3.11.1.6.7
DMA Write Protection
3.11.1.7
Memory Error Detection, Correction and Error Handling
3.11.1.7.1
Error Detection and Correction
3.11.1.7.2
Error Handling
3.11.1.8
Application Test Hooks for Error Detection and Correction
3.11.1.9
RAM Initialization
3.12
Flash and OTP Memory
3.12.1
Features
3.12.2
Flash Tools
3.12.3
Default Flash Configuration
3.12.4
Flash Bank, One-Time Programmable (OTP) Memory, and Flash Pump
3.12.5
Flash Module Controller (FMC)
3.12.6
Flash and OTP Memory Power-Down Modes and Wakeup
3.12.7
Flash and OTP Memory Performance
3.12.8
Flash Read Interface
3.12.8.1
FMC Flash Read Interface
3.12.8.1.1
Standard Read Mode
3.12.8.1.2
Prefetch Mode
3.12.8.1.2.1
Data Cache
3.12.9
Erase/Program Flash
3.12.9.1
Erase
3.12.9.2
Program
3.12.9.3
Verify
3.12.10
Error Correction Code (ECC) Protection
3.12.10.1
Single-Bit Data Error
3.12.10.2
Uncorrectable Error
3.12.10.3
SECDED Logic Correctness Check
3.12.10.4
Reading ECC Memory From a Higher Address Space
3.12.11
Reserved Locations Within Flash and OTP Memory
3.12.12
Procedure to Change the Flash Control Registers
3.12.13
Simple Procedure to Modify an Application from RAM Configuration to Flash Configuration
3.13
Dual Code Security Module (DCSM)
3.13.1
Functional Description
3.13.1.1
Emulation Code Security Logic (ECSL)
3.13.1.2
CPU Secure Logic
3.13.1.3
Execute-Only Protection
3.13.1.4
Password Lock
3.13.1.5
JTAG Lock
3.13.1.6
Link Pointer and Zone Select
3.13.1.6.1
C Code Example to get Zone Select Block Addr for Zone1
3.13.1.7
Flash and OTP Memory Erase/Program
3.13.1.8
Safe Copy Code
3.13.1.9
SafeCRC
3.13.2
CSM Impact on Other On-Chip Resources
3.13.3
Incorporating Code Security in User Applications
3.13.3.1
Environments That Require Security Unlocking
3.13.3.2
CSM Password Match Flow
3.13.3.3
Unsecuring Considerations for Zones With and Without Code Security
3.13.3.3.1
C Code Example to Unsecure C28x Zone1
3.13.3.3.2
C Code Example to Resecure C28x Zone1
3.13.3.4
Environments That Require ECSL Unlocking
3.13.3.5
ECSL Password Match Flow
3.13.3.6
ECSL Disable Considerations for any Zone
3.13.3.6.1
C Code Example to Disable ECSL for C28x-Zone1
3.13.3.7
Device Unique ID
3.14
JTAG
3.15
System Control Register Configuration Restrictions
3.16
Software
3.16.1
SYSCTL Examples
3.16.1.1
Missing clock detection (MCD)
3.16.1.2
XCLKOUT (External Clock Output) Configuration
3.16.2
TIMER Examples
3.16.2.1
CPU Timers
3.16.2.2
CPU Timers
3.16.3
MEMCFG Examples
3.16.4
INTERRUPT Examples
3.16.4.1
External Interrupts (ExternalInterrupt)
3.16.4.2
Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
3.16.4.3
CPU Timer Interrupt Software Prioritization
3.16.4.4
EPWM Real-Time Interrupt
3.16.5
LPM Examples
3.16.6
WATCHDOG Examples
3.16.6.1
Watchdog
3.17
System Control Registers
3.17.1
System Control Base Addresses
3.17.2
CPUTIMER_REGS Registers
3.17.3
PIE_CTRL_REGS Registers
3.17.4
WD_REGS Registers
3.17.5
NMI_INTRUPT_REGS Registers
3.17.6
XINT_REGS Registers
3.17.7
SYNC_SOC_REGS Registers
3.17.8
DMA_CLA_SRC_SEL_REGS Registers
3.17.9
DEV_CFG_REGS Registers
3.17.10
CLK_CFG_REGS Registers
3.17.11
CPU_SYS_REGS Registers
3.17.12
ROM_PREFETCH_REGS Registers
3.17.13
DCSM_Z1_REGS Registers
3.17.14
DCSM_Z2_REGS Registers
3.17.15
DCSM_COMMON_REGS Registers
3.17.16
MEM_CFG_REGS Registers
3.17.17
ACCESS_PROTECTION_REGS Registers
3.17.18
MEMORY_ERROR_REGS Registers
3.17.19
ROM_WAIT_STATE_REGS Registers
3.17.20
FLASH_CTRL_REGS Registers
3.17.21
FLASH_ECC_REGS Registers
3.17.22
UID_REGS Registers
3.17.23
DCSM_Z1_OTP Registers
3.17.24
DCSM_Z2_OTP Registers
3.17.25
Register to Driverlib Function Mapping
3.17.25.1
CPUTIMER Registers to Driverlib Functions
3.17.25.2
ASYSCTL Registers to Driverlib Functions
3.17.25.3
PIE Registers to Driverlib Functions
3.17.25.4
SYSCTL Registers to Driverlib Functions
3.17.25.5
NMI Registers to Driverlib Functions
3.17.25.6
XINT Registers to Driverlib Functions
3.17.25.7
DCSM Registers to Driverlib Functions
3.17.25.8
MEMCFG Registers to Driverlib Functions
3.17.25.9
FLASH Registers to Driverlib Functions
4
ROM Code and Peripheral Booting
4.1
Introduction
4.2
Boot ROM Registers
4.3
Device Boot Sequence
4.4
Device Boot Modes
4.5
Configuring Boot Mode Pins
4.6
Configuring Get Boot Options
4.7
Configuring Emulation Boot Options
4.8
Device Boot Flow Diagrams
4.8.1
Emulation Boot Flow Diagrams
4.8.2
Standalone and Hibernate Boot Flow Diagrams
4.9
Device Reset and Exception Handling
4.9.1
Reset Causes and Handling
4.9.2
Exceptions and Interrupts Handling
4.10
Boot ROM Description
4.10.1
Entry Points
4.10.2
Wait Points
4.10.3
Memory Maps
4.10.3.1
Boot ROM Memory Map
4.10.3.2
CLA Data ROM Memory Map
4.10.3.3
Reserved RAM and Flash Memory-Map
4.10.3.4
ROM Tables
4.10.3.4.1
Boot ROM Tables
4.10.3.4.2
CLA ROM Tables
4.10.4
Boot Modes
4.10.4.1
Wait Boot Mode
4.10.4.2
SCI Boot Mode
4.10.4.3
SPI Boot Mode
4.10.4.4
I2C Boot Mode
4.10.4.5
Parallel Boot Mode
4.10.4.6
CAN Boot Mode
4.10.4.7
USB Boot Mode
4.10.5
Boot Data Stream Structure
4.10.5.1
Bootloader Data Stream Structure
4.10.5.1.1
Data Stream Structure 8-bit
4.10.6
GPIO Assignments
4.10.7
Secure ROM Function APIs
4.10.8
Clock Initializations
4.10.9
Wait State Configuration
4.10.10
Boot Status information
4.10.10.1
CPU Booting Status
4.10.11
ROM Version
5
Direct Memory Access (DMA)
5.1
Introduction
5.1.1
Features
5.1.2
Block Diagram
5.2
Architecture
5.2.1
Common Peripheral Architecture
5.2.2
Peripheral Interrupt Event Trigger Sources
5.2.3
DMA Bus
5.3
Address Pointer and Transfer Control
5.4
Pipeline Timing and Throughput
5.5
CPU and CLA Arbitration
5.6
Channel Priority
5.6.1
Round-Robin Mode
5.6.2
Channel 1 High-Priority Mode
5.7
Overrun Detection Feature
5.8
Software
5.8.1
DMA Examples
5.8.1.1
DMA GSRAM Transfer (dma_ex1_gsram_transfer)
5.8.1.2
DMA Transfer Shared Peripheral - C28X_DUAL
5.8.1.3
DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
5.8.1.4
DMA GSRAM Transfer (dma_ex2_gsram_transfer)
5.9
DMA Registers
5.9.1
DMA Base Addresses
5.9.2
DMA_REGS Registers
5.9.3
DMA_CH_REGS Registers
5.9.4
DMA Registers to Driverlib Functions
6
Control Law Accelerator (CLA)
6.1
Introduction
6.1.1
Features
6.1.2
CLA Related Collateral
6.1.3
Block Diagram
6.2
CLA Interface
6.2.1
CLA Memory
6.2.2
CLA Memory Bus
6.2.3
Shared Peripherals and EALLOW Protection
6.2.4
CLA Tasks and Interrupt Vectors
6.2.5
CLA Software Interrupt to CPU
6.3
CLA and CPU Arbitration
6.3.1
CLA Message RAM
6.3.2
CLA Program Memory
6.3.3
CLA Data Memory
6.3.4
Peripheral Registers (ePWM, HRPWM, Comparator)
6.4
CLA Configuration and Debug
6.4.1
Building a CLA Application
6.4.2
Typical CLA Initialization Sequence
6.4.3
Debugging CLA Code
6.4.3.1
Breakpoint Support (MDEBUGSTOP)
6.4.4
CLA Illegal Opcode Behavior
6.4.5
Resetting the CLA
6.5
Pipeline
6.5.1
Pipeline Overview
6.5.2
CLA Pipeline Alignment
6.5.2.1
Code Fragment For MBCNDD, MCCNDD, or MRCNDD
332
6.5.2.2
Code Fragment for Loading MAR0 or MAR1
334
6.5.2.3
ADC Early Interrupt to CLA Response
6.5.3
Parallel Instructions
6.5.3.1
Math Operation with Parallel Load
6.5.3.2
Multiply with Parallel Add
6.5.4
CLA Task Execution Latency
6.6
Software
6.6.1
CLA Examples
6.6.1.1
CLA arcsine(x) using a lookup table (cla_asin_cpu01)
6.6.1.2
CLA arctangent(x) using a lookup table (cla_atan_cpu01)
6.7
Instruction Set
6.7.1
Instruction Descriptions
6.7.2
Addressing Modes and Encoding
6.7.3
Instructions
MABSF32 MRa, MRb
MADD32 MRa, MRb, MRc
MADDF32 MRa, #16FHi, MRb
MADDF32 MRa, MRb, #16FHi
MADDF32 MRa, MRb, MRc
MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
MAND32 MRa, MRb, MRc
MASR32 MRa, #SHIFT
MBCNDD 16BitDest [, CNDF]
MCCNDD 16BitDest [, CNDF]
MCMP32 MRa, MRb
MCMPF32 MRa, MRb
MCMPF32 MRa, #16FHi
MDEBUGSTOP
MEALLOW
MEDIS
MEINVF32 MRa, MRb
MEISQRTF32 MRa, MRb
MF32TOI16 MRa, MRb
MF32TOI16R MRa, MRb
MF32TOI32 MRa, MRb
MF32TOUI16 MRa, MRb
MF32TOUI16R MRa, MRb
MF32TOUI32 MRa, MRb
MFRACF32 MRa, MRb
MI16TOF32 MRa, MRb
MI16TOF32 MRa, mem16
MI32TOF32 MRa, mem32
MI32TOF32 MRa, MRb
MLSL32 MRa, #SHIFT
MLSR32 MRa, #SHIFT
MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
MMAXF32 MRa, MRb
MMAXF32 MRa, #16FHi
MMINF32 MRa, MRb
MMINF32 MRa, #16FHi
MMOV16 MARx, MRa, #16I
MMOV16 MARx, mem16
MMOV16 mem16, MARx
MMOV16 mem16, MRa
MMOV32 mem32, MRa
MMOV32 mem32, MSTF
MMOV32 MRa, mem32 [, CNDF]
MMOV32 MRa, MRb [, CNDF]
MMOV32 MSTF, mem32
MMOVD32 MRa, mem32
MMOVF32 MRa, #32F
MMOVI16 MARx, #16I
MMOVI32 MRa, #32FHex
MMOVIZ MRa, #16FHi
MMOVZ16 MRa, mem16
MMOVXI MRa, #16FLoHex
MMPYF32 MRa, MRb, MRc
MMPYF32 MRa, #16FHi, MRb
MMPYF32 MRa, MRb, #16FHi
MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
MNEGF32 MRa, MRb[, CNDF]
MNOP
MOR32 MRa, MRb, MRc
MRCNDD [CNDF]
MSETFLG FLAG, VALUE
MSTOP
MSUB32 MRa, MRb, MRc
MSUBF32 MRa, MRb, MRc
MSUBF32 MRa, #16FHi, MRb
MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
MSWAPF MRa, MRb [, CNDF]
MTESTTF CNDF
MUI16TOF32 MRa, mem16
MUI16TOF32 MRa, MRb
MUI32TOF32 MRa, mem32
MUI32TOF32 MRa, MRb
MXOR32 MRa, MRb, MRc
6.8
CLA Registers
6.8.1
CLA Base Addresses
6.8.2
CLA_REGS Registers
6.8.3
CLA_SOFTINT_REGS Registers
6.8.4
CLA Registers to Driverlib Functions
7
General-Purpose Input/Output (GPIO)
7.1
Introduction
7.1.1
GPIO Related Collateral
7.2
Configuration Overview
7.3
Digital General-Purpose I/O Control
7.4
Input Qualification
7.4.1
No Synchronization (Asynchronous Input)
7.4.2
Synchronization to SYSCLKOUT Only
7.4.3
Qualification Using a Sampling Window
7.5
USB Signals
7.6
SPI Signals
7.7
GPIO and Peripheral Muxing
7.7.1
GPIO Muxing
7.7.2
Peripheral Muxing
7.8
Internal Pullup Configuration Requirements
7.9
Software
7.9.1
GPIO Examples
7.9.1.1
Device GPIO Setup
7.9.1.2
Device GPIO Toggle
7.9.1.3
Device GPIO Interrupt
7.9.2
LED Examples
7.10
GPIO Registers
7.10.1
GPIO Base Addresses
7.10.2
GPIO_CTRL_REGS Registers
7.10.3
GPIO_DATA_REGS Registers
7.10.4
GPIO Registers to Driverlib Functions
8
Crossbar (X-BAR)
8.1
Input X-BAR
8.2
ePWM, CLB, and GPIO Output X-BAR
8.2.1
ePWM X-BAR
8.2.1.1
ePWM X-BAR Architecture
8.2.2
CLB X-BAR
8.2.2.1
CLB X-BAR Architecture
8.2.3
GPIO Output X-BAR
8.2.3.1
GPIO Output X-BAR Architecture
8.2.4
X-BAR Flags
8.3
XBAR Registers
8.3.1
XBAR Base Addresses
8.3.2
INPUT_XBAR_REGS Registers
8.3.3
XBAR_REGS Registers
8.3.4
EPWM_XBAR_REGS Registers
8.3.5
CLB_XBAR_REGS Registers
8.3.6
OUTPUT_XBAR_REGS Registers
8.3.7
Register to Driverlib Function Mapping
8.3.7.1
INPUTXBAR Registers to Driverlib Functions
8.3.7.2
XBAR Registers to Driverlib Functions
8.3.7.3
EPWMXBAR Registers to Driverlib Functions
8.3.7.4
CLBXBAR Registers to Driverlib Functions
8.3.7.5
OUTPUTXBAR Registers to Driverlib Functions
9
Analog Subsystem
9.1
Introduction
9.1.1
Features
9.1.2
Block Diagram
9.2
Optimizing Power-Up Time
9.3
Analog Subsystem Registers
9.3.1
Analog Subsystem Base Addresses
9.3.2
ANALOG_SUBSYS_REGS Registers
10
Analog-to-Digital Converter (ADC)
10.1
Introduction
10.1.1
ADC Related Collateral
10.1.2
Features
10.1.3
Block Diagram
10.2
ADC Configurability
10.2.1
Clock Configuration
10.2.2
Resolution
10.2.3
Voltage Reference
10.2.3.1
External Reference Mode
10.2.4
Signal Mode
10.2.5
Expected Conversion Results
10.2.6
Interpreting Conversion Results
10.3
SOC Principle of Operation
10.3.1
SOC Configuration
10.3.2
Trigger Operation
10.3.3
ADC Acquisition (Sample and Hold) Window
10.3.4
ADC Input Models
10.3.5
Channel Selection
10.4
SOC Configuration Examples
10.4.1
Single Conversion from ePWM Trigger
10.4.2
Oversampled Conversion from ePWM Trigger
10.4.3
Multiple Conversions from CPU Timer Trigger
10.4.4
Software Triggering of SOCs
10.5
ADC Conversion Priority
10.6
Burst Mode
10.6.1
Burst Mode Example
10.6.2
Burst Mode Priority Example
10.7
EOC and Interrupt Operation
10.7.1
Interrupt Overflow
10.7.2
Continue to Interrupt Mode
10.7.3
Early Interrupt Configuration Mode
10.8
Post-Processing Blocks
10.8.1
PPB Offset Correction
10.8.2
PPB Error Calculation
10.8.3
PPB Limit Detection and Zero-Crossing Detection
10.8.4
PPB Sample Delay Capture
10.9
Opens/Shorts Detection Circuit (OSDETECT)
10.9.1
Implementation
10.9.2
Detecting an Open Input Pin
10.9.3
Detecting a Shorted Input Pin
10.10
Power-Up Sequence
10.11
ADC Calibration
10.11.1
ADC Zero Offset Calibration
10.12
ADC Timings
10.12.1
ADC Timing Diagrams
10.13
Additional Information
10.13.1
Ensuring Synchronous Operation
10.13.1.1
Basic Synchronous Operation
10.13.1.2
Synchronous Operation with Multiple Trigger Sources
10.13.1.3
Synchronous Operation with Uneven SOC Numbers
10.13.1.4
Non-overlapping Conversions
10.13.2
Choosing an Acquisition Window Duration
10.13.3
Achieving Simultaneous Sampling
10.13.4
Result Register Mapping
10.13.5
Internal Temperature Sensor
10.13.6
Designing an External Reference Circuit
10.14
Software
10.14.1
ADC Examples
10.14.1.1
ADC Software Triggering
10.14.1.2
ADC ePWM Triggering
10.14.1.3
ADC Temperature Sensor Conversion
10.14.1.4
ADC Synchronous SOC Software Force (adc_soc_software_sync)
10.14.1.5
ADC Continuous Triggering (adc_soc_continuous)
10.14.1.6
ADC PPB Offset (adc_ppb_offset)
10.14.1.7
ADC PPB Limits (adc_ppb_limits)
10.14.1.8
ADC PPB Delay Capture (adc_ppb_delay)
10.14.1.9
ADC ePWM Triggering Multiple SOC
10.14.1.10
ADC Burst Mode
10.14.1.11
ADC Burst Mode Oversampling
10.14.1.12
ADC SOC Oversampling
10.14.1.13
ADC PPB PWM trip (adc_ppb_pwm_trip)
10.15
ADC Registers
10.15.1
ADC Base Addresses
10.15.2
ADC_RESULT_REGS Registers
10.15.3
ADC_REGS Registers
10.15.4
ADC Registers to Driverlib Functions
11
Buffered Digital-to-Analog Converter (DAC)
11.1
Introduction
11.1.1
DAC Related Collateral
11.1.2
Features
11.1.3
Block Diagram
11.2
Using the DAC
11.2.1
Initialization Sequence
11.2.2
DAC Offset Adjustment
11.2.3
EPWMSYNCPER Signal
11.3
Lock Registers
11.4
Software
11.4.1
DAC Examples
11.4.1.1
Buffered DAC Enable
11.4.1.2
Buffered DAC Random
11.4.1.3
Buffered DAC Sine (buffdac_sine)
11.5
DAC Registers
11.5.1
DAC Base Addresses
11.5.2
DAC_REGS Registers
11.5.3
DAC Registers to Driverlib Functions
12
Comparator Subsystem (CMPSS)
12.1
Introduction
12.1.1
CMPSS Related Collateral
12.1.2
Features
12.1.3
Block Diagram
12.2
Comparator
12.3
Reference DAC
12.4
Ramp Generator
12.4.1
Ramp Generator Overview
12.4.2
Ramp Generator Behavior
12.4.3
Ramp Generator Behavior at Corner Cases
12.5
Digital Filter
12.5.1
Filter Initialization Sequence
12.6
Using the CMPSS
12.6.1
LATCHCLR and EPWMSYNCPER Signals
12.6.2
Synchronizer, Digital Filter, and Latch Delays
12.6.3
Calibrating the CMPSS
12.6.4
Enabling and Disabling the CMPSS Clock
12.7
Software
12.7.1
CMPSS Examples
12.7.1.1
CMPSS Asynchronous Trip
12.7.1.2
CMPSS Digital Filter Configuration
12.8
CMPSS Registers
12.8.1
CMPSS Base Addresses
12.8.2
CMPSS_REGS Registers
12.8.3
CMPSS Registers to Driverlib Functions
13
Sigma Delta Filter Module (SDFM)
13.1
Introduction
13.1.1
SDFM Related Collateral
13.1.2
Features
13.1.3
Block Diagram
13.2
Configuring Device Pins
13.3
Input Control Unit
13.4
Sinc Filter
13.4.1
Data Rate and Latency of the Sinc Filter
13.5
Data (Primary) Filter Unit
13.5.1
32-bit or 16-bit Data Filter Output Representation
13.5.2
SDSYNC Event
13.6
Comparator (Secondary) Filter Unit
13.6.1
Higher Threshold (HLT) Comparator
13.6.2
Lower Threshold (LLT) Comparator
13.7
Theoretical SDFM Filter Output
13.8
Interrupt Unit
13.8.1
SDFM (SDINT) Interrupt Sources
13.9
Register Descriptions
13.10
Software
13.10.1
SDFM Examples
13.11
SDFM Registers
13.11.1
SDFM Base Addresses
13.11.2
SDFM_REGS Registers
13.11.3
SDFM Registers to Driverlib Functions
14
Enhanced Pulse Width Modulator (ePWM)
14.1
Introduction
14.1.1
EPWM Related Collateral
14.1.2
Submodule Overview
14.2
Configuring Device Pins
14.3
ePWM Modules Overview
14.4
Time-Base (TB) Submodule
14.4.1
Purpose of the Time-Base Submodule
14.4.2
Controlling and Monitoring the Time-Base Submodule
14.4.3
Calculating PWM Period and Frequency
14.4.3.1
Time-Base Period Shadow Register
14.4.3.2
Time-Base Clock Synchronization
14.4.3.3
Time-Base Counter Synchronization
14.4.4
Phase Locking the Time-Base Clocks of Multiple ePWM Modules
14.4.5
Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
14.4.6
Time-Base Counter Modes and Timing Waveforms
14.4.7
Global Load
14.4.7.1
Global Load Pulse Pre-Scalar
14.4.7.2
One-Shot Load Mode
14.4.7.3
One-Shot Sync Mode
14.5
Counter-Compare (CC) Submodule
14.5.1
Purpose of the Counter-Compare Submodule
14.5.2
Controlling and Monitoring the Counter-Compare Submodule
14.5.3
Operational Highlights for the Counter-Compare Submodule
14.5.4
Count Mode Timing Waveforms
14.6
Action-Qualifier (AQ) Submodule
14.6.1
Purpose of the Action-Qualifier Submodule
14.6.2
Action-Qualifier Submodule Control and Status Register Definitions
14.6.3
Action-Qualifier Event Priority
14.6.4
AQCTLA and AQCTLB Shadow Mode Operations
14.6.5
Configuration Requirements for Common Waveforms
14.7
Dead-Band Generator (DB) Submodule
14.7.1
Purpose of the Dead-Band Submodule
14.7.2
Dead-band Submodule Additional Operating Modes
14.7.3
Operational Highlights for the Dead-Band Submodule
14.8
PWM Chopper (PC) Submodule
14.8.1
Purpose of the PWM Chopper Submodule
14.8.2
Operational Highlights for the PWM Chopper Submodule
14.8.3
Waveforms
14.8.3.1
One-Shot Pulse
14.8.3.2
Duty Cycle Control
14.9
Trip-Zone (TZ) Submodule
14.9.1
Purpose of the Trip-Zone Submodule
14.9.2
Operational Highlights for the Trip-Zone Submodule
14.9.2.1
Trip-Zone Configurations
14.9.3
Generating Trip Event Interrupts
14.10
Event-Trigger (ET) Submodule
14.10.1
Operational Overview of the ePWM Event-Trigger Submodule
14.11
Digital Compare (DC) Submodule
14.11.1
Purpose of the Digital Compare Submodule
14.11.2
Enhanced Trip Action Using CMPSS
14.11.3
Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
14.11.4
Operation Highlights of the Digital Compare Submodule
14.11.4.1
Digital Compare Events
14.11.4.2
Event Filtering
14.11.4.3
Valley Switching
14.12
ePWM Crossbar (X-BAR)
14.13
Applications to Power Topologies
14.13.1
Overview of Multiple Modules
14.13.2
Key Configuration Capabilities
14.13.3
Controlling Multiple Buck Converters With Independent Frequencies
14.13.4
Controlling Multiple Buck Converters With Same Frequencies
14.13.5
Controlling Multiple Half H-Bridge (HHB) Converters
14.13.6
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
14.13.7
Practical Applications Using Phase Control Between PWM Modules
14.13.8
Controlling a 3-Phase Interleaved DC/DC Converter
14.13.9
Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
14.13.10
Controlling a Peak Current Mode Controlled Buck Module
14.13.11
Controlling H-Bridge LLC Resonant Converter
14.14
High-Resolution Pulse Width Modulator (HRPWM)
14.14.1
Operational Description of HRPWM
14.14.1.1
Controlling the HRPWM Capabilities
14.14.1.2
HRPWM Source Clock
14.14.1.3
Configuring the HRPWM
14.14.1.4
Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
14.14.1.5
Principle of Operation
14.14.1.5.1
Edge Positioning
14.14.1.5.2
Scaling Considerations
14.14.1.5.3
Duty Cycle Range Limitation
14.14.1.5.4
High-Resolution Period
14.14.1.5.4.1
High-Resolution Period Configuration
14.14.1.6
Deadband High-Resolution Operation
14.14.1.7
Scale Factor Optimizing Software (SFO)
14.14.1.8
HRPWM Examples Using Optimized Assembly Code
14.14.1.8.1
#Defines for HRPWM Header Files
14.14.1.8.2
Implementing a Simple Buck Converter
14.14.1.8.2.1
HRPWM Buck Converter Initialization Code
14.14.1.8.2.2
HRPWM Buck Converter Run-Time Code
14.14.1.8.3
Implementing a DAC Function Using an R+C Reconstruction Filter
14.14.1.8.3.1
PWM DAC Function Initialization Code
14.14.1.8.3.2
PWM DAC Function Run-Time Code
14.14.2
SFO Library Software - SFO_TI_Build_V8.lib
14.14.2.1
Scale Factor Optimizer Function - int SFO()
14.14.2.2
Software Usage
14.14.2.2.1
A Sample of How to Add "Include" Files
730
14.14.2.2.2
Declaring an Element
732
14.14.2.2.3
Initializing With a Scale Factor Value
734
14.14.2.2.4
SFO Function Calls
14.15
ePWM Registers
14.15.1
ePWM Base Addresses
14.15.2
EPWM_REGS Registers
14.15.3
Register to Driverlib Function Mapping
14.15.3.1
EPWM Registers to Driverlib Functions
14.15.3.2
HRPWM Registers to Driverlib Functions
15
Enhanced Capture (eCAP)
15.1
Introduction
15.1.1
Features
15.1.2
ECAP Related Collateral
15.2
Description
15.3
Configuring Device Pins for the eCAP
15.4
Capture and APWM Operating Mode
15.5
Capture Mode Description
15.5.1
Event Prescaler
15.5.2
Edge Polarity Select and Qualifier
15.5.3
Continuous/One-Shot Control
15.5.4
32-Bit Counter and Phase Control
15.5.5
CAP1-CAP4 Registers
15.5.6
eCAP Synchronization
15.5.6.1
Example 1 - Using SWSYNC with ECAP Module
15.5.7
Interrupt Control
15.5.8
DMA Interrupt
15.5.9
Shadow Load and Lockout Control
15.5.10
APWM Mode Operation
15.6
Application of the eCAP Module
15.6.1
Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
15.6.2
Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
15.6.3
Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
15.6.4
Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
15.7
Application of the APWM Mode
15.7.1
Example 1 - Simple PWM Generation (Independent Channels)
15.8
Software
15.8.1
ECAP Examples
15.8.1.1
eCAP APWM Example
15.8.1.2
eCAP Capture PWM Example
15.8.1.3
eCAP APWM Phase-shift Example
15.8.1.4
eCAP Software Sync Example
15.9
eCAP Registers
15.9.1
eCAP Base Addresses
15.9.2
ECAP_REGS Registers
15.9.3
ECAP Registers to Driverlib Functions
16
Enhanced Quadrature Encoder Pulse (eQEP)
16.1
Introduction
16.1.1
EQEP Related Collateral
16.2
Configuring Device Pins
16.3
Description
16.3.1
EQEP Inputs
16.3.2
Functional Description
16.3.3
eQEP Memory Map
16.4
Quadrature Decoder Unit (QDU)
16.4.1
Position Counter Input Modes
16.4.1.1
Quadrature Count Mode
16.4.1.2
Direction-Count Mode
16.4.1.3
Up-Count Mode
16.4.1.4
Down-Count Mode
16.4.2
eQEP Input Polarity Selection
16.4.3
Position-Compare Sync Output
16.5
Position Counter and Control Unit (PCCU)
16.5.1
Position Counter Operating Modes
16.5.1.1
Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
16.5.1.2
Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
16.5.1.3
Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
16.5.1.4
Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
16.5.2
Position Counter Latch
16.5.2.1
Index Event Latch
16.5.2.2
Strobe Event Latch
16.5.3
Position Counter Initialization
16.5.4
eQEP Position-compare Unit
16.6
eQEP Edge Capture Unit
16.7
eQEP Watchdog
16.8
eQEP Unit Timer Base
16.9
eQEP Interrupt Structure
16.10
eQEP Registers
16.10.1
eQEP Base Addresses
16.10.2
EQEP_REGS Registers
16.10.3
EQEP Registers to Driverlib Functions
17
Serial Peripheral Interface (SPI)
17.1
Introduction
17.1.1
Features
17.1.2
SPI Related Collateral
17.1.3
Block Diagram
17.2
System-Level Integration
17.2.1
SPI Module Signals
17.2.2
Configuring Device Pins
17.2.2.1
GPIOs Required for High-Speed Mode
17.2.3
SPI Interrupts
17.2.4
DMA Support
17.3
SPI Operation
17.3.1
Introduction to Operation
17.3.2
Master Mode
17.3.3
Slave Mode
17.3.4
Data Format
17.3.4.1
Transmission of Bit from SPIRXBUF
17.3.5
Baud Rate Selection
17.3.5.1
Baud Rate Determination
17.3.5.2
Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
17.3.6
SPI Clocking Schemes
17.3.7
SPI FIFO Description
17.3.8
SPI DMA Transfers
17.3.8.1
Transmitting Data Using SPI with DMA
17.3.8.2
Receiving Data Using SPI with DMA
17.3.9
SPI High-Speed Mode
17.3.10
SPI 3-Wire Mode Description
17.4
Programming Procedure
17.4.1
Initialization Upon Reset
17.4.2
Configuring the SPI
17.4.3
Configuring the SPI for High-Speed Mode
17.4.4
Data Transfer Example
17.4.5
SPI 3-Wire Mode Code Examples
17.4.5.1
3-Wire Master Mode Transmit
847
17.4.5.2.1
3-Wire Master Mode Receive
849
17.4.5.2.1
3-Wire Slave Mode Transmit
851
17.4.5.2.1
3-Wire Slave Mode Receive
17.4.6
SPI STEINV Bit in Digital Audio Transfers
17.5
Software
17.5.1
SPI Examples
17.5.1.1
SPI Digital Loopback
17.5.1.2
SPI Digital Loopback with FIFO Interrupts
17.5.1.3
SPI Digital External Loopback without FIFO Interrupts
17.5.1.4
SPI Digital External Loopback with FIFO Interrupts
17.5.1.5
SPI Digital Loopback with DMA
17.5.1.6
SPI EEPROM
17.5.1.7
SPI DMA EEPROM
17.6
SPI Registers
17.6.1
SPI Base Addresses
17.6.2
SPI_REGS Registers
17.6.3
SPI Registers to Driverlib Functions
18
Serial Communications Interface (SCI)
18.1
Introduction
18.1.1
Features
18.1.2
SCI Related Collateral
18.1.3
Block Diagram
18.2
Architecture
18.3
SCI Module Signal Summary
18.4
Configuring Device Pins
18.5
Multiprocessor and Asynchronous Communication Modes
18.6
SCI Programmable Data Format
18.7
SCI Multiprocessor Communication
18.7.1
Recognizing the Address Byte
18.7.2
Controlling the SCI TX and RX Features
18.7.3
Receipt Sequence
18.8
Idle-Line Multiprocessor Mode
18.8.1
Idle-Line Mode Steps
18.8.2
Block Start Signal
18.8.3
Wake-Up Temporary (WUT) Flag
18.8.3.1
Sending a Block Start Signal
18.8.4
Receiver Operation
18.9
Address-Bit Multiprocessor Mode
18.9.1
Sending an Address
18.10
SCI Communication Format
18.10.1
Receiver Signals in Communication Modes
18.10.2
Transmitter Signals in Communication Modes
18.11
SCI Port Interrupts
18.11.1
Break Detect
18.12
SCI Baud Rate Calculations
18.13
SCI Enhanced Features
18.13.1
SCI FIFO Description
18.13.2
SCI Auto-Baud
18.13.3
Autobaud-Detect Sequence
18.14
Software
18.14.1
SCI Examples
18.15
SCI Registers
18.15.1
SCI Base Addresses
18.15.2
SCI_REGS Registers
18.15.3
SCI Registers to Driverlib Functions
19
Inter-Integrated Circuit Module (I2C)
19.1
Introduction
19.1.1
I2C Related Collateral
19.1.2
Features
19.1.3
Features Not Supported
19.1.4
Functional Overview
19.1.5
Clock Generation
19.1.6
I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
19.1.6.1
Formula for the Master Clock Period
19.2
Configuring Device Pins
19.3
I2C Module Operational Details
19.3.1
Input and Output Voltage Levels
19.3.2
Selecting Pullup Resistors
19.3.3
Data Validity
19.3.4
Operating Modes
19.3.5
I2C Module START and STOP Conditions
19.3.6
Non-repeat Mode versus Repeat Mode
19.3.7
Serial Data Formats
19.3.7.1
7-Bit Addressing Format
19.3.7.2
10-Bit Addressing Format
19.3.7.3
Free Data Format
19.3.7.4
Using a Repeated START Condition
19.3.8
Clock Synchronization
19.3.9
Arbitration
19.3.10
Digital Loopback Mode
19.3.11
NACK Bit Generation
19.4
Interrupt Requests Generated by the I2C Module
19.4.1
Basic I2C Interrupt Requests
19.4.2
I2C FIFO Interrupts
19.5
Resetting or Disabling the I2C Module
19.6
Software
19.6.1
I2C Examples
19.6.1.1
C28x-I2C Library source file for FIFO interrupts
19.6.1.2
C28x-I2C Library source file for FIFO using polling
19.6.1.3
C28x-I2C Library source file for FIFO interrupts
19.6.1.4
I2C Digital Loopback with FIFO Interrupts
19.6.1.5
I2C EEPROM
19.6.1.6
I2C Digital External Loopback with FIFO Interrupts
19.6.1.7
I2C EEPROM
19.6.1.8
I2C controller target communication using FIFO interrupts
19.6.1.9
I2C EEPROM
19.7
I2C Registers
19.7.1
I2C Base Addresses
19.7.2
I2C_REGS Registers
19.7.3
I2C Registers to Driverlib Functions
20
Multichannel Buffered Serial Port (McBSP)
20.1
Introduction
20.1.1
MCBSP Related Collateral
20.1.2
Features of the McBSPs
20.1.3
McBSP Pins/Signals
20.1.3.1
McBSP Generic Block Diagram
20.2
Configuring Device Pins
20.3
McBSP Operation
20.3.1
Data Transfer Process of McBSPs
20.3.1.1
Data Transfer Process for Word Length of 8, 12, or 16 Bits
20.3.1.2
Data Transfer Process for Word Length of 20, 24, or 32 Bits
20.3.2
Companding (Compressing and Expanding) Data
20.3.2.1
Companding Formats
20.3.2.2
Capability to Compand Internal Data
20.3.2.3
Reversing Bit Order: Option to Transfer LSB First
20.3.3
Clocking and Framing Data
20.3.3.1
Clocking
20.3.3.2
Serial Words
20.3.3.3
Frames and Frame Synchronization
20.3.3.4
Generating Transmit and Receive Interrupts
20.3.3.4.1
Detecting Frame-Synchronization Pulses, Even in Reset State
20.3.3.5
Ignoring Frame-Synchronization Pulses
20.3.3.6
Frame Frequency
20.3.3.7
Maximum Frame Frequency
20.3.4
Frame Phases
20.3.4.1
Number of Phases, Words, and Bits Per Frame
20.3.4.2
Single-Phase Frame Example
20.3.4.3
Dual-Phase Frame Example
20.3.4.4
Implementing the AC97 Standard With a Dual-Phase Frame
20.3.5
McBSP Reception
20.3.6
McBSP Transmission
20.3.7
Interrupts and DMA Events Generated by a McBSP
20.4
McBSP Sample Rate Generator
20.4.1
Block Diagram
20.4.1.1
Clock Generation in the Sample Rate Generator
20.4.1.2
Choosing an Input Clock
20.4.1.3
Choosing a Polarity for the Input Clock
20.4.1.4
Choosing a Frequency for the Output Clock (CLKG)
20.4.1.4.1
CLKG Frequency
20.4.1.5
Keeping CLKG Synchronized to External MCLKR
20.4.2
Frame Synchronization Generation in the Sample Rate Generator
20.4.2.1
Choosing the Width of the Frame-Synchronization Pulse on FSG
20.4.2.2
Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
20.4.2.3
Keeping FSG Synchronized to an External Clock
20.4.3
Synchronizing Sample Rate Generator Outputs to an External Clock
20.4.3.1
Operating the Transmitter Synchronously with the Receiver
20.4.3.2
Synchronization Examples
20.4.4
Reset and Initialization Procedure for the Sample Rate Generator
20.5
McBSP Exception/Error Conditions
20.5.1
Types of Errors
20.5.2
Overrun in the Receiver
20.5.2.1
Example of Overrun Condition
20.5.2.2
Example of Preventing Overrun Condition
20.5.3
Unexpected Receive Frame-Synchronization Pulse
20.5.3.1
Possible Responses to Receive Frame-Synchronization Pulses
20.5.3.2
Example of Unexpected Receive Frame-Synchronization Pulse
20.5.3.3
Preventing Unexpected Receive Frame-Synchronization Pulses
20.5.4
Overwrite in the Transmitter
20.5.4.1
Example of Overwrite Condition
20.5.4.2
Preventing Overwrites
20.5.5
Underflow in the Transmitter
20.5.5.1
Example of the Underflow Condition
20.5.5.2
Example of Preventing Underflow Condition
20.5.6
Unexpected Transmit Frame-Synchronization Pulse
20.5.6.1
Possible Responses to Transmit Frame-Synchronization Pulses
20.5.6.2
Example of Unexpected Transmit Frame-Synchronization Pulse
20.5.6.3
Preventing Unexpected Transmit Frame-Synchronization Pulses
20.6
Multichannel Selection Modes
20.6.1
Channels, Blocks, and Partitions
20.6.2
Multichannel Selection
20.6.3
Configuring a Frame for Multichannel Selection
20.6.4
Using Two Partitions
20.6.4.1
Assigning Blocks to Partitions A and B
20.6.4.2
Reassigning Blocks During Reception/Transmission
20.6.5
Using Eight Partitions
20.6.6
Receive Multichannel Selection Mode
20.6.7
Transmit Multichannel Selection Modes
20.6.7.1
Disabling/Enabling Versus Masking/Unmasking
20.6.7.2
Activity on McBSP Pins for Different Values of XMCM
20.6.8
Using Interrupts Between Block Transfers
20.7
SPI Operation Using the Clock Stop Mode
20.7.1
SPI Protocol
20.7.2
Clock Stop Mode
20.7.3
Enable and Configure the Clock Stop Mode
20.7.4
Clock Stop Mode Timing Diagrams
20.7.5
Procedure for Configuring a McBSP for SPI Operation
20.7.6
McBSP as the SPI Master
20.7.7
McBSP as an SPI Slave
20.8
Receiver Configuration
20.8.1
Programming the McBSP Registers for the Desired Receiver Operation
20.8.2
Resetting and Enabling the Receiver
20.8.2.1
Reset Considerations
20.8.3
Set the Receiver Pins to Operate as McBSP Pins
20.8.4
Digital Loopback Mode
20.8.5
Clock Stop Mode
20.8.6
Receive Multichannel Selection Mode
20.8.7
Receive Frame Phases
20.8.8
Receive Word Lengths
20.8.8.1
Word Length Bits
20.8.9
Receive Frame Length
20.8.9.1
Selected Frame Length
20.8.10
Receive Frame-Synchronization Ignore Function
20.8.10.1
Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
20.8.10.2
Examples of Effects of RFIG
20.8.11
Receive Companding Mode
20.8.11.1
Companding
20.8.11.2
Format of Expanded Data
20.8.11.3
Companding Internal Data
20.8.11.4
Option to Receive LSB First
20.8.12
Receive Data Delay
20.8.12.1
Data Delay
20.8.12.2
0-Bit Data Delay
20.8.12.3
2-Bit Data Delay
20.8.13
Receive Sign-Extension and Justification Mode
20.8.13.1
Sign-Extension and the Justification
20.8.14
Receive Interrupt Mode
20.8.15
Receive Frame-Synchronization Mode
20.8.15.1
Receive Frame-Synchronization Modes
20.8.16
Receive Frame-Synchronization Polarity
20.8.16.1
Frame-Synchronization Pulses, Clock Signals, and Their Polarities
20.8.16.2
Frame-Synchronization Period and the Frame-Synchronization Pulse Width
20.8.17
Receive Clock Mode
20.8.17.1
Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
20.8.18
Receive Clock Polarity
20.8.18.1
Frame Synchronization Pulses, Clock Signals, and Their Polarities
20.8.19
SRG Clock Divide-Down Value
20.8.19.1
Sample Rate Generator Clock Divider
20.8.20
SRG Clock Synchronization Mode
20.8.21
SRG Clock Mode (Choose an Input Clock)
20.8.22
SRG Input Clock Polarity
20.8.22.1
Using CLKXP/CLKRP to Choose an Input Clock Polarity
20.9
Transmitter Configuration
20.9.1
Programming the McBSP Registers for the Desired Transmitter Operation
20.9.2
Resetting and Enabling the Transmitter
20.9.2.1
Reset Considerations
20.9.3
Set the Transmitter Pins to Operate as McBSP Pins
20.9.4
Digital Loopback Mode
20.9.5
Clock Stop Mode
20.9.6
Transmit Multichannel Selection Mode
20.9.7
XCERs Used in the Transmit Multichannel Selection Mode
20.9.8
Transmit Frame Phases
20.9.9
Transmit Word Lengths
20.9.9.1
Word Length Bits
20.9.10
Transmit Frame Length
20.9.10.1
Selected Frame Length
20.9.11
Enable/Disable the Transmit Frame-Synchronization Ignore Function
20.9.11.1
Unexpected Frame-Synchronization Pulses and Frame-Synchronization Ignore
20.9.11.2
Examples Showing the Effects of XFIG
20.9.12
Transmit Companding Mode
20.9.12.1
Companding
20.9.12.2
Format for Data To Be Compressed
20.9.12.3
Capability to Compand Internal Data
20.9.12.4
Option to Transmit LSB First
20.9.13
Transmit Data Delay
20.9.13.1
Data Delay
20.9.13.2
0-Bit Data Delay
20.9.13.3
2-Bit Data Delay
20.9.14
Transmit DXENA Mode
20.9.15
Transmit Interrupt Mode
20.9.16
Transmit Frame-Synchronization Mode
20.9.16.1
Other Considerations
20.9.17
Transmit Frame-Synchronization Polarity
20.9.17.1
Frame Synchronization Pulses, Clock Signals, and Their Polarities
20.9.18
SRG Frame-Synchronization Period and Pulse Width
20.9.18.1
Frame-Synchronization Period and Frame-Synchronization Pulse Width
20.9.19
Transmit Clock Mode
20.9.19.1
Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
20.9.19.2
Other Considerations
20.9.20
Transmit Clock Polarity
20.9.20.1
Frame Synchronization Pulses, Clock Signals, and Their Polarities
20.10
Emulation and Reset Considerations
20.10.1
McBSP Emulation Mode
20.10.2
Resetting and Initializing McBSPs
20.10.2.1
McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
20.10.2.2
Device Reset, McBSP Reset, and Sample Rate Generator Reset
20.10.2.3
McBSP Initialization Procedure
20.10.2.4
Resetting the Transmitter While the Receiver is Running
20.10.2.4.1
Resetting and Configuring McBSP Transmitter While McBSP Receiver Running
20.11
Data Packing Examples
20.11.1
Data Packing Using Frame Length and Word Length
20.11.2
Data Packing Using Word Length and the Frame-Synchronization Ignore Function
20.12
Interrupt Generation
20.12.1
McBSP Receive Interrupt Generation
20.12.2
McBSP Transmit Interrupt Generation
20.12.3
Error Flags
20.13
McBSP Modes
20.14
Special Case: External Device is the Transmit Frame Master
20.15
Software
20.15.1
MCBSP Examples
20.16
McBSP Registers
20.16.1
McBSP Base Addresses
20.16.2
McBSP_REGS Registers
20.16.3
MCBSP Registers to Driverlib Functions
21
Controller Area Network (CAN)
21.1
Introduction
21.1.1
DCAN Related Collateral
21.1.2
Features
21.1.3
Block Diagram
21.1.3.1
CAN Core
21.1.3.2
Message Handler
21.1.3.3
Message RAM
21.1.3.4
Registers and Message Object Access (IFx)
21.2
Functional Description
21.2.1
Configuring Device Pins
21.2.2
Address/Data Bus Bridge
21.3
Operating Modes
21.3.1
Initialization
21.3.2
CAN Message Transfer (Normal Operation)
21.3.2.1
Disabled Automatic Retransmission
21.3.2.2
Auto-Bus-On
21.3.3
Test Modes
21.3.3.1
Silent Mode
21.3.3.2
Loopback Mode
21.3.3.3
External Loopback Mode
21.3.3.4
Loopback Combined with Silent Mode
21.4
Multiple Clock Source
21.5
Interrupt Functionality
21.5.1
Message Object Interrupts
21.5.2
Status Change Interrupts
21.5.3
Error Interrupts
21.5.4
Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
21.5.5
Interrupt Topologies
21.6
Parity Check Mechanism
21.6.1
Behavior on Parity Error
21.7
Debug Mode
21.8
Module Initialization
21.9
Configuration of Message Objects
21.9.1
Configuration of a Transmit Object for Data Frames
21.9.2
Configuration of a Transmit Object for Remote Frames
21.9.3
Configuration of a Single Receive Object for Data Frames
21.9.4
Configuration of a Single Receive Object for Remote Frames
21.9.5
Configuration of a FIFO Buffer
21.10
Message Handling
21.10.1
Message Handler Overview
21.10.2
Receive/Transmit Priority
21.10.3
Transmission of Messages in Event Driven CAN Communication
21.10.4
Updating a Transmit Object
21.10.5
Changing a Transmit Object
21.10.6
Acceptance Filtering of Received Messages
21.10.7
Reception of Data Frames
21.10.8
Reception of Remote Frames
21.10.9
Reading Received Messages
21.10.10
Requesting New Data for a Receive Object
21.10.11
Storing Received Messages in FIFO Buffers
21.10.12
Reading from a FIFO Buffer
21.11
CAN Bit Timing
21.11.1
Bit Time and Bit Rate
21.11.1.1
Synchronization Segment
21.11.1.2
Propagation Time Segment
21.11.1.3
Phase Buffer Segments and Synchronization
21.11.1.4
Oscillator Tolerance Range
21.11.2
Configuration of the CAN Bit Timing
21.11.2.1
Calculation of the Bit Timing Parameters
21.11.2.2
Example for Bit Timing at High Baudrate
21.11.2.3
Example for Bit Timing at Low Baudrate
21.12
Message Interface Register Sets
21.12.1
Message Interface Register Sets 1 and 2 (IF1 and IF2)
21.12.2
Message Interface Register Set 3 (IF3)
21.13
Message RAM
21.13.1
Structure of Message Objects
21.13.2
Addressing Message Objects in RAM
21.13.3
Message RAM Representation in Debug Mode
21.14
Software
21.14.1
CAN Examples
21.15
CAN Registers
21.15.1
CAN Base Addresses
21.15.2
CAN_REGS Registers
21.15.3
CAN Registers to Driverlib Functions
22
Universal Serial Bus (USB) Controller
22.1
Introduction
22.1.1
Features
22.1.2
USB Related Collateral
22.1.3
Block Diagram
22.1.3.1
Signal Description
22.1.3.2
VBus Recommendations
22.2
Functional Description
22.2.1
Operation as a Device
22.2.1.1
Control and Configurable Endpoints
22.2.1.1.1
IN Transactions as a Device
22.2.1.1.2
Out Transactions as a Device
22.2.1.1.3
Scheduling
22.2.1.1.4
Additional Actions
22.2.1.1.5
Device Mode Suspend
22.2.1.1.6
Start of Frame
22.2.1.1.7
USB Reset
22.2.1.1.8
Connect/Disconnect
22.2.2
Operation as a Host
22.2.2.1
Endpoint Registers
22.2.2.2
IN Transactions as a Host
22.2.2.3
OUT Transactions as a Host
22.2.2.4
Transaction Scheduling
22.2.2.5
USB Hubs
22.2.2.6
Babble
22.2.2.7
Host SUSPEND
22.2.2.8
USB RESET
22.2.2.9
Connect/Disconnect
22.2.3
DMA Operation
22.2.4
Address/Data Bus Bridge
22.3
Initialization and Configuration
22.3.1
Pin Configuration
22.3.2
Endpoint Configuration
22.4
USB Global Interrupts
22.5
Software
22.5.1
USB Examples
22.6
USB Registers
22.6.1
USB Base Address
22.6.2
USB Register Map
22.6.3
Register Descriptions
22.6.3.1
USB Device Functional Address Register (USBFADDR), offset 0x000
22.6.3.2
USB Power Management Register (USBPOWER), offset 0x001
22.6.3.3
USB Transmit Interrupt Status Register
22.6.3.4
USB Receive Interrupt Status Register
22.6.3.5
USB Transmit Interrupt Enable Register
22.6.3.6
USB Receive Interrupt Enable Register
22.6.3.7
USB General Interrupt Status Register (USBIS), offset 0x00A
22.6.3.8
USB Interrupt Enable Register (USBIE), offset 0x00B
22.6.3.9
USB Frame Value Register (USBFRAME), offset 0x00C
22.6.3.10
USB Endpoint Index Register (USBEPIDX), offset 0x00E
22.6.3.11
USB Test Mode Register (USBTEST), offset 0x00F
22.6.3.12
USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[3])
22.6.3.13
USB Device Control Register (USBDEVCTL), offset 0x060
22.6.3.14
USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062
22.6.3.15
USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063
22.6.3.16
USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064
22.6.3.17
USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066
22.6.3.18
USB Connect Timing Register (USBCONTIM), offset 0x07A
22.6.3.19
USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset 0x07D
22.6.3.20
USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset 0x07E
22.6.3.21
USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-USBTXFUNCADDR[n])
22.6.3.22
USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-USBTXHUBADDR[n])
22.6.3.23
USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[n])
22.6.3.24
USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-USBRXFUNCADDR[n)
22.6.3.25
USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-USBRXHUBADDR[n])
22.6.3.26
USB Receive Hub Port Endpoint n Register (USBRXHUBPORT[1]-USBRXHUBPORT[n])
22.6.3.27
USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[n])
22.6.3.28
USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102
22.6.3.29
USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103
22.6.3.30
USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108
22.6.3.31
USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A
22.6.3.32
USB NAK Limit Register (USBNAKLMT), offset 0x10B
22.6.3.33
USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[n])
22.6.3.34
USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-USBTXCSRH[n])
22.6.3.35
USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[n])
22.6.3.36
USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-USBRXCSRL[n])
22.6.3.37
USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-USBRXCSRH[n])
22.6.3.38
USB Receive Byte Count Endpoint n Register (USBRXCOUNT[1]-USBRXCOUNT[n])
22.6.3.39
USB Host Transmit Configure Type Endpoint n Registers (USBTXTYPE[1]-USBTXTYPE[n])
22.6.3.40
USB Host Transmit Interval Endpoint n Registers (USBTXINTERVAL[1]-USBTXINTERVAL[n])
22.6.3.41
USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[n])
22.6.3.42
USB Host Receive Polling Interval Endpoint n Registers (USBRXINTERVAL[1]-USBRXINTERVAL[n])
22.6.3.43
USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-USBRQPKTCOUNT[n])
22.6.3.44
USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340
22.6.3.45
USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342
22.6.3.46
USB External Power Control Register (USBEPC), offset 0x400
22.6.3.47
USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404
22.6.3.48
USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408
22.6.3.49
USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C
22.6.3.50
USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410
22.6.3.51
USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414
22.6.3.52
USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418
22.6.3.53
USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C
22.6.3.54
USB DMA Select Register (USBDMASEL), offset 0x450
22.6.4
USB Registers to Driverlib Functions
23
External Memory Interface (EMIF)
23.1
Introduction
23.1.1
Purpose of the Peripheral
23.1.2
EMIF Related Collateral
23.1.3
Features
23.1.3.1
Asynchronous Memory Support
23.1.3.2
Synchronous DRAM Memory Support
23.1.4
Functional Block Diagram
23.1.5
Configuring Device Pins
23.2
EMIF Module Architecture
23.2.1
EMIF Clock Control
23.2.2
EMIF Requests
23.2.3
EMIF Signal Descriptions
23.2.4
EMIF Signal Multiplexing Control
23.2.5
SDRAM Controller and Interface
23.2.5.1
SDRAM Commands
23.2.5.2
Interfacing to SDRAM
23.2.5.3
SDRAM Configuration Registers
23.2.5.4
SDRAM Auto-Initialization Sequence
23.2.5.5
SDRAM Configuration Procedure
23.2.5.6
EMIF Refresh Controller
23.2.5.6.1
Determining the Appropriate Value for the RR Field
23.2.5.7
Self-Refresh Mode
23.2.5.8
Power-Down Mode
23.2.5.9
SDRAM Read Operation
23.2.5.10
SDRAM Write Operations
23.2.5.11
Mapping from Logical Address to EMIF Pins
23.2.6
Asynchronous Controller and Interface
23.2.6.1
Interfacing to Asynchronous Memory
23.2.6.2
Accessing Larger Asynchronous Memories
23.2.6.3
Configuring EMIF for Asynchronous Accesses
23.2.6.4
Read and Write Operations in Normal Mode
23.2.6.4.1
Asynchronous Read Operations (Normal Mode)
23.2.6.4.2
Asynchronous Write Operations (Normal Mode)
23.2.6.5
Read and Write Operation in Select Strobe Mode
23.2.6.5.1
Asynchronous Read Operations (Select Strobe Mode)
23.2.6.5.2
Asynchronous Write Operations (Select Strobe Mode)
23.2.6.6
Extended Wait Mode and the EM1WAIT Pin
23.2.7
Data Bus Parking
23.2.8
Reset and Initialization Considerations
23.2.9
Interrupt Support
23.2.9.1
Interrupt Events
23.2.10
DMA Event Support
23.2.11
EMIF Signal Multiplexing
23.2.12
Memory Map
23.2.13
Priority and Arbitration
23.2.14
System Considerations
23.2.14.1
Asynchronous Request Times
23.2.15
Power Management
23.2.15.1
Power Management Using Self-Refresh Mode
23.2.15.2
Power Management Using Power Down Mode
23.2.16
Emulation Considerations
23.3
Example Configuration
23.3.1
Hardware Interface
23.3.2
Software Configuration
23.3.2.1
Configuring the SDRAM Interface
23.3.2.1.1
PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
23.3.2.1.2
SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
23.3.2.1.3
SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
23.3.2.1.4
SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
23.3.2.1.5
SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
23.3.2.2
Configuring the Flash Interface
23.3.2.2.1
Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
23.4
EMIF Registers
23.4.1
EMIF Base Addresses
23.4.2
EMIF_REGS Registers
23.4.3
EMIF1_CONFIG_REGS Registers
23.4.4
EMIF2_CONFIG_REGS Registers
23.4.5
EMIF Registers to Driverlib Functions
24
Configurable Logic Block (CLB)
24.1
Introduction
24.1.1
CLB Related Collateral
24.2
Description
24.2.1
CLB Clock
24.3
CLB Input/Output Connection
24.3.1
Overview
24.3.2
CLB Input Selection
24.3.3
CLB Output Selection
24.3.4
CLB Output Signal Multiplexer
24.4
CLB Tile
24.4.1
Static Switch Block
24.4.2
Counter Block
24.4.2.1
Counter Description
24.4.2.2
Counter Operation
24.4.3
FSM Block
24.4.4
LUT4 Block
24.4.5
Output LUT Block
24.4.6
High Level Controller (HLC)
24.4.6.1
High Level Controller Events
24.4.6.2
High Level Controller Instructions
24.4.6.3
<Src> and <Dest>
24.4.6.4
Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
24.5
CPU Interface
24.5.1
Register Description
24.5.2
Non-Memory Mapped Registers
24.6
DMA Access
24.7
Software
24.7.1
CLB Examples
24.7.1.1
CLB Empty Project
24.7.1.2
CLB Combinational Logic
24.7.1.3
CLB GPIO Input Filter
24.7.1.4
CLB Auxilary PWM
24.7.1.5
CLB PWM Protection
24.7.1.6
CLB Event Window
24.7.1.7
CLB Signal Generator
24.7.1.8
CLB State Machine
24.7.1.9
CLB External Signal AND Gate
24.7.1.10
CLB Timer
24.7.1.11
CLB Timer Two States
24.7.1.12
CLB Interrupt Tag
24.7.1.13
CLB Output Intersect
24.7.1.14
CLB PUSH PULL
24.7.1.15
CLB Multi Tile
24.7.1.16
CLB Tile to Tile Delay
24.7.1.17
CLB based One-shot PWM
24.7.1.18
CLB Trip Zone Timestamp
24.8
CLB Registers
24.8.1
CLB Base Addresses
24.8.2
CLB_LOGIC_CONFIG_REGS Registers
24.8.3
CLB_LOGIC_CONTROL_REGS Registers
24.8.4
CLB_DATA_EXCHANGE_REGS Registers
24.8.5
CLB Registers to Driverlib Functions
25
Revision History
14.31.27
Register to Driverlib Function Mapping