SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
The USB receive control and status endpoint n high 8-bit register (USBRXCSRL[n]) provides additional control and status bits for transfers through the currently selected receive endpoint.
Mode(s): | Host | Device |
The USBCSRH[n] registers in OTG A/Host mode are shown in Figure 22-48 and described in Table 22-50.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUTOCL | AUTORQ | DMAEN | Reserved | DMAMOD | DTWE | DT | Reserved |
W1C-0 | R/W-0 | R/W-0 | R-0 | R/W-0 | R-0 | R-0 | R-0 |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Value | Description |
---|---|---|---|
7 | AUTOCL | Auto Clear | |
0 | No effect | ||
1 | Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using DMA to unload the receive FIFO as data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXP[n] register, see Section 22.2.3. | ||
6 | AUTORQ | Auto Request Note: This bit is automatically cleared when a short packet is received. | |
0 | No effect | ||
1 | Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared. | ||
5 | DMAEN | DMA Request Enable Note: Three TX and three RX endpoints can be connected to the DMA module. If this bit is set for a particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. | |
0 | Disables the DMA request for the receive endpoint. | ||
1 | Enables the DMA request for the receive endpoint. | ||
4 | Reserved | Reserved | |
3 | DMAMOD | DMAMOD Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. | |
0 | An interrupt is generated after every DMA packet transfer. | ||
1 | An interrupt is generated only after the entire DMA transfer is complete. | ||
2 | DTWE | Data Toggle Write Enable. This bit is automatically cleared once the new value is written. | |
0 | The DT bit cannot be written. | ||
1 | Enables the current state of the receive endpoint data to be written (see DT bit). | ||
1 | DT | Data Toggle. When read, this bit indicates the current state of the receive data toggle. If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any value written to this bit is ignored. Care should be taken when writing to this bit as it should only be changed to RESET the receive endpoint. | |
0 | Reserved | 0 | Reserved |
The USBCSRH[n] registers in Device mode are shown in Figure 22-49 and described in Table 22-51.
7 | 6 | 5 | 4 | 3 | 2 | 0 |
AUTOCL | Reserved | DMAEN | DISNYET / PIDERR | DMAMOD | Reserved |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R-0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Value | Description |
---|---|---|---|
7 | AUTOCL | Auto Clear | |
0 | No effect | ||
1 | Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded, RXRDY must be cleared manually. Care must be taken when using DMA to unload the receive FIFO as data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXP[n] register, see Section 22.2.3. | ||
6 | Reserved | Reserved | |
5 | DMAEN | DMA Request Enable Note: Three TX and three RX endpoints can be connected to the DMA module. If this bit is set for a particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL) register must be programmed correspondingly. | |
0 | Disables the DMA request for the receive endpoint. | ||
1 | Enables the DMA request for the receive endpoint. | ||
4 | DISNYET/PIDERR | Disable NYET / PID Error | |
0 | No effect | ||
1 | For bulk or interrupt transactions: Disables the sending of NYET handshakes. When this bit is set, all successfully received packets are acknowledged, including at the point at which the FIFO becomes full. | ||
3 | DMAMOD | DMA Request Mode Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is cleared. | |
0 | An interrupt is generated after every DMA packet transfer. | ||
1 | An interrupt is generated only after the entire DMA transfer is complete. | ||
0 | Reserved | 0 | Reserved |