SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
(USBRXIS), offset 0x004
Use caution when reading this register. Performing a read may change bit status.
The USB receive interrupt status 16-bit read-only register (USBRXIS) indicates which interrupts are currently active for receive endpoints 1–15.
Note: The USBRXIS register does not have a bit for EP0. See the USBTXIS register for EP0 use.
Note: Bits relating to endpoints that have not been configured always return 0. All active interrupts are cleared when this register is read.
Mode(s): | Host | Device |
USBRXIS is shown in Figure 22-7 and described in Table 22-9.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EP15 | EP14 | EP13 | EP12 | EP11 | EP10 | EP9 | EP8 |
R-0 | |||||||
EP7 | EP6 | EP5 | EP4 | EP3 | EP2 | EP1 | EP0 |
R-0 | Reserved | ||||||
Bit | Field | Value | Description |
---|---|---|---|
15 | EP15 | RX Endpoint 15 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 15 receive interrupt is asserted. | ||
14 | EP14 | RX Endpoint 14 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 14 receive interrupt is asserted. | ||
13 | EP13 | RX Endpoint 13 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 13 receive interrupt is asserted. | ||
12 | EP12 | RX Endpoint 12 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 12 receive interrupt is asserted. | ||
11 | EP11 | RX Endpoint 11 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 11 receive interrupt is asserted. | ||
10 | EP10 | RX Endpoint 10 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 10 receive interrupt is asserted. | ||
9 | EP9 | RX Endpoint 9 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 9 receive interrupt is asserted. | ||
8 | EP8 | RX Endpoint 8 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 8 receive interrupt is asserted. | ||
7 | EP7 | RX Endpoint 7 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 7 receive interrupt is asserted. | ||
6 | EP6 | RX Endpoint 6 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 6 receive interrupt is asserted. | ||
5 | EP5 | RX Endpoint 5 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 5 receive interrupt is asserted. | ||
4 | EP4 | RX Endpoint 4 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 4 receive interrupt is asserted. | ||
3 | EP3 | RX Endpoint 3 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 3 receive interrupt is asserted. | ||
2 | EP2 | RX Endpoint 2 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 2 receive interrupt is asserted. | ||
1 | EP1 | RX Endpoint 1 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 1 receive interrupt is asserted. | ||
0 | Reserved | Reserved |