SPRUI30H November 2015 – May 2024 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4809 C000 0x480B 4000 0x480A D000 0x480D 1000 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | REVISION | IP Revision | R | TI internal data |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4809 C004 0x480B 4004 0x480A D004 0x480D 1004 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Information about the IP module's hardware configuration. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RETMODE | MEM_SIZE | MERGE_MEM | MADMA_EN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:7 | RESERVED | R | 0x- | |
6 | RETMODE | Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET. | R | 0x- |
Read 0x1: Retention mode enabled | ||||
Read 0x0: Retention mode disabled | ||||
5:2 | MEM_SIZE | Memory size for FIFO buffer: | R | 0x- |
Read 0x2: Memory of 1024 bytes, max block length is 1024 bytes | ||||
Read 0x1: Memory of 512 bytes, max block length is 512 bytes | ||||
Read 0x8: Memory of 4096 bytes, max block length is 2048 bytes | ||||
Read 0x4: Memory of 2048 bytes, max block length is 2048 bytes | ||||
1 | MERGE_MEM | Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing. | R | 0x- |
Read 0x1: A single memory is used with multiplexed addresses, data and clocks. | ||||
Read 0x0: 2 memories instantiated, one per data transfer direction. | ||||
0 | MADMA_EN | Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA. | R | 0x- |
Read 0x1: Controller supports ADMA | ||||
Read 0x0: No Master DMA (ADMA) management supported |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4809 C010 0x480B 4010 0x480A D010 0x480D 1010 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Clock Management Configuration Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STANDBYMODE | IDLEMODE | FREEEMU | SOFTRESET |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:6 | RESERVED | R | 0x000 0000 | |
5:4 | STANDBYMODE | Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state. | RW | 0x2 |
0x0: Force-standby mode: local initiator is unconditionally placed in standby state.Backup mode, for debug only. | ||||
0x1: No-standby mode: local initiator is unconditionally placed out of standby state.Backup mode, for debug only. | ||||
0x3: Smart-Standby wakeup-capable mode: local initiator standby status depends on local conditions, i.e. the module's functional requirement from the initiator. IP module may generate (master-related) wakeup events when in standby state.Mode is only relevant if the appropriate IP module "mwakeup" output is implemented. | ||||
0x2: Smart-standby mode: local initiator standby status depends on local conditions, i.e. the module's functional requirement from the initiator.IP module shall not generate (initiator-related) wakeup events. | ||||
3:2 | IDLEMODE | Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. | RW | 0x2 |
0x0: Force-idle mode: local target's idle state follows (acknowledges) the system's IDLE requests unconditionally, i.e. regardless of the IP module's internal requirements.Backup mode, for debug only. | ||||
0x1: No-idle mode: local target never enters idle state.Backup mode, for debug only. | ||||
0x3: Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's IDLE requests, depending on the IP module's internal requirements.IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state.Mode is only relevant if the appropriate IP module "swakeup" output(s) is (are) implemented. | ||||
0x2: Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's IDLE requests, depending on the IP module's internal requirements.IP module shall not generate (IRQ- or DMA-request-related) wakeup events. | ||||
1 | FREEEMU | Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS. | RW | 0 |
0x0: IP module is sensitive to emulation suspend | ||||
0x1: IP module is not sensitive to emulation suspend | ||||
0 | SOFTRESET | Software reset. (Optional) | RW | 0 |
Write 0x0: No action | ||||
Write 0x1: Initiate software reset | ||||
Read 0x1: Reset (software or other) ongoing | ||||
Read 0x0: Reset done, no pending action |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4809 C110 0x480B 4110 0x480A D110 0x480D 1110 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | System Configuration Register This register allows controlling various parameters of the Interconnect interface. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STANDBYMODE | RESERVED | CLOCKACTIVITY | RESERVED | SIDLEMODE | ENAWAKEUP | SOFTRESET | AUTOIDLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:14 | RESERVED | R | 0x0 0000 | |
13:12 | STANDBYMODE | Master interface power
Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a '0'. | RW | 0x2 |
0x0: Force-standby. Mstandby is forced unconditionnaly. | ||||
0x1: No-standby. Mstandby is never asserted. | ||||
0x2: Smart-standby mode: local initiator standby status depends on local conditions, i.e. the module's functional requirement from the initiator.IP module shall not generate (initiator-related) wakeup events. | ||||
11:10 | RESERVED | R | 0x0 | |
9:8 | CLOCKACTIVITY | Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock | RW | 0x0 |
0x0: Interface and Functional clock may be switched off. | ||||
0x1: Interface clock is maintained. Functional clock may be switched-off. | ||||
0x3: Interface and Functional clocks are maintained. | ||||
0x2: Functional clock is maintained. Interface clock may be switched-off. | ||||
7:5 | RESERVED | This bit is initialized to zero, and writes to it are ignored. Reads return 0. | R | 0x0 |
4:3 | SIDLEMODE | Power management | RW | 0x2 |
0x0: If an IDLE request is detected, the MMCHS acknowledges it unconditionally and goes in Inactive mode. Interrupt and DMA requests are unconditionally de-asserted. | ||||
0x1: If an IDLE request is detected, the request is ignored and the module keeps on behaving normally. | ||||
0x3: Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's IDLE requests, depending on the IP module's internal requirements.IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state.Mode is only relevant if the appropriate IP module "swakeup" output(s) is (are) implemented. | ||||
0x2: Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's IDLE requests, depending on the IP module's internal requirements.IP module shall not generate (IRQ- or DMA-request-related) wakeup events. | ||||
2 | ENAWAKEUP | Wakeup feature control | RW | 1 |
0x0: Wakeup capability is disabled | ||||
0x1: Wakeup capability is enabled | ||||
1 | SOFTRESET | Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0. | RW | 0 |
Write 0x0: No effect. | ||||
Write 0x1: Trigger a module reset. | ||||
Read 0x1: The module is reset. | ||||
Read 0x0: Normal mode | ||||
0 | AUTOIDLE | Internal Clock gating strategy | RW | 1 |
0x0: Clocks are free-running | ||||
0x1: Automatic clock gating strategy is applied, based on the Interconnect and MMC interface activity |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4809 C114 0x480B 4114 0x480A D114 0x480D 1114 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | System Status Register This register provides status information about the module excluding the interrupt status information | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETDONE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:1 | RESERVED | R | 0x0000 0000 | |
0 | RESETDONE | Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring. | R | 0 |
Read 0x1: Reset completed. | ||||
Read 0x0: Internal module reset is on-going |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x4809 C124 0x480B 4124 0x480A D124 0x480D 1124 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Card Status Response
Error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit MMCHS_CSRE[i] is set to 1, if the corresponding bit at the same position in the response MMCHS_RSP0[i] is set to 1, the host controller indicates a card error (MMCHS_STAT[CERR]) interrupt status to avoid the host driver reading the response register (MMCHS_RSP0). Note: No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (MMCHS_RESP76) for possible card errors. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CSRE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | CSRE | Card status response error | RW | 0x0000 0000 |
Address Offset | 0x0000 0128 | ||
Physical Address | 0x4809 C128 0x480B 4128 0x480A D128 0x480D 1128 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | System Test
Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into MMCHS_CMD register will not start a transfer. The buffer behaves as a stack accessible only by the local host (push and pop operations). In this mode, the Transfer Block Size (MMCHS_BLK[BLEN]) and the Blocks count for current transfer (MMCHS_BLK[NBLK]) are needed to generate a Buffer write ready interrupt (MMCHS_STAT[BWR]) or a Buffer read ready interrupt (MMCHS_STAT[BRR]) and DMA requests if enabled. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OBI | SDCD | SDWP | WAKD | SSB | D7D | D6D | D5D | D4D | D3D | D2D | D1D | D0D | DDIR | CDAT | CDIR | MCKD |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:17 | RESERVED | R | 0x0000 | |
16 | OBI | Out-Of-Band Interrupt (OBI) data value | R | 0 |
Read 0x1: The Out-of-Band Interrupt pin is driven high. | ||||
Read 0x0: The Out-of-Band Interrupt pin is driven low. | ||||
15 | SDCD | Card detect input signal (mmci_sdcd) data value | R | 0 |
Read 0x1: The card detect pin is driven high. | ||||
Read 0x0: The card detect pin is driven low. | ||||
14 | SDWP | Write protect input signal (mmci_sdwp) data value | R | 0 |
Read 0x1: The write protect pin mmci_sdwp is driven high. | ||||
Read 0x0: The write protect pin mmci_sdwp is driven low. | ||||
13 | WAKD | Wake request output signal data value | RW | 0 |
Write 0x0: The pin SWAKEUP is driven low. | ||||
Write 0x1: The pin SWAKEUP is driven high. | ||||
Read 0x1: No action. Returns 1. | ||||
Read 0x0: No action. Returns 0. | ||||
12 | SSB | Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT). | RW | 0 |
Write 0x0: Clear this SSB bitfield. Writing 0 does not clear already set status bits; | ||||
Write 0x1: Force to 1 all status bits of the interrupt status register (MMCHS_STAT) only if the corresponding bitfield in the Interrupt signal enable register (MMCHS_ISE) is set. | ||||
Read 0x1: No action. Returns 1. | ||||
Read 0x0: No action. Returns 0. | ||||
11 | D7D | DAT7 input/output signal data value | RW | 0 |
Write 0x0: If SYSTEST[DDIR] = 0 (output mode direction), the DAT7 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Write 0x1: If SYSTEST[DDIR] = 0 (output mode direction), the DAT7 line is driven high. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Read 0x1: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT7 line (high) If SYSTEST[DDIR] = 0 (output mode direction), returns 1 | ||||
Read 0x0: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT7 line (low). If SYSTEST[DDIR] = 0 (output mode direction), returns 0 | ||||
10 | D6D | DAT6 input/output signal data value | RW | 0 |
Write 0x0: If SYSTEST[DDIR] = 0 (output mode direction), the DAT6 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Write 0x1: If SYSTEST[DDIR] = 0 (output mode direction), the DAT6 line is driven high. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Read 0x1: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT6 line (high) If SYSTEST[DDIR] = 0 (output mode direction), returns 1 | ||||
Read 0x0: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT6 line (low). If SYSTEST[DDIR] = 0 (output mode direction), returns 0 | ||||
9 | D5D | DAT5 input/output signal data value | RW | 0 |
Write 0x0: If SYSTEST[DDIR] = 0 (output mode direction), the DAT5 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Write 0x1: If SYSTEST[DDIR] = 0 (output mode direction), the DAT5 line is driven high. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Read 0x1: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT5 line (high) If SYSTEST[DDIR] = 0 (output mode direction), returns 1 | ||||
Read 0x0: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT5 line (low). If SYSTEST[DDIR] = 0 (output mode direction), returns 0 | ||||
8 | D4D | DAT4 input/output signal data value | RW | 0 |
Write 0x0: If SYSTEST[DDIR] = 0 (output mode direction), the DAT4 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Write 0x1: If SYSTEST[DDIR] = 0 (output mode direction), the DAT4 line is driven high. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Read 0x1: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT4 line (high) If SYSTEST[DDIR] = 0 (output mode direction), returns 1 | ||||
Read 0x0: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT4 line (low). If SYSTEST[DDIR] = 0 (output mode direction), returns 0 | ||||
7 | D3D | DAT3 input/output signal data value | RW | 0 |
Write 0x0: If SYSTEST[DDIR] = 0 (output mode direction), the DAT3 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Write 0x1: If SYSTEST[DDIR] = 0 (output mode direction), the DAT3 line is driven high. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Read 0x1: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT3 line (high) If SYSTEST[DDIR] = 0 (output mode direction), returns 1 | ||||
Read 0x0: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT3 line (low). If SYSTEST[DDIR] = 0 (output mode direction), returns 0 | ||||
6 | D2D | DAT2 input/output signal data value | RW | 0 |
Write 0x0: If SYSTEST[DDIR] = 0 (output mode direction), the DAT2 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Write 0x1: If SYSTEST[DDIR] = 0 (output mode direction), the DAT2 line is driven high. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Read 0x1: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT2 line (high) If SYSTEST[DDIR] = 0 (output mode direction), returns 1 | ||||
Read 0x0: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT2 line (low). If SYSTEST[DDIR] = 0 (output mode direction), returns 0 | ||||
5 | D1D | DAT1 input/output signal data value | RW | 0 |
Write 0x0: If SYSTEST[DDIR] = 0 (output mode direction), the DAT1 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Write 0x1: If SYSTEST[DDIR] = 0 (output mode direction), the DAT1 line is driven high. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Read 0x1: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT1 line (high) If SYSTEST[DDIR] = 0 (output mode direction), returns 1 | ||||
Read 0x0: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT1 line (low). If SYSTEST[DDIR] = 0 (output mode direction), returns 0 | ||||
4 | D0D | DAT0 input/output signal data value | RW | 0 |
Write 0x0: If SYSTEST[DDIR] = 0 (output mode direction), the DAT0 line is driven low. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Write 0x1: If SYSTEST[DDIR] = 0 (output mode direction), the DAT0 line is driven high. If SYSTEST[DDIR] = 1 (input mode direction), no effect. | ||||
Read 0x1: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT0 line (high) If SYSTEST[DDIR] = 0 (output mode direction), returns 1 | ||||
Read 0x0: If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT0 line (low). If SYSTEST[DDIR] = 0 (output mode direction), returns 0 | ||||
3 | DDIR | Control of the DAT[7:0] pins direction. | RW | 0 |
Write 0x0: The DAT lines are outputs (host to card) | ||||
Write 0x1: The DAT lines are inputs (card to host) | ||||
Read 0x1: No action. Returns 1. | ||||
Read 0x0: No action. Returns 0. | ||||
2 | CDAT | CMD input/output signal data value | RW | 0 |
Write 0x0: If SYSTEST[CDIR] = 0 (output mode direction), the CMD line is driven low. If SYSTEST[CDIR] = 1 (input mode direction), no effect. | ||||
Write 0x1: If SYSTEST[CDIR] = 0 (output mode direction), the CMD line is driven high. If SYSTEST[CDIR] = 1 (input mode direction), no effect. | ||||
Read 0x1: If SYSTEST[CDIR] = 1 (input mode direction), returns the value on the CMD line (high) If SYSTEST[CDIR] = 0 (output mode direction), returns 1 | ||||
Read 0x0: If SYSTEST[CDIR] = 1 (input mode direction), returns the value on the CMD line (low). If SYSTEST[CDIR] = 0 (output mode direction), returns 0 | ||||
1 | CDIR | Control of the CMD pin direction. | RW | 0 |
Write 0x0: The CMD line is an output (host to card) | ||||
Write 0x1: The CMD line is an input (card to host) | ||||
Read 0x1: No action. Returns 1. | ||||
Read 0x0: No action. Returns 0. | ||||
0 | MCKD | MMC clock output signal data value | RW | 0 |
Write 0x0: The output clock is driven low. | ||||
Write 0x1: The output clock is driven high. | ||||
Read 0x1: No action. Returns 1. | ||||
Read 0x0: No action. Returns 0. |
Address Offset | 0x0000 012C | ||
Physical Address | 0x4809 C12C 0x480B 412C 0x480A D12C 0x480D 112C | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and also to configure : - specific data and command transfers for MMC cards only. - the parameters related to the card detect and write protect input signals. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDMA_LNE | DMA_MNS | DDR | BOOT_CF0 | BOOT_ACK | CLKEXTFREE | PADEN | OBIE | OBIP | CEATA | CTPL | DVAL | WPP | CDP | MIT | DW8 | MODE | STR | HR | INIT | OD |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:22 | RESERVED | R | 0x000 | |
21 | SDMA_LNE | Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data written into MMCHS_DATA. | RW | 0 |
0x0: Slave DMA edge sensitive, Early DMA de-assertion | ||||
0x1: Slave DMA level sensitive, Late DMA de-assertion | ||||
20 | DMA_MNS | DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available if generic parameter MADMA_EN is asserted to '1'. | RW | 0 |
0x0: The controller is slave on data transfers with system. | ||||
0x1: The controller is master on data exchange with system, controller must be configured as using DMA. | ||||
19 | DDR | Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Data bytes and CRC, Start, end bits and CRC status are kept full cycle. This bit field is only meaningful and active for even clock divider ratio of MMCHS_SYSCTL[CLKD], it is insensitive to MMCHS_HCTL[HSPE] setting. | RW | 0 |
0x0: Standard mode : data are transmitted on a single edge depending on MMCHS_HCTRL[HSPE]. | ||||
0x1: Data Bytes and CRC are transmitted on both edge. | ||||
18 | BOOT_CF0 | Boot status supported: This register is set when the CMD line need to be forced to '0' for a boot sequence. CMD line is driven to '0' after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer in case of a pending transaction. | RW | 0 |
Write 0x0: CMD line is released when it was previously forced to '0' by a boot sequence. | ||||
Write 0x1: CMD line forced to '0' is enabled and will be active after writing into MMCHS_CMD | ||||
Read 0x1: CMD line forced to '0' is enabled | ||||
Read 0x0: CMD line not forced | ||||
17 | BOOT_ACK | Boot acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated. | RW | 0 |
0x0: No acknowledge to be received | ||||
0x1: A boot status will be received on DAT0 line after issuing a command. | ||||
16 | CLKEXTFREE | External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only if MMCHS_SYSCTL[CEN] is set. | RW | 0 |
0x0: External card clock is cut off outside active transaction period. | ||||
0x1: External card clock is maintain even out of active transaction period only if MMCHS_SYSCTL[CEN] is set. | ||||
15 | PADEN | Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also combine outside the module with the dedicated power control MMCHS_CON[CTPL] bit. | RW | 0 |
0x0: ADPIDLE module pin is not forced, it is automatically generated by the MMC fsms. | ||||
0x1: ADPIDLE module pin is forced to active state. | ||||
14 | OBIE | Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration. | RW | 0 |
0x0: Out-of-Band interrupt detection disabled | ||||
0x1: Out-of-Band interrupt detection enabled | ||||
13 | OBIP | Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration. | RW | 0 |
0x0: Active high level | ||||
0x1: Active low level | ||||
12 | CEATA | CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is used to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features. | RW | 0 |
0x0: Standard MMC/SD/SDIO mode. | ||||
0x1: CE-ATA mode next commands are considered as CE-ATA commands. | ||||
11 | CTPL | Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards: When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of DAT[1] outside of a transaction in order to detect asynchronous card interrupt on DAT[1] line and minimize the leakage current of the buffers. | RW | 0 |
0x0: Disable all the input buffers outside of a transaction. | ||||
0x1: Disable all the input buffers except the buffer of DAT[1] outside of a transaction. | ||||
10:9 | DVAL | Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card. | RW | 0x3 |
0x0: 33 us debounce period | ||||
0x1: 231 us debounce period | ||||
0x3: 8,4 ms debounce period | ||||
0x2: 1 ms debounce period | ||||
8 | WPP | Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (mmci_sdwp). The usage of the write protect input signal (mmci_sdwp) is optional and depends on the system integration and the type of the connector housing that accommodates the card. | RW | 0 |
0x0: Active high level | ||||
0x1: Active low level | ||||
7 | CDP | Card detect polarity All cards This bit selects the active level of the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card. | RW | 0 |
0x0: Active low level | ||||
0x1: Active high level | ||||
6 | MIT | MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detection to be disabled for the command response. | RW | 0 |
0x0: Command timeout enabled | ||||
0x1: Command timeout disabled | ||||
5 | DW8 | 8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliancy with MMC standard specification 4.x (see section 3.6). | RW | 0 |
0x0: 1-bit or 4-bit Data width (DAT[0] used, MMC, SD cards) | ||||
0x1: 8-bit Data width (DAT[7:0] used, MMC cards) | ||||
4 | MODE | Mode select All cards This bit select between Functional mode and SYSTEST mode. | RW | 0 |
0x0: Functional mode. Transfers to the MMC/SD/SDIO cards follow the card protocol. MMC clock is enabled. MMC/SD transfers are operated under the control of the CMD register. | ||||
0x1: SYSTEST mode The signal pins are configured as general-purpose input/output and the 1024-byte buffer is configured as a stack memory accessible only by the local host or system DMA. The pins retain their default type (input, output or in-out). SYSTEST mode is operated under the control of the SYSTEST register. | ||||
3 | STR | Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a class 3 command (CMD20: WRITE_DAT_UNTIL_STOP). | RW | 0 |
0x0: Block oriented data transfer | ||||
0x1: Stream oriented data transfer | ||||
2 | HR | Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section 4.3, "Interrupt Mode", in the MMC specification). In order to have the host response to be generated in open drain mode, the register MMCHS_CON[OD] must be set to 1. When MMCHS_CON[CEATA] is set to 1 and MMCHS_ARG set to 0x00000000 when writing 0x00000000 into MMCHS_CMD register, the host controller performs a 'command completion signal disable' token i.e. CMD line held to '0' during 47 cycles followed by a 1. | RW | 0 |
0x0: The host does not generate a 48-bit response instead of a command. | ||||
0x1: The host generates a 48-bit response instead of a command or a command completion signal disable token. | ||||
1 | INIT | Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock cycles. The initialisation sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider (MMCHS_SYSCTL[CLKD]) should be set to ensure that 80 clock periods are greater than 1ms. (see section 9.3, "Power-Up", in the MMC card specification, or section 6.4 in the SD card specification). Note: in this mode, there is no command sent to the card and no response is expected | RW | 0 |
0x0: The host does not send an initialization sequence. | ||||
0x1: The host sends an initialization sequence. | ||||
0 | OD | Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response (see Broadcast host response register MMCHS_CON[HR]) | RW | 0 |
0x0: No Open Drain | ||||
0x1: Open Drain or Broadcast host response |
Address Offset | 0x0000 0130 | ||
Physical Address | 0x4809 C130 0x480B 4130 0x480A D130 0x480D 1130 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Power Counter Register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRCNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RESERVED | R | 0x0000 | |
15:0 | PWRCNT | Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued. | RW | 0x0000 |
0xFFFF: TCF x 65535 delay (card clock period) | ||||
0x0: No additional delay added | ||||
0x1: TCF delay (card clock period) | ||||
0xFFFE: TCF x 65534 delay (card clock period) | ||||
0x2: TCF x 2 delay (card clock period) |
Address Offset | 0x0000 0134 | ||
Physical Address | 0x4809 C134 0x480B 4134 | Instance | MMC1 MMC2 |
Description | DLL control and status register This register is used for tuning procedure required for SDR104/HS200 speed mode. It gives visibility and control on the DLL | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLL_SOFT_RESET | LOCK_TIMER | MAX_LOCK_DIFF | FORCE_SR_F | SWT | FORCE_SR_C | FORCE_VALUE | SLAVE_RATIO | RESERVED | DLL_UNLOCK_CLEAR | DLL_UNLOCK_STICKY | DLL_CALIB | DLL_LOCK |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | DLL_SOFT_RESET | Soft reset for DLL, active HIGH. | RW | 1 |
Write 0x0: No action. | ||||
Write 0x1: Issue soft reset | ||||
Read 0x1: Reset is in progress | ||||
Read 0x0: Reset completed. | ||||
30 | LOCK_TIMER | Timer for the dll_lock signal to be asserted after reset. | RW | 0 |
0x0: 1024 cycles (equivalent to DLL fast mode lock) | ||||
0x1: 66560 cycles | ||||
29:22 | MAX_LOCK_DIFF | Maximum number of taps that the master DLL clock period measurement can deviate without resulting in the master DLL losing lock. | RW | 0x00 |
21 | FORCE_SR_F | Forced fine delay value. | RW | 0x0 |
20 | SWT | Software Tuning enable. The bit shall be set to manage the tuning sequence fully in software. NOTE: For proper operation when SDR104/HS200 mode is used this bit must be set to 0x1 which disables the Conflict Error (CFT Error) on the CMD line. 0x0: No software tuning sequence. 0x1: Execute software tuning sequence. | RW | 0x0 |
19:13 | FORCE_SR_C | Forced coarse delay value | RW | 0x00 |
12 | FORCE_VALUE | Put forced values to slave DLL, ignoring master DLL output and ratio value. | RW | 0 |
0x0: Do not put force value | ||||
0x1: Put force value. | ||||
11:6 | SLAVE_RATIO | Fraction of a clock cycle for the shift to be implemented, in units of 256ths of a clock cycle. | RW | 0x00 |
0x6: 135 degrees delay | ||||
0x3F: 4 clocks delay | ||||
0x8: 180 degrees delay | ||||
0x2: 45 degrees delay | ||||
0xA: 225 degrees delay | ||||
0x10: Full clock delay | ||||
0x0: 0 degree delay | ||||
0xC: 270 degrees delay | ||||
0x4: 90 degrees delay | ||||
0xE: 315 degrees delay | ||||
5:4 | RESERVED | R | 0x0 | |
3 | DLL_UNLOCK_CLEAR | Clears the phy_reg_status_mdll_unlock_sticky flags of the DLL. | RW | 0 |
0x0: No effect. | ||||
0x1: Clears the flag. | ||||
2 | DLL_UNLOCK_STICKY | Asserted when any single period measurement exceeds MAX_LOCK_DIFF. | R | 0 |
1 | DLL_CALIB | Enables Slave DLL to update new delay values. | RW | 0 |
0x0: Disabled | ||||
0x1: Enabled | ||||
0 | DLL_LOCK | Master DLL lock status. | R | 0 |
Read 0x1: DLL is locked | ||||
Read 0x0: DLL is not locked |
Address Offset | 0x0000 0200 | ||
Physical Address | 0x4809 C200 0x480B 4200 0x480A D200 0x480D 1200 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | SDMA System Address / Argument 2 Register | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SDMA_ARG2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | SDMA_ARG2 | SDMA System Address / Argument 2 This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. (1) SDMA System Address This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (003h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register. (2) Argument 2 This register is used with the Auto CMD23 to set a 32-bit block count value to the argument of the CMD23 while executing Auto CMD23. If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If Auto CMD23 is used without AMDA, the available block count value is limited by the Block Count register. 65535 blocks is the maximum value in this case. | RW | 0x0000 0000 |
Address Offset | 0x0000 0204 | ||
Physical Address | 0x4809 C204 0x480B 4204 0x480A D204 0x480D 1204 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Transfer Length
Configuration Register MMCHS_BLK[BLEN] is the block size register. MMCHS_BLK[NBLK] is the block count register. This register shall be used for any card. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NBLK | RESERVED | BLEN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | NBLK | Blocks count for current
transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (i.e, after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. In suspend context, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, The local host shall restore the previously saved block count. | RW | 0x0000 |
0xFFFF: 65535 blocks | ||||
0x0: Stop count | ||||
0x1: 1 block | ||||
0x2: 2 blocks | ||||
15:12 | RESERVED | R | 0x0 | |
11:0 | BLEN | Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issued to stop the transfer, a read of the BLEN field after transfer completion (MMCHS_STAT[TC] set to 1) will not return the true byte number of data length while the stop occurs but the value written in this register before transfer is launched. | RW | 0x000 |
0x1: 1 byte block length | ||||
0x7FF: 2047 bytes block length | ||||
0x0: No data transfer | ||||
0x1FF: 511 bytes block length | ||||
0x800: 2048 bytes block length | ||||
0x2: 2 bytes block length | ||||
0x3: 3 bytes block length | ||||
0x200: 512 bytes block length |
Address Offset | 0x0000 0208 | ||
Physical Address | 0x4809 C208 0x480B 4208 0x480A D208 0x480D 1208 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Command Argument
Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register MMCHS_CMD register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARG |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ARG | Command argument bits [31:0] | RW | 0x0000 0000 |
Address Offset | 0x0000 020C | ||
Physical Address | 0x4809 C20C 0x480B 420C 0x480A D20C 0x480D 120C | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Command and Transfer
Mode Register MMCHS_CMD[31:16] = the command register MMCHS_CMD[15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into MMCHS_CMD[15:0] registers during data transfer has no effect. This register shall be used for any card. Note: In SYSTEST mode, a write into MMCHS_CMD register will not start a transfer. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INDX | CMD_TYPE | DP | CICE | CCCE | RESERVED | RSP_TYPE | RESERVED | MSBS | DDIR | ACEN | BCE | DE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | R | 0x0 | |
29:24 | INDX | Command index | RW | 0x00 |
Binary encoded value from 0 to 63 specifying the command number send to card | ||||
0xD: CMD13 or ACMD13 | ||||
0x33: CMD51 or ACMD51 | ||||
0x3B: CMD59 or ACMD59 | ||||
0x15: CMD21 or ACMD21 | ||||
0x1E: CMD30 or ACMD30 | ||||
0x8: CMD8 or ACMD8 | ||||
0x5: CMD5 or ACMD5 | ||||
0x2E: CMD46 or ACMD46 | ||||
0x1B: CMD27 or ACMD27 | ||||
0x2C: CMD44 or ACMD44 | ||||
0x36: CMD54 or ACMD54 | ||||
0x2: CMD2 or ACMD2 | ||||
0x3E: CMD62 or ACMD62 | ||||
0x4: CMD4 or ACMD4 | ||||
0x39: CMD57 or ACMD57 | ||||
0x32: CMD50 or ACMD50 | ||||
0x6: CMD6 or ACMD6 | ||||
0x1: CMD1 or ACMD1 | ||||
0x1D: CMD29 or ACMD29 | ||||
0x3F: CMD63 or ACMD63 | ||||
0x28: CMD40 or ACMD40 | ||||
0x3A: CMD58 or ACMD58 | ||||
0x24: CMD36 or ACMD36 | ||||
0x0: CMD0 or ACMD0 | ||||
0x2D: CMD45 or ACMD45 | ||||
0x38: CMD56 or ACMD56 | ||||
0x3C: CMD60 or ACMD60 | ||||
0xB: CMD11 or ACMD11 | ||||
0x3D: CMD61 or ACMD61 | ||||
0x20: CMD32 or ACMD32 | ||||
0x3: CMD3 or ACMD3 | ||||
0x17: CMD23 or ACMD23 | ||||
0x30: CMD48 or ACMD48 | ||||
0x31: CMD49 or ACMD49 | ||||
0x11: CMD17 or ACMD17 | ||||
0x23: CMD35 or ACMD35 | ||||
0x35: CMD53 or ACMD53 | ||||
0x2F: CMD47 or ACMD47 | ||||
0xA: CMD10 or ACMD10 | ||||
0x9: CMD9 or ACMD9 | ||||
0x10: CMD16 or ACMD16 | ||||
0x26: CMD38 or ACMD38 | ||||
0x21: CMD33 or ACMD33 | ||||
0x25: CMD37 or ACMD37 | ||||
0x12: CMD18 or ACMD18 | ||||
0x13: CMD19 or ACMD19 | ||||
0x2B: CMD43 or ACMD43 | ||||
0x37: CMD55 or ACMD55 | ||||
0x18: CMD24 or ACMD24 | ||||
0x14: CMD20 or ACMD20 | ||||
0xE: CMD14 or ACMD14 | ||||
0x16: CMD22 or ACMD22 | ||||
0x2A: CMD42 or ACMD42 | ||||
0x1C: CMD28 or ACMD28 | ||||
0x7: CMD7 or ACMD7 | ||||
0x19: CMD25 or ACMD25 | ||||
0x1F: CMD31 or ACMD31 | ||||
0x34: CMD52 or ACMD52 | ||||
0x1A: CMD26 or ACMD26 | ||||
0x29: CMD41 or ACMD41 | ||||
0xF: CMD15 or ACMD15 | ||||
0xC: CMD12 or ACMD12 | ||||
0x27: CMD39 or ACMD39 | ||||
0x22: CMD34 or ACMD34 | ||||
23:22 | CMD_TYPE | Command type | RW | 0x0 |
This register specifies three types of special command: Suspend, Resume and Abort. | ||||
These bits shall be set to 00b for all other commands. | ||||
0x0: Others Commands | ||||
0x1: CMD52 for writing "Bus Suspend" in CCCR | ||||
0x3: Abort command CMD12, CMD52 for writing " I/O Abort" in CCCR | ||||
0x2: CMD52 for writing "Function Select" in CCCR | ||||
21 | DP | Data present select | RW | 0 |
This register indicates that data is present and DAT line shall be used. | ||||
It must be set to 0 in the following conditions: | ||||
- command using only CMD line | ||||
- command with no data transfer but using busy signal on DAT[0] | ||||
- Resume command | ||||
0x0: Command with no data transfer | ||||
0x1: Command with data transfer | ||||
20 | CICE | Command Index check enable | RW | 0 |
This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. | ||||
If the index is not the same in the response as in the command, it is reported as a command index error (MMCHS_STAT[CIE] set to1). | ||||
Note: The register CICE cannot be configured for an Auto CMD12, then index check is automatically checked when this command is issued. | ||||
0x0: Index check disable | ||||
0x1: Index check enable | ||||
19 | CCCE | Command CRC check enable | RW | 0 |
This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. | ||||
If an error is detected, it is reported as a command CRC error (MMCHS_STAT[CCRC] set to 1). | ||||
Note: The register CCCE cannot be configured for an Auto CMD12, and then CRC check is automatically checked when this command is issued. | ||||
0x0: CRC7 check disable | ||||
0x1: CRC7 check enable | ||||
18 | RESERVED | R | 0 | |
17:16 | RSP_TYPE | Response type | RW | 0x0 |
This bits defines the response type of the command | ||||
0x0: No response | ||||
0x1: Response Length 136 bits | ||||
0x3: Response Length 48 bits with busy after response | ||||
0x2: Response Length 48 bits | ||||
15:6 | RESERVED | R | 0x000 | |
5 | MSBS | Multi/Single block select | RW | 0 |
This bit must be set to 1 for data transfer in case of multi block command. | ||||
For any others command this bit shall be set to 0. | ||||
0x0: Single block. | ||||
If this bit is 0, it is not necessary to set the register MMCHS_BLK[NBLK]. | ||||
0x1: Multi block. | ||||
When Block Count is disabled (MMCHS_CMD[BCE] is set to 0) in Multiple block transfers (MMCHS_CMD[MSBS] is set to 1), the module can perform infinite transfer. | ||||
4 | DDIR | Data transfer Direction Select | RW | 0 |
This bit defines either data transfer will be a read or a write. | ||||
0x0: Data Write (host to card) | ||||
0x1: Data Read (card to host) | ||||
3:2 | ACEN | Auto CMD Enable - SD card only. | RW | 0x0 |
This field determines use of auto command functions. | ||||
There are two methods to stop Multiple-block read and write operation | ||||
| ||||
– Auto CMD23 Supported (Host Controller Version is 3.00 or later) | ||||
– A memory card that supports CMD23 (SCR[33]=1) | ||||
– If DMA is used, it shall be ADMA. | ||||
–Only when CMD18 or CMD25 is issued | ||||
(Note: the Host Controller does not check command index.) | ||||
Auto CMD23 can be used with or without ADMA. By writing the Command register, the Host Controller issues a CMD23 first and then issues a command specified by the Command Index in Command register. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status register (MMCHS_AC12). 32-bit block count value for CMD23 is set to SDMA System Address / Argument 2 register (MMCHS_SDMASA). | ||||
0x0: Auto Command Disabled | ||||
0x1: Auto CMD12 enable or CCS detection enabled. | ||||
0x3: Reserved | ||||
0x2: Auto CMD23 Enable | ||||
1 | BCE | Block Count Enable | RW | 0 |
Multiple block transfers only. | ||||
This bit is used to enable the block count register (MMCHS_BLK[NBLK]). | ||||
When Block Count is disabled (MMCHS_CMD[BCE] is set to 0) in Multiple block transfers (MMCHS_CMD[MSBS] is set to 1), the module can perform infinite transfer. | ||||
0x0: Block count disabled for infinite transfer. | ||||
0x1: Block count enabled for multiple block transfer with known number of blocks | ||||
0 | DE | DMA Enable | RW | 0 |
This bit is used to enable DMA mode for host data access. | ||||
0x0: DMA mode disable | ||||
0x1: DMA mode enable |
Address Offset | 0x0000 0210 | ||
Physical Address | 0x4809 C210 0x480B 4210 0x480A D210 0x480D 1210 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Command Response[31:0] Register (bits [31:0] of the internal RSP register) This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6/R7 | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSP1 | RSP0 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RSP1 | Command Response [31:16] | R | 0x0000 |
15:0 | RSP0 | Command Response [15:0] | R | 0x0000 |
Address Offset | 0x0000 0214 | ||
Physical Address | 0x4809 C214 0x480B 4214 0x480A D214 0x480D 1214 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Command Response[63:32] Register (bits [63:32] of the internal RSP register) This 32-bit register holds bits positions [63:32] of command response type R2 | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSP3 | RSP2 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RSP3 | Command Response [63:48] | R | 0x0000 |
15:0 | RSP2 | Command Response [47:32] | R | 0x0000 |
Address Offset | 0x0000 0218 | ||
Physical Address | 0x4809 C218 0x480B 4218 0x480A D218 0x480D 1218 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Command Response[95:64] Register (bits [95:64] of the internal RSP register) This 32-bit register holds bits positions [95:64] of command response type R2 | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSP5 | RSP4 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RSP5 | Command Response [95:80] | R | 0x0000 |
15:0 | RSP4 | Command Response [79:64] | R | 0x0000 |
Address Offset | 0x0000 021C | ||
Physical Address | 0x4809 C21C 0x480B 421C 0x480A D21C 0x480D 121C | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Command Response[127:96] Register (bits [127:96] of the internal RSP register) This 32-bit register holds bits positions [127:96] of command response type R1(Auto CMD23)/R1b(Auto CMD12)/R2 | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSP7 | RSP6 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RSP7 | Command Response [127:112] | R | 0x0000 |
15:0 | RSP6 | Command Response [111:96] | R | 0x0000 |
Address Offset | 0x0000 0220 | ||
Physical Address | 0x4809 C220 0x480B 4220 0x480A D220 0x480D 1220 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Data Register This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bits x256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer. Example 1: Byte or 16-bit access Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | DATA | Data Register [31:0] In functional mode (MMCHS_CON[MODE] set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[BRE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled. A write access to this register is allowed only when the buffer write enable status is set to 1(MMCHS_STATE[BWE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled and the data is not written. | RW | 0x0000 0000 |
Address Offset | 0x0000 0224 | ||
Physical Address | 0x4809 C224 0x480B 4224 0x480A D224 0x480D 1224 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Present State Register The Host can get status of the Host Controller from this 32-bit read only register. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLEV | DLEV | WP | CDPL | CSS | CINS | RESERVED | BRE | BWE | RTA | WTA | RESERVED | RTR | DLA | DATI | CMDI |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:25 | RESERVED | R | 0x00 | |
24 | CLEV | CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time. | R | - |
Read 0x1: The CMD line level is 1. | ||||
Read 0x0: The CMD line level is 0. | ||||
23:20 | DLEV | DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. The value of these registers after reset depends on the DAT lines level at that time. | R | 0x- |
19 | WP | Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (mmci_sdwp) level. The value of this register after reset depends on the protect input pin (mmci_sdwp) level at that time. | R | - |
Read 0x1: If MMCHS_CON[WPP] is set to 0 (default), the card is not write protected, otherwise the card is protected. | ||||
Read 0x0: If MMCHS_CON[WPP] is
set to 0 (default), the card is write protected, otherwise the card
is not protected. | ||||
18 | CDPL | Card detect pin level This bit reflects the inverse value of the card detect input pin (mmci_sdcd), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTAE[CSS]) is set to 1. Use of this bit is limited to testing since it must be debounced y software. The value of this register after reset depends on the card detect input pin (mmci_sdcd) level at that time. | R | - |
Read 0x1: The value of the card detect input pin (mmci_sdcd) is 0 | ||||
Read 0x0: The value of the card detect input pin (mmci_sdcd) is 1 | ||||
17 | CSS | Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[CDPL]). Debouncing is performed on the card detect input pin (mmci_sdcd) to detect card stability. This bit is not affected by a software reset. | R | 0 |
Read 0x1: No card or card inserted | ||||
Read 0x0: Reset or Debouncing | ||||
16 | CINS | Card inserted This bit is the debounced value of the card detect input pin (mmci_sdcd). An inactive to active transition of the card detect input pin (mmci_sdcd) will generate a card insertion interrupt (MMCHS_STAT[CINS]). A active to inactive transition of the card detect input pin (mmci_sdcd) will generate a card removal interrupt (MMCHS_STAT[REM]). This bit is not affected by a software reset. | R | 0 |
Read 0x1: If MMCHS_CON[CDP] is
set to 1, the card has been inserted from the card slot. If MMCHS_CON[CDP] is set to 0, no card is detected. The card may have been removed from the card slot. | ||||
Read 0x0: If MMCHS_CON[CDP] is
set to 1, no card is detected. The card may have been removed from
the card slot. If MMCHS_CON[CDP] is set to 0, the card has been inserted. | ||||
15:12 | RESERVED | R | 0x0 | |
11 | BRE | Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[BLEN] has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from the buffer. It is set to 1 when a block data is ready in the buffer and generates the Buffer read ready status of interrupt (MMCHS_STAT[BRR]). | R | 0 |
Read 0x1: Read BLEN bytes enable. Readable data exists in the buffer. | ||||
Read 0x0: Read BLEN bytes disable | ||||
10 | BWE | Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data. | R | 0 |
Read 0x1: There is enough space in the buffer to write BLEN bytes of data. | ||||
Read 0x0: There is no room left in the buffer to write BLEN bytes of data. | ||||
9 | RTA | Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when all data have been read by the local host after last block or after a stop at block gap request. | R | 0 |
Read 0x1: read data transfer on going. | ||||
Read 0x0: No valid data on the DAT lines. | ||||
8 | WTA | Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when CRC status has been received after last block or after a stop at block gap request. | R | 0 |
Read 0x1: Write data transfer on going. | ||||
Read 0x0: No valid data on the DAT lines. | ||||
7:4 | RESERVED | R | 0x0 | |
3 | RTR | Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting MMCHS_AC12[22] ET. This bit isn't set to 1 if MMCHS_AC12[23] SCLK_SEL is set to 0 (using fixed sampling clock). Refer to MMCHS_CAPA2[15:14] RTM for more detail. | R | 0 |
Read 0x1: Sampling clock needs re-tuning | ||||
Read 0x0: Fixed or well tuned sampling clock | ||||
2 | DLA | DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 when the host controller received the end bit of the last data block or at the beginning of the read wait mode. In the case of write transactions (host to card): This bit is set to 1 after the end bit of write command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 on the end of busy event for the last block; host controller must wait 8 clock cycles with line not busy to really consider not "busy state" or after the busy block as a result of a stop at gap request. | R | 0 |
Read 0x1: DAT Line active | ||||
Read 0x0: DAT Line inactive | ||||
1 | DATI | Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued. This bit prevents the local host to issue a command. A change of this bit from 1 to 0 generates a transfer complete interrupt (MMCHS_STAT[TC]). | R | 0 |
Read 0x1: Issuing of command using DAT lines is not allowed | ||||
Read 0x0: Issuing of command using the DAT lines is allowed | ||||
0 | CMDI | Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0 in either the following cases: - After the end bit of the command response, excepted if there is a command conflict error (MMCHS_STAT[CCRC] or MMCHS_STAT[CEB] set to 1) or a Auto CMD12 is not executed (MMCHS_AC12[ACNE]). - After the end bit of the command without response (MMCHS_CMD[RSP_TYPE] set to "00") In case of a command data error is detected (MMCHS_STAT[CTO] set to 1), this register is not automatically cleared. | R | 0 |
Read 0x1: Issuing of command using CMD line is not allowed | ||||
Read 0x0: Issuing of command using CMD line is allowed |
Address Offset | 0x0000 0228 | ||
Physical Address | 0x4809 C228 0x480B 4228 0x480A D228 0x480D 1228 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Host Control
Register This register defines the host controls to set power, wakeup and transfer parameters. MMCHS_HCTL[31:24] = Wakeup control MMCHS_HCTL[23:16] = Block gap control MMCHS_HCTL[15:8] = Power control MMCHS_HCTL[7:0] = Host control | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OBWE | REM | INS | IWE | RESERVED | IBG | RWC | CR | SBGR | RESERVED | SDVS | SDBP | CDSS | CDTL | RESERVED | DMAS | HSPE | DTW | LED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:28 | RESERVED | R | 0x0 | |
27 | OBWE | Wakeup event enable for
'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP]). The write to this register is ignored when MMCHS_CON[OBIE] is not set. | RW | 0 |
0x0: Disable wakeup on 'Out-of-Band' Interrupt | ||||
0x1: Enable wakeup on 'Out-of-Band' Interrupt | ||||
26 | REM | Wakeup event enable on SD card
removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP]). | RW | 0 |
0x0: Disable wakeup on card removal | ||||
0x1: Enable wakeup on card removal | ||||
25 | INS | Wakeup event enable on SD card
insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP]). | RW | 0 |
0x0: Disable wakeup on card insertion | ||||
0x1: Enable wakeup on card insertion | ||||
24 | IWE | Wakeup event enable on SD card
interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP]). | RW | 0 |
0x0: Disable wakeup on card interrupt | ||||
0x1: Enable wakeup on card interrupt | ||||
23:20 | RESERVED | R | 0x0 | |
19 | IBG | Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be set to 0. | RW | 0 |
0x0: Disable interrupt detection at the block gap in 4-bit mode | ||||
0x1: Enable interrupt detection at the block gap in 4-bit mode | ||||
18 | RWC | Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[SBGR]) generates a read wait period after the current end of block. Be careful, if read wait is not supported it may cause a conflict on DAT line. | RW | 0 |
0x0: Disable Read Wait Control. Suspend/Resume cannot be supported. | ||||
0x1: Enable Read Wait Control | ||||
17 | CR | Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR]). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when transfer has restarted i.e DAT line is active (MMCHS_PSTATE[DLA]) or transferring data (MMCHS_PSTATE[WTA]). The Stop at block gap request must be disabled (MMCHS_HCTL[SBGR]=0) before setting this bit. | RW | 0 |
0x0: No affect | ||||
0x1: transfer restart | ||||
16 | SBGR | Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[CR]) or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver shall set this bit after all block data written. Until the transfer completion (MMCHS_STAT[TC] set to 1), the host driver shall leave this bit set to 1. If this bit is set, the local host shall not write to the data register (MMCHS_DATA). | RW | 0 |
0x0: Transfer mode | ||||
0x1: Stop at block gap | ||||
15:12 | RESERVED | R | 0x0 | |
11:9 | SDVS | SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[VS18,VS30,VS33]) before starting a transfer. | RW | 0x0 |
0x6: 3.0V (Typical) | ||||
0x7: 3.3V (Typical) | ||||
0x5: 1.8V (Typical) | ||||
8 | SDBP | SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS]). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in the command register (MMCHS_CMD) will not start the transfer. A write to this bit has no effect if the selected SD bus voltage MMCHS_HCTL[SDVS] is not supported according to capability register (MMCHS_CAPA[VS*]). | RW | 0 |
0x0: Power off | ||||
0x1: Power on | ||||
7 | CDSS | Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in order to mask unexpected interrupts caused by the glitch. The Interrupt Status/Signal Enable should be disabled during over the period of debouncing. | RW | 0 |
0x0: mmci_sdcd is selected (for normal use) | ||||
0x1: MMCHS_HCTL[6] CDTL is selected (for test purpose) | ||||
6 | CDTL | Card Detect Test Level: This bit is enabled while MMCHS_HCTL[7] CDSS is set to 1 and it indicates whether the card is inserted or not. | RW | 0 |
0x0: No Card | ||||
0x1: Card Inserted | ||||
5 | RESERVED | R | 0 | |
4:3 | DMAS | DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register MMCHS_CAPA . Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This register is only meaningful when MADMA_EN is set to 1. When MADMA_EN is set to 0 the bit field is read only and returned value is 0. | RW | 0x0 |
0x0: Reserved | ||||
0x1: Reserved | ||||
0x3: Reserved | ||||
0x2: 32-bit Address ADMA2 is selected | ||||
2 | HSPE | Before setting this bit, the Host Driver shall check the MMCHS_CAPA[21] HSS. This bit shall not be set when dual data rate mode is activated in MMCHS_CON[DDR]. | RW | 0 |
0x0: Тhe Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock | ||||
0x1: Тhe Host Controller outputs CMD line and DAT lines at the rising edge of the SD Clock NOTE: Do not set this bit to 0x1 because device was timing closed with HSPE bit set to 0x0 for all supported modes of operation. | ||||
1 | DTW | Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliance with MMC standard specification 4.x (see section 3.6). This register has no effect when the MMC 8-bit mode is selected (register MMCHS_CON[DW8] set to1 ), For SD/SDIO cards, this bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified for the supported bus width by the SD card. | RW | 0 |
0x0: 1-bit Data width (DAT[0] used) | ||||
0x1: 4-bit Data width (DAT[3:0] used) | ||||
0 | LED | Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored. | R | 0 |
Address Offset | 0x0000 022C | ||
Physical Address | 0x4809 C22C 0x480B 422C 0x480A D22C 0x480D 122C | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | SD System Control
Register This register defines the system controls to set software resets, clock frequency management and data timeout. MMCHS_SYSCTL[31:24] = Software resets MMCHS_SYSCTL[23:16] = Timeout control MMCHS_SYSCTL[15:0] = Clock control | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRD | SRC | SRA | RESERVED | DTO | CLKD | CGS | RESERVED | CEN | ICS | ICE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:27 | RESERVED | R | 0x00 | |
26 | SRD | Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see DATA Lines Reset Procedure. DAT finite state machine in both clock domain are also reset. Here below are the registers cleared by MMCHS_SYSCTL[SRD]: - MMCHS_DATA - MMCHS_PSTATE: BRE, BWE, RTA, WTA, DLA and DATI - MMCHS_HCTL: SBGR and CR - MMCHS_STAT: BRR, BWR, BGE and TC Interconnect and MMC buffer data management is reinitialized. | RW | 0 |
0x0: Reset completed | ||||
0x1: Software reset for DAT line | ||||
25 | SRC | Software reset for CMD line For more information about SRC bit manipulation, see CMD Line Reset Procedure. This bit is set to 1 for reset and released to 0 when completed. CMD finite state machine in both clock domain are also reset. Here below the registers cleared by MMCHS_SYSCTL[SRC]: - MMCHS_PSTATE: CMDI - MMCHS_STAT: CC Interconnect and MMC command status management is reinitialized. | RW | 0 |
0x0: Reset completed | ||||
0x1: Software reset for CMD line | ||||
24 | SRA | Software reset for all This bit is set to 1 for reset , and released to 0 when completed. This reset affects the entire host controller except for the capabilities registers (MMCHS_CAPA and MMCHS_CUR_CAPA). | RW | 0 |
0x0: Reset completed | ||||
0x1: Software reset for all the design | ||||
23:20 | RESERVED | R | 0x0 | |
19:16 | DTO | Data timeout counter value and
busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bitfield based on - the maximum read access time (NAC) (Refer to the SD Specification Part1 Physical Layer), - the data read access time values (TAAC and NSAC) in the card specific data register (CSD) of the card, - the timeout clock base frequency (MMCHS_CAPA[TCF]). If the card does not respond within the specified number of cycles, a data timeout error occurs (MMCHS_STA[DTO]). The MMCHS_SYSCTL[DTO] register is also used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write. | RW | 0x0 |
0xF: Reserved | ||||
0x0: TCF x 2^13 | ||||
0x1: TCF x 2^14 | ||||
0xE: TCF x 2^27 | ||||
15:6 | CLKD | Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO). | RW | 0x000 |
0x0: MMCi_FCLK bypass | ||||
0x1: MMCi_FCLK bypass | ||||
0x2: MMCi_FCLK / 2 | ||||
0x3: MMCi_FCLK / 3 | ||||
0x3FF: MMCi_FCLK / 1023 | ||||
5 | CGS | Clock Generator Select - For SD
cards Host Controller Version 3.00 supports this bit. This bit is used to select the clock generator mode in MMCHS_SYSCTL[15:6] CLKD. If the Programmable Clock Mode is supported (non-zero value is set to MMCHS_CAPA2[23:16] CM), this bit attribute is RW, and if not supported, this bit attribute is RO and zero is read. This bit depends on the setting of MMCHS_AC12[31] PV_ENABLE. If PV_ENABLE = 0, this bit is set by Host Driver. If PV_ENABLE = 1, this bit is automatically set to a value specified in one of Preset Value registers, see, Table 25-22. | R | 0 |
4:3 | RESERVED | R | 0x0 | |
2 | CEN | Clock enable This bit controls if the clock is provided to the card or not. | RW | 0 |
0x0: The clock is not provided to the card . Clock frequency can be changed . | ||||
0x1: The clock is provided to the
card and can be automatically gated when MMCHS_SYSCONFIG[AUTOIDLE]
is set to 1 (default value) . The host driver shall wait to set this bit to 1 until the Internal clock is stable (MMCHS_SYSCTL[ICS]). | ||||
1 | ICS | Internal clock stable (status) This bit indicates either the internal clock is stable or not. | R | 0 |
Read 0x1: The internal clock is stable after enabling the clock (MMCHS_SYSCTL[ICE]) or after changing the clock ratio (MMCHS_SYSCTL[CLKD]). | ||||
Read 0x0: The internal clock is not stable. | ||||
0 | ICE | Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface clock (used for reads and writes to the module register map) are not affected by this register. | RW | 0 |
0x0: The internal clock is stopped (very low power state). | ||||
0x1: The internal clock oscillates and can be automatically gated when MMCHS_SYSCONFIG[AUTOIDLE] is set to 1 (default value) . |
Address Offset | 0x0000 0230 | ||
Physical Address | 0x4809 C230 0x480B 4230 0x480A D230 0x480D 1230 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Interrupt Status
Register The interrupt status regroups all the status of the module internal events that can generate an interrupt. MMCHS_STAT[31:16] = Error Interrupt Status MMCHS_STAT[15:0] = Normal Interrupt Status | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BADA | CERR | RESERVED | TE | ADMAE | ACE | RESERVED | DEB | DCRC | DTO | CIE | CEB | CCRC | CTO | ERRI | RESERVED | BSR | OBI | CIRQ | CREM | CINS | BRR | BWR | DMA | BGE | TC | CC |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | R | 0x0 | |
29 | BADA | Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit is set during a write access to the data register (MMCHS_DATA) while buffer writes are not allowed (MMCHS_STATE[BWE] =0) | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Bad Access | ||||
Read 0x0: No Interrupt. | ||||
28 | CERR | Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error MMCHS_CSRE in set. There is no card error detection for autoCMD12 command. The host driver shall read MMCHS_RSP76 register to detect error bits in the command response. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Card error | ||||
Read 0x0: No Error | ||||
27 | RESERVED | R | 0 | |
26 | TE | Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select). By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. To reset tuning circuit, Sampling Clock shall be set to 0 before executing tuning procedure. The Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting Tuning Error, the Host Driver should discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from tuning circuit error. The bit is set if the lock is lost (but not during the tuning process) or if the lock counter expires without the lock being asserted. If the latter happens, the SW can decide to ignore the interrupt and wait some more for the lock to be set. | RW | 0 |
0x0: No Error | ||||
0x1: Error | ||||
25 | ADMAE | ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller generates this interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: ADMA error | ||||
Read 0x0: No Interrupt. | ||||
24 | ACE | Auto CMD error Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register (MMCHS_AC12) has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Auto CMD error | ||||
Read 0x0: No Error. | ||||
23 | RESERVED | R | 0 | |
22 | DEB | Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Data end bit error | ||||
Read 0x0: No Error | ||||
21 | DCRC | Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position "010" token during a block write command. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Data CRC error | ||||
Read 0x0: No Error. | ||||
20 | DTO | Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Time out | ||||
Read 0x0: No error. | ||||
19 | CIE | Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[CICE] register. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Command index error | ||||
Read 0x0: No error. | ||||
18 | CEB | Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Command end bit error | ||||
Read 0x0: No error. | ||||
17 | CCRC | Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Command CRC error | ||||
Read 0x0: No Error. | ||||
16 | CTO | Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Time Out | ||||
Read 0x0: No error | ||||
15 | ERRI | Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[31:16]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored. | R | 0 |
Read 0x1: Error interrupt event(s) occurred | ||||
Read 0x0: No Interrupt. | ||||
14:11 | RESERVED | R | 0x0 | |
10 | BSR | Boot status received interrupt This bit is set automatically when MMCHS_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Boot status received interrupt. | ||||
Read 0x0: No Interrupt. | ||||
9 | OBI | Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[OBIP]. This interrupt is only useful for MMC card. The Out-of-Band interrupt signal is a system specific feature for future use, this signal is not required for existing specification implementation. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Interrupt Out-Of-Band occurs | ||||
Read 0x0: No Out-Of-Band interrupt. | ||||
8 | CIRQ | Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives CMD line to zero during one cycle after data transmission end.All modes above are fully exclusive. The controller interrupt must be clear by setting MMCHS_IE[CIRQ] to 0, then the host driver must start the interrupt service with card (clearing card interrupt status) to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as MMCHS_IE[CIRQ] is set to 1. Writes to this bit are ignored. | R | 0 |
Read 0x1: Generate card interrupt | ||||
Read 0x0: No card interrupt | ||||
7 | CREM | Card removal This bit is set automatically when MMCHS_PSTATE[CINS] changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS]). | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Card removed | ||||
Read 0x0: Card state stable or Debouncing | ||||
6 | CINS | Card insertion This bit is set automatically when MMCHS_PSTATE[CINS] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS]). | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Card inserted | ||||
Read 0x0: Card state stable or debouncing | ||||
5 | BRR | Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it. Note: If the DMA receive-mode is enabled, this bit is never set; instead a DMA receive request to the main DMA controller of the system is generated. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Ready to read buffer | ||||
Read 0x0: Not Ready to read buffer | ||||
4 | BWR | Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit request to the main DMA controller of the system is generated. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Ready to write buffer | ||||
Read 0x0: Not Ready to write buffer | ||||
3 | DMA | DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: No dma interrupt | ||||
Read 0x0: Dma interrupt detected | ||||
2 | BGE | Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap is requested on the last block. In read mode, a 1-to-0 transition of the DAT Line active status (MMCHS_PSTATE[DLA]) between data blocks generates a Block gap event interrupt. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Transaction stopped at block gap | ||||
Read 0x0: No block gap event | ||||
1 | TC | Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR]). In Read mode: This bit is automatically set on completion of a read transfer (MMCHS_PSTATE[RTA]). In write mode: This bit is set automatically on completion of the DAT line use (MMCHS_PSTATE[DLA]). | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Data transfer complete | ||||
Read 0x0: No transfer complete | ||||
0 | CC | Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected, then the command complete interrupt is generated at the end of the command. A command timeout error (MMCHS_STAT[CTO]) has higher priority than command complete (MMCHS_STAT[CC]). If a response is expected but none is received, then a command timeout error is detected and signaled instead of the command complete interrupt. | RW | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
Read 0x1: Command complete | ||||
Read 0x0: No Command complete |
Address Offset | 0x0000 0234 | ||
Physical Address | 0x4809 C234 0x480B 4234 0x480A D234 0x480D 1234 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Interrupt Status
Enable Register This register allows to enable/disable the module to set status bits, on an event-by-event basis. MMCHS_IE[31:16] = Error Interrupt Status Enable MMCHS_IE[15:0] = Normal Interrupt Status Enable | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BADA_ENABLE | CERR_ENABLE | RESERVED | TE_ENABLE | ADMAE_ENABLE | ACE_ENABLE | RESERVED | DEB_ENABLE | DCRC_ENABLE | DTO_ENABLE | CIE_ENABLE | CEB_ENABLE | CCRC_ENABLE | CTO_ENABLE | NULL | RESERVED | BSR_ENABLE | OBI_ENABLE | CIRQ_ENABLE | CREM_ENABLE | CINS_ENABLE | BRR_ENABLE | BWR_ENABLE | DMA_ENABLE | BGE_ENABLE | TC_ENABLE | CC_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | R | 0x0 | |
29 | BADA_ENABLE | Bad access to data space Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
28 | CERR_ENABLE | Card Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
27 | RESERVED | R | 0 | |
26 | TE_ENABLE | Tuning Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
25 | ADMAE_ENABLE | ADMA Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
24 | ACE_ENABLE | Auto CMD Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
23 | RESERVED | R | 0 | |
22 | DEB_ENABLE | Data End Bit Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
21 | DCRC_ENABLE | Data CRC Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
20 | DTO_ENABLE | Data Timeout Error Status Enable | RW | 0 |
0x0: The data timeout detection is deactivated. The host controller provides the clock to the card until the card sends the data or the transfer is aborted. | ||||
0x1: The data timeout detection is enabled. | ||||
19 | CIE_ENABLE | Command Index Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
18 | CEB_ENABLE | Command End Bit Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
17 | CCRC_ENABLE | Command CRC Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
16 | CTO_ENABLE | Command Timeout Error Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
15 | NULL | Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored | R | 0 |
14:11 | RESERVED | R | 0x0 | |
10 | BSR_ENABLE | Boot Status Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored. | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
9 | OBI_ENABLE | Out-of-Band Status Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored. | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
8 | CIRQ_ENABLE | Card Status Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1. | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
7 | CREM_ENABLE | Card Removal Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
6 | CINS_ENABLE | Card Insertion Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
5 | BRR_ENABLE | Buffer Read Ready Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
4 | BWR_ENABLE | Buffer Write Ready Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
3 | DMA_ENABLE | DMA Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
2 | BGE_ENABLE | Block Gap Event Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
1 | TC_ENABLE | Transfer Complete Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
0 | CC_ENABLE | Command Complete Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled |
Address Offset | 0x0000 0238 | ||
Physical Address | 0x4809 C238 0x480B 4238 0x480A D238 0x480D 1238 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Interrupt Signal
Enable Register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. MMCHS_ISE[31:16] = Error Interrupt Signal Enable MMCHS_ISE[15:0] = Normal Interrupt Signal Enable | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BADA_SIGEN | CERR_SIGEN | RESERVED | TE_SIGEN | ADMAE_SIGEN | ACE_SIGEN | RESERVED | DEB_SIGEN | DCRC_SIGEN | DTO_SIGEN | CIE_SIGEN | CEB_SIGEN | CCRC_SIGEN | CTO_SIGEN | NULL | RESERVED | BSR_SIGEN | OBI_SIGEN | CIRQ_SIGEN | CREM_SIGEN | CINS_SIGEN | BRR_SIGEN | BWR_SIGEN | DMA_SIGEN | BGE_SIGEN | TC_SIGEN | CC_SIGEN |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | R | 0x0 | |
29 | BADA_SIGEN | Bad access to data space Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
28 | CERR_SIGEN | Card Error Interrupt Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
27 | RESERVED | R | 0 | |
26 | TE_SIGEN | Tuning Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
25 | ADMAE_SIGEN | ADMA Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
24 | ACE_SIGEN | Auto CMD Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
23 | RESERVED | R | 0 | |
22 | DEB_SIGEN | Data End Bit Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
21 | DCRC_SIGEN | Data CRC Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
20 | DTO_SIGEN | Data Timeout Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
19 | CIE_SIGEN | Command Index Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
18 | CEB_SIGEN | Command End Bit Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
17 | CCRC_SIGEN | Command CRC Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
16 | CTO_SIGEN | Command timeout Error Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
15 | NULL | Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored | R | 0 |
14:11 | RESERVED | R | 0x0 | |
10 | BSR_SIGEN | Boot Status Signal Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored. | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
9 | OBI_SIGEN | Out-Of-Band Interrupt Signal
Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored. | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
8 | CIRQ_SIGEN | Card Interrupt Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
7 | CREM_SIGEN | Card Removal Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
6 | CINS_SIGEN | Card Insertion Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
5 | BRR_SIGEN | Buffer Read Ready Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
4 | BWR_SIGEN | Buffer Write Ready Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
3 | DMA_SIGEN | DMA Interrupt Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
2 | BGE_SIGEN | Black Gap Event Signal Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
1 | TC_SIGEN | Transfer Completed Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled | ||||
0 | CC_SIGEN | Command Complete Status Enable | RW | 0 |
0x0: Masked | ||||
0x1: Enabled |
Address Offset | 0x0000 023C | ||
Physical Address | 0x4809 C23C 0x480B 423C 0x480A D23C 0x480D 123C | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Host Control 2
Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12 / CMD23 errors occur by this register. Auto CMD23 errors are indicated only in bits[4:1]. Bits[7:0] are valid only when the MMCHS_CMD[3:2] ACEN bitfield is configured to enable Auto CMD and the Auto CMD Error bit (MMCHS_STAT[24]ACE) is set. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PV_ENABLE | AI_ENABLE | RESERVED | SCLK_SEL | ET | DS_SEL | V1V8_SIGEN | UHSMS | RESERVED | CNI | RESERVED | ACIE | ACEB | ACCE | ACTO | ACNE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | PV_ENABLE | Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When Preset Value Enable is set, automatic SDCLK frequency generation and driver strength selection is performed without considering system specific conditions. This bit enables the functions defined in the Preset Value registers, see, Table 25-22. If this bit is set to 0, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Driver. If this bit is set to 1, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Controller as specified in the Preset Value registers, see, Table 25-22. | RW | 0 |
0x0: SDCLK and Driver Strength (DS_SEL) are controlled by Host Driver. | ||||
0x1: Automatic Selection by Preset Value are Enabled. | ||||
30 | AI_ENABLE | Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver the Card Interrupt to the host when it is asserted by the Card. | RW | 0 |
0x0: Disabled | ||||
0x1: Enabled | ||||
29:24 | RESERVED | R | 0x00 | |
23 | SCLK_SEL | Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is set by tuning procedure and valid after the completion of tuning (when MMCHS_AC12[22] ET is cleared). Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Writing 1 to this bit is meaningless and ignored. A tuning circuit is reset by writing to 0. This bit can be cleared with setting MMCHS_AC12[22] ET. Once the tuning circuit is reset, it will take time to complete tuning sequence. Therefore, Host Driver should keep this bit to 1 to perform re-tuning sequence to compete re-tuning sequence in a short time. Change of this bit is not allowed while the Host Controller is receiving response or a read data block. | RW | 0 |
0x0: Fixed clock is used to sample data | ||||
0x1: Tuned clock is used to sample data | ||||
22 | ET | Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to MMCHS_AC12[23] SCLK_SEL. Tuning procedure is aborted by writing 0. This is Read-Write with automatic clear register | RW | 0 |
0x0: Not Tuned or Tuning Completed | ||||
0x1: Execute Tuning | ||||
21:20 | DS_SEL | Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depending on Driver Type A, C and D support bits (DTA, DTC and DTD respectively) in the MMCHS_CAPA2 register. This bit depends on setting of Preset Value Enable. If Preset Value Enable = 0, this field is set by Host Driver. If Preset Value Enable = 1, this field is automatically set by a value specified in the one of Preset Value registers, see, Table 25-22. | RW | 0x0 |
0x0: Driver Type B is selected (Default) | ||||
0x1: Driver Type A is selected | ||||
0x3: Driver Type D is selected | ||||
0x2: Driver Type C is selected | ||||
19 | V1V8_SIGEN | 1.8V Signaling Enable This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling (One of support bits is set to 1: SDR50, SDR104 or DDR50 in MMCHS_CAPA2 register) and the card or device supports UHS-I (S18A=1. Refer to Bus Signal Voltage Switch Sequence in the Physical Layer Specification Version 3.0x). | RW | 0 |
0x0: 3.3V Signaling | ||||
0x1: 1.8V Signaling | ||||
18:16 | UHSMS | UHS Mode Select This field is used to select one of UHS-I modes or eMMC HS200 mode and is effective when 1.8V Signaling Enable is set to 1. If MMCHS_AC12[31] PV_ENABLE is set to 1, Host Controller sets MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL according to Preset Value registers, see, Table 25-22. In this case, one of preset value registers is selected by this field. Host Driver needs to reset MMCHS_SYSCTL[2] CEN before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets MMCHS_SYSCTL[2] CEN again. When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more detail. | RW | 0x0 |
0x0: SDR12 | ||||
0x1: SDR25 | ||||
0x2: SDR50 | ||||
0x3: SDR104/HS200 | ||||
0x4: DDR50 | ||||
0x5: Reserved | ||||
0x6: Reserved | ||||
0x7: Reserved | ||||
15:8 | RESERVED | R | 0x00 | |
7 | CNI | Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. | R | 0 |
Read 0x1: Command not issued | ||||
Read 0x0: No error | ||||
6:5 | RESERVED | R | 0x0 | |
4 | ACIE | Auto CMD Index Error - For Auto CMD12 and Auto CMD23 This bit is set if the Command Index error occurs in response to a command. | R | 0 |
Read 0x1: Error | ||||
Read 0x0: No error | ||||
3 | ACEB | Auto CMD End Bit Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting that the end bit of command response is 0. | R | 0 |
Read 0x1: End bit Error Generated | ||||
Read 0x0: No error | ||||
2 | ACCE | Auto CMD CRC Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting a CRC error in the command response. | R | 0 |
Read 0x1: CRC Error Generated | ||||
Read 0x0: No error | ||||
1 | ACTO | Auto CMD Timeout Error - For Auto CMD12 and Auto CMD23 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command. If this bit is set to1, the other error status bits (D04-D02) are meaningless. | R | 0 |
Read 0x1: Auto CMD Time Out | ||||
Read 0x0: No error | ||||
0 | ACNE | Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controller cannot issue Auto CMD12 to stop memory multiple block data transfer due to some error. If this bit is set to 1, other error status bits (D04-D01) are meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. | R | 0 |
Read 0x1: Auto CMD12 Not Executed | ||||
Read 0x0: Auto CMD12 Executed |
Address Offset | 0x0000 0240 | ||
Physical Address | 0x4809 C240 0x480B 4240 0x480A D240 0x480D 1240 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Capabilities Register This register lists the capabilities of the MMC/SD/SDIO host controller. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AIS | BIT64 | RESERVED | VS18 | VS30 | VS33 | SRS | DS | HSS | RESERVED | AD2S | RESERVED | MBL | BCF | TCU | RESERVED | TCF |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | R | 0x0 | |
29 | AIS | Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt. | R | 1 |
Read 0x1: Asynchronous Interrupt Supported | ||||
Read 0x0: Asynchronous Interrupt Not Supported | ||||
28 | BIT64 | 64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. | R | 0 |
Read 0x1: 64 bit System bus address | ||||
Read 0x0: 32 bit System bus address | ||||
27 | RESERVED | R | 0 | |
26 | VS18 | Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal) | RW | 0 |
Write 0x0: 1.8V Not supported | ||||
Write 0x1: 1.8V Supported | ||||
Read 0x1: 1.8V Supported | ||||
Read 0x0: 1.8V Not Supported | ||||
25 | VS30 | Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal) | RW | 0 |
Write 0x0: 3.0V Not supported | ||||
Write 0x1: 3.0V Supported | ||||
Read 0x1: 3.0V Supported | ||||
Read 0x0: 3.0V Not Supported | ||||
24 | VS33 | Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal) | RW | 0 |
Write 0x0: 3.3V Not supported | ||||
Write 0x1: 3.3V Supported | ||||
Read 0x1: 3.3V Supported | ||||
Read 0x0: 3.3V Not Supported | ||||
23 | SRS | Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality. | R | 1 |
Read 0x1: The Host controller supports Suspend/Resume functionality. | ||||
Read 0x0: The Host controller does not Suspend/Resume functionality. | ||||
22 | DS | DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly. | R | 1 |
Read 0x1: DMA Supported | ||||
Read 0x0: DMA Not Supported | ||||
21 | HSS | High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency. | R | 1 |
Read 0x1: High Speed Supported | ||||
Read 0x0: High Speed Not
Supported NOTE: High Speed modes are supported, but MMCHS_HCTL[HSPE] bit must always be set to 0x0 because device was timing closed with HSPE bit set to 0x0 for all supported modes of operation. | ||||
20 | RESERVED | R | 0 | |
19 | AD2S | ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. It depends on setting of generic parameter MADMA_EN | R | 0 |
Read 0x1: ADMA2 Supported | ||||
Read 0x0: ADMA2 not Supported | ||||
18 | RESERVED | R | 0 | |
17:16 | MBL | Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 bytes. The host controller supports 512 bytes and 1024 bytes block transfers. | R | 0x1 |
Read 0x2: 2048 bytes | ||||
Read 0x1: 1024 bytes | ||||
Read 0x0: 512 bytes | ||||
15:8 | BCF | Base Clock Frequency For SD
Clock This value indicates the base (maximum) clock frequency for the SD Clock. 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh : 255MHz .... : ....... 02h : 2MHz 01h : 1MHz 00h : Get information via another method If the real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because the Host Driver use this value to calculate the clock divider value (Refer to MMCHS_SYSCTL[15:6] CLKD) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method. | R | 0x00 |
Read 0x0: The value indicating the base (maximum) frequency for the output clock provided to the card is system dependent and is not available in this register. Get the information via another method. | ||||
7 | TCU | Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO]). | R | 1 |
Read 0x1: MHz | ||||
Read 0x0: KHz | ||||
6 | RESERVED | R | 0 | |
5:0 | TCF | Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO]). | R | 0x00 |
Read 0x0: The timeout clock frequency depends on the frequency of the clock provided to the card. The value of the timeout clock frequency is not available in this register. |
Address Offset | 0x0000 0244 | ||
Physical Address | 0x4809 C244 0x480B 4244 0x480A D244 0x480D 1244 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset For All in the Software Reset register for loading from flash memory and completion timing control. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CM | RTM | TSDR50 | RESERVED | TCRT | RESERVED | DTD | DTC | DTA | RESERVED | DDR50 | SDR104 | SDR50 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | R | 0x00 | |
23:16 | CM | Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to MMCHS_SYSCTL [15:0]. Setting 00h means that Host Controller does not support programmable clock generator. 00h : Clock Multiplier is Not Supported 01h : Clock Multiplier M = 2 02h : Clock Multiplier M = 3 .... : ...................... FFh : Clock Multiplier M = 256 | R | 0x00 |
15:14 | RTM | Re-Tuning Modes This field selects re-tuning method and limits the maximum data length. Bit47-46 Re-Tuning Mode Re-Tuning Method Data Length There are two re-tuning timings: Re-Tuning Request controlled by the Host Controller and expiration of a Re-Tuning Timer controlled by the Host Driver. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue. The maximum data length per read/write command is restricted so that re-tuning procedures can be inserted during data transfers. (1) Re-Tuning Mode 1 The host controller does not have any internal logic to detect when the re-tuning needs to be performed. In this case, the Host Driver should maintain all re-tuning timings by using a Re-Tuning Timer. To enable inserting the re-tuning procedure during data transfers, the data length per read/write command shall be limited up to 4 MiB. (2) Re-Tuning Mode 2 The host controller has the capability to indicate the re-tuning timing by Re-Tuning Request during data transfers. Then the data length per read/write command shall be limited up to 4 MiB. During non data transfer, re-tuning timing is determined by either Re-Tuning Request or Re-Tuning Timer. If Re-Tuning Request is used, Re-Tuning Timer should be disabled. (3) Re-Tuning Mode 3 The host controller has the capability to take care of the re-tuning during data transfer (Auto Re-Tuning). Re-Tuning Request shall not be generated during data transfers and there is no limitation to data length per read/write command. During non data transfer, re-tuning timing is determined by either Re-Tuning Request or Re-Tuning Timer. If Re-Tuning Request is used, Re-Tuning Timer should be disabled. Re-Tuning Timer Control Example for Re-Tuning Mode 1 The initial value of re-tuning timer is provided by Timer Count for Re-Tuning field in this register. The timer starts counting by loading the initial value. When the timer expires, the Host Driver marks an expiration flag. On receiving a command request, the Host driver checks the expiration flag. If the expiration flag is set, then the Host Driver should perform the re-tuning procedure before issuing a command. If the expiration flag is not set, then the Host Driver issues a command without performing the re-tuning procedure. Every time the re-tuning procedure is performed, the timer loads the new initial value and the expiration flag is cleared. Re-Tuning Timer Control Example for Re-Tuning Mode 2 and Mode 3 The timer control is almost the same as Re-Tuning Mode 1 except the timer loads the new initial value after data transfer (when receiving Transfer Complete). In case of Mode 3, Timer Count for Re-Tuning is set either smaller value: Tuning effective time after re-tuning procedure or after data transfer. If a Host System goes into power down mode, the Host Driver should stop the re-tuning timer and set the expiration flag to 1 when the Host System resumes from power down mode. | R | 0x0 |
Read 0x3: Reserved | ||||
Read 0x2: Auto Re-Tuning (for transfer) - Timer and Re-Tuning Request | ||||
Read 0x1: Timer and Re-Tuning Request - Max data length 4 MiB | ||||
Read 0x0: Timer - Max data length 4 MiB | ||||
13 | TSDR50 | Use Tuning for SDR50 If this bit is set to 1, this Host Controller requires tuning to operate SDR50. (Tuning is always required to operate SDR104.) | R | 0 |
Read 0x1: SDR50 requires tuning. | ||||
Read 0x0: SDR50 does not require tuning. | ||||
12 | RESERVED | R | 0 | |
11:8 | TCRT | Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 0 disables Re-Tuning Timer. | R | 0xF |
Read 0x3: 4 seconds | ||||
Read 0xE: Reserved | ||||
Read 0xC: Reserved | ||||
Read 0x4: 8 seconds | ||||
Read 0xB: 1024 seconds | ||||
Read 0xF: Get information from other source | ||||
Read 0x2: 2 seconds | ||||
Read 0x0: Re-Tuning Timer disabled | ||||
Read 0xA: 512 seconds | ||||
Read 0x6: 32 seconds | ||||
Read 0x1: 1 second | ||||
Read 0x8: 128 seconds | ||||
Read 0x7: 64 seconds | ||||
Read 0x9: 256 seconds | ||||
Read 0xD: Reserved | ||||
Read 0x5: 16 seconds | ||||
7 | RESERVED | R | 0 | |
6 | DTD | Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling. | R | 1 |
Read 0x1: Driver Type D is Supported | ||||
Read 0x0: Driver Type D is Not Supported. | ||||
5 | DTC | Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling. | R | 1 |
Read 0x1: Driver Type C is Supported. | ||||
Read 0x0: Driver Type C is Not Supported. | ||||
4 | DTA | Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling. | R | 1 |
Read 0x1: Driver Type A is Supported. | ||||
Read 0x0: Driver Type A is Not Supported. | ||||
3 | RESERVED | R | 0 | |
2 | DDR50 | DDR50 Support | R | 1(1) |
Read 0x1: DDR50 is Supported. | ||||
Read 0x0: DDR50 is Not Supported. | ||||
1 | SDR104 | SDR104 Support SDR104 requires tuning. | R | 1(1) |
Read 0x1: SDR104 is Supported. | ||||
Read 0x0: SDR104 is Not Supported. | ||||
0 | SDR50 | SDR50 Support If SDR104 is supported, this bit shall be set to 1. Bit 13 indicates whether SDR50 requires tuning or not. | R | 1(1) |
Read 0x1: SDR50 is Supported. | ||||
Read 0x0: SDR50 is Not Supported. |
Supported Mode | Supported By |
---|---|
DDR50 | MMC1 |
SDR104 | MMC1 |
SDR50 | MMC1, MMC3 |
Address Offset | 0x0000 0248 | ||
Physical Address | 0x4809 C248 0x480B 4248 0x480A D248 0x480D 1248 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Maximum Current
Capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (MMCHS_CAPA). Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal) | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CUR_1V8 | CUR_3V0 | CUR_3V3 |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | RESERVED | R | 0x00 | |
23:16 | CUR_1V8 | Maximum current for 1.8V | RW | 0x00 |
Read 0x0: The maximum current capability for this voltage is not available. Feature not implemented. | ||||
15:8 | CUR_3V0 | Maximum current for 3.0V | RW | 0x00 |
Read 0x0: The maximum current capability for this voltage is not available. Feature not implemented. | ||||
7:0 | CUR_3V3 | Maximum current for 3.3V | RW | 0x00 |
Read 0x0: The maximum current capability for this voltage is not available. Feature not implemented. |
Address Offset | 0x0000 0250 | ||
Physical Address | 0x4809 C250 0x480B 4250 0x480A D250 0x480D 1250 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Force Event Register
for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register. Rather, it is an address at which the Auto CMD Error Status Register (MMCHS_AC12) can be written. Writing 1 : set each bit of the Auto CMD Error Status Register Writing 0 : no effect Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set. Writing 1 : set each bit of the Error Interrupt Status Register Writing 0 : no effect Note: By setting this register, the Error Interrupt can be set in the Error Interrupt Status register. In order to generate interrupt signal, both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set. | ||
Type | W |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FE_BADA | FE_CERR | RESERVED | FE_ADMAE | FE_ACE | RESERVED | FE_DEB | FE_DCRC | FE_DTO | FE_CIE | FE_CEB | FE_CCRC | FE_CTO | RESERVED | FE_CNI | RESERVED | FE_ACIE | FE_ACEB | FE_ACCE | FE_ACTO | FE_ACNE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | RESERVED | NA | 0x0 | |
29 | FE_BADA | Force Event Bad access to data space. | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
28 | FE_CERR | Force Event Card error. | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
27:26 | RESERVED | NA | 0x0 | |
25 | FE_ADMAE | Force Event ADMA Error. | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
24 | FE_ACE | Force Event for Auto CMD Error - For Auto CMD12 and Auto CMD23 | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
23 | RESERVED | NA | 0 | |
22 | FE_DEB | Force Event Data End Bit error. | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
21 | FE_DCRC | Force Event Data CRC Error. | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
20 | FE_DTO | Force Event Data Timeout Error. | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
19 | FE_CIE | Force Event Command Index Error. | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
18 | FE_CEB | Force Event Command End Bit Error. | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
17 | FE_CCRC | Force Event Command CRC Error. | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
16 | FE_CTO | Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles. | W | 0 |
Write 0x0: Status bit unchanged | ||||
Write 0x1: Status is cleared | ||||
15:8 | RESERVED | NA | 0x00 | |
7 | FE_CNI | Force Event Command not issue by Auto CMD12 error | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
6:5 | RESERVED | NA | 0x0 | |
4 | FE_ACIE | Force Event for Auto CMD Index Error - For Auto CMD12 and Auto CMD23 | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
3 | FE_ACEB | Force Event Auto CMD End Bit Error | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
2 | FE_ACCE | Force Event Auto CMD CRC Error | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
1 | FE_ACTO | Force Event Auto CMD Timeout Error | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced | ||||
0 | FE_ACNE | Force Event Auto CMD12 Not Executed | W | 0 |
Write 0x0: No effect, No Interrupt. | ||||
Write 0x1: Interrupt Forced |
Address Offset | 0x0000 0254 | ||
Physical Address | 0x4809 C254 0x480B 4254 0x480A D254 0x480D 1254 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | ADMA Error Status Register When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver requires the ADMA state to identify the error descriptor address as follows: ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address ST_FDS: Current location set in the ADMA System Address register is the error descriptor address ST_CADR: This sate is never set because do not generate ADMA error in this state. ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address In case of write operation, the Host Driver should use ACMD22 to get the number of written block rather than using this information, since unwritten data may exist in the Host Controller. The Host Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver may find that the Valid bit is not set in the error descriptor. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LME | AES |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:3 | RESERVED | R | 0x0000 0000 | |
2 | LME | ADMA Length Mismatch Error: (1) While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. (2) Total data length can not be divided by the block length. | RW | 0 |
0x0: No Error | ||||
0x1: Error | ||||
1:0 | AES | ADMA Error State This field indicates the state of ADMA when error occurred during ADMA data transfer. This field will never be 0x2 because ADMA never stops in that state. 0x0: ST_STOP (STOP_ADMA). Previous SYS_ADR is the error descriptor address 0x1: ST_FDS (Fetch Descriptor). Content of current SYS_ADR is the error descriptor address 0x2: Not used. Error never set in this state 0x3: ST_TFR (Transfer Data). Previous SYS_ADR is the error descriptor address | RW | 0x0 |
Address Offset | 0x0000 0258 | ||
Physical Address | 0x4809 C258 0x480B 4258 0x480A D258 0x480D 1258 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | ADMA System address Low bits | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADMA_A32B |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | ADMA_A32B | ADMA System address 32 bits.This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32-bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold valid Descriptor address depending on the ADMA state. The Host Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be 00b. | RW | 0x0000 0000 |
Address Offset | 0x0000 0260 | ||
Physical Address | 0x4809 C260 0x480B 4260 0x480A D260 0x480D 1260 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Preset Value for Initialization and Default Speed modes | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSDS_SEL | RESERVED | DSCLKGEN_SEL | DSSDCLK_SEL | INITDS_SEL | RESERVED | INITCLKGEN_SEL | INITSDCLK_SEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | DSDS_SEL | Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. | R | 0x0 |
Read 0x3: Driver Type D is Selected. | ||||
Read 0x2: Driver Type C is Selected. | ||||
Read 0x1: Driver Type A is Selected. | ||||
Read 0x0: Driver Type B is Selected. | ||||
29:27 | RESERVED | R | 0x0 | |
26 | DSCLKGEN_SEL | Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator. | R | 0 |
Read 0x1: Programmable Clock Generator. | ||||
Read 0x0: Host Controller Ver2.00 Compatible Clock Generator. | ||||
25:16 | DSSDCLK_SEL | SDCLK Frequency Select Value -
Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system. | R | 0x004 |
15:14 | INITDS_SEL | Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. | R | 0x0 |
Read 0x3: Driver Type D is Selected | ||||
Read 0x2: Driver Type C is Selected | ||||
Read 0x1: Driver Type A is Selected | ||||
Read 0x0: Driver Type B is Selected | ||||
13:11 | RESERVED | R | 0x0 | |
10 | INITCLKGEN_SEL | Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator. | R | 0 |
Read 0x1: Programmable Clock Generator. | ||||
Read 0x0: Host Controller Ver2.00 Compatible Clock Generator. | ||||
9:0 | INITSDCLK_SEL | SDCLK Frequency Select Value -
Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system. | R | 0x1E0 |
Address Offset | 0x0000 0264 | ||
Physical Address | 0x4809 C264 0x480B 4264 0x480A D264 0x480D 1264 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Preset Value for High Speed and SDR12 speed modes | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SDR12DS_SEL | RESERVED | SDR12CLKGEN_SEL | SDR12SDCLK_SEL | HSDS_SEL | RESERVED | HSCLKGEN_SEL | HSSDCLK_SEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | SDR12DS_SEL | Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. | R | 0x0 |
Read 0x3: Driver Type D is Selected. | ||||
Read 0x2: Driver Type C is Selected. | ||||
Read 0x1: Driver Type A is Selected. | ||||
Read 0x0: Driver Type B is Selected. | ||||
29:27 | RESERVED | R | 0x0 | |
26 | SDR12CLKGEN_SEL | Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator. | R | 0 |
Read 0x1: Programmable Clock Generator. | ||||
Read 0x0: Host Controller Ver2.00 Compatible Clock Generator. | ||||
25:16 | SDR12SDCLK_SEL | SDCLK Frequency Select Value -
SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system. | R | 0x004 |
15:14 | HSDS_SEL | Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. | R | 0x0 |
Read 0x3: Driver Type D is Selected. | ||||
Read 0x2: Driver Type C is Selected. | ||||
Read 0x1: Driver Type A is Selected. | ||||
Read 0x0: Driver Type B is Selected. | ||||
13:11 | RESERVED | R | 0x0 | |
10 | HSCLKGEN_SEL | Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator. | R | 0 |
Read 0x1: Programmable Clock Generator. | ||||
Read 0x0: Host Controller Ver2.00 Compatible Clock Generator. | ||||
9:0 | HSSDCLK_SEL | SDCLK Frequency Select Value -
High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system. | R | 0x002 |
Address Offset | 0x0000 0268 | ||
Physical Address | 0x4809 C268 0x480B 4268 0x480A D268 0x480D 1268 | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Preset Value for SDR25 and SDR50 speed modes | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SDR50DS_SEL | RESERVED | SDR50CLKGEN_SEL | SDR50SDCLK_SEL | SDR25DS_SEL | RESERVED | SDR25CLKGEN_SEL | SDR25SDCLK_SEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | SDR50DS_SEL | Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. | R | 0x0 |
Read 0x3: Driver Type D is Selected. | ||||
Read 0x2: Driver Type C is Selected. | ||||
Read 0x1: Driver Type A is Selected. | ||||
Read 0x0: Driver Type B is Selected. | ||||
29:27 | RESERVED | R | 0x0 | |
26 | SDR50CLKGEN_SEL | Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator. | R | 0 |
Read 0x1: Programmable Clock Generator. | ||||
Read 0x0: Host Controller Ver2.00 Compatible Clock Generator. | ||||
25:16 | SDR50SDCLK_SEL | SDCLK Frequency Select Value -
SDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system. | R | 0x001 |
15:14 | SDR25DS_SEL | Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. | R | 0x0 |
Read 0x3: Driver Type D is Selected. | ||||
Read 0x2: Driver Type C is Selected. | ||||
Read 0x1: Driver Type A is Selected. | ||||
Read 0x0: Driver Type B is Selected. | ||||
13:11 | RESERVED | R | 0x0 | |
10 | SDR25CLKGEN_SEL | Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator. | R | 0 |
Read 0x1: Programmable Clock Generato. | ||||
Read 0x0: Host Controller Ver2.00 Compatible Clock Generator. | ||||
9:0 | SDR25SDCLK_SEL | SDCLK Frequency Select Value -
SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system. | R | 0x002 |
Address Offset | 0x0000 026C | ||
Physical Address | 0x4809 C26C 0x480B 426C 0x480A D26C 0x480D 126C | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Preset Value for SDR104 and DDR50 speed modes | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DDR50DS_SEL | RESERVED | DDR50CLKGEN_SEL | DDR50SDCLK_SEL | SDR104DS_SEL | RESERVED | SDR104CLKGEN_SEL | SDR104SDCLK_SEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | DDR50DS_SEL | Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. | R | 0x0 |
Read 0x3: Driver Type D is Selected. | ||||
Read 0x2: Driver Type C is Selected. | ||||
Read 0x1: Driver Type A is Selected. | ||||
Read 0x0: Driver Type B is Selected. | ||||
29:27 | RESERVED | R | 0x0 | |
26 | DDR50CLKGEN_SEL | Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator. | R | 0 |
Read 0x1: Programmable Clock Generator | ||||
Read 0x0: Host Controller Ver2.00 Compatible Clock Generator | ||||
25:16 | DDR50SDCLK_SEL | SDCLK Frequency Select Value -
DDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system. | R | 0x002 |
15:14 | SDR104DS_SEL | Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. | R | 0x0 |
Read 0x3: Driver Type D is Selected. | ||||
Read 0x2: Driver Type C is Selected. | ||||
Read 0x1: Driver Type A is Selected. | ||||
Read 0x0: Driver Type B is Selected. | ||||
13:11 | RESERVED | R | 0x0 | |
10 | SDR104CLKGEN_SEL | Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator. | R | 0 |
Read 0x1: Programmable Clock Generator. | ||||
Read 0x0: Host Controller Ver2.00 Compatible Clock Generator. | ||||
9:0 | SDR104SDCLK_SEL | SDCLK Frequency Select Value -
SDR104 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system. | R | 0x000 |
Address Offset | 0x0000 02FC | ||
Physical Address | 0x4809 C2FC 0x480B 42FC 0x480A D2FC 0x480D 12FC | Instance | MMC1 MMC2 MMC3 MMC4 |
Description | Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. MMCHS_REV[31:16] = Host controller version MMCHS_REV[15:0] = Slot Interrupt Status | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VREV | SREV | RESERVED | SIS |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:24 | VREV | Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1 | R | 0x-- |
23:16 | SREV | Specification Version Number This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version. | R | 0x02 |
Read 0x3: Reserved | ||||
Read 0x2: SD Host Specification Version 3.00. | ||||
Read 0x1: SD Host Specification Version 2.00 - Including the feature of the ADMA and Test Register. | ||||
Read 0x0: SD Host Specification Version 1.00. | ||||
15:1 | RESERVED | R | 0x0000 | |
0 | SIS | Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_HCTL[SRA]), the interrupt signal shall be de-asserted and this status shall read 0. | R | 0 |