SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The DPLL_HDMI controller works in manual mode. In this mode the DPLL_HDMI requires a sequence on TINITZ, TENABLE, and TENABLEDIV to update the configuration values and start the locking sequence.
When all the configuration values are programmed into the registers, the GO bit must be set. The appropriate sequence is then sent on the TINITZ, TENABLE, and TENABLEDIV pins, respecting the timing requirements of the DPLL_HDMI. The PLLCTRL_HDMI_GO[0] PLL_GO bit is cleared to 0 at the end of the sequence.
In this mode, software must deassert CLKINEN by resetting the PLLCTRL_HDMI_CONFIGURATION2[14] PHY_CLKINEN bit to 0 to prevent uncontrolled frequencies affecting HDMI_PHY and the display subsystem during DPLL_HDMI locking.
Figure 11-21 shows the PLLCTRL HDMI GO flow chart in manual mode.