SPRUI30H November 2015 – May 2024 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
The GPMC_CONFIG7_i register (where i = 0 to 7) associated with a NAND device region interfaced in byte or word stream mode can be initialized with a minimum size of 16MiB, because any address location in the chip-select memory region can be used to access a NAND data array. The NAND flash protocol specifies an address sequence where address bits are passed through the data bus in a series of write accesses with the ALE pin asserted. After this address phase, all operations are streamed and the system requests address is irrelevant.
To allow correct command, address, and data-access controls, the GPMC_CONFIG1_i register associated with a NAND device region must be initialized in asynchronous read and write modes with the parameters listed in Table 15-425. Failure to comply with these settings corrupts the NAND interface protocol.
Bit Field | Register | Value | Comments |
---|---|---|---|
WRAPBURST | GPMC_CONFIG1_i[31] (1) | 0 | No wrap |
READMULTIPLE | GPMC_CONFIG1_i[30] | 0 | Single access |
READTYPE | GPMC_CONFIG1_i[29] | 0 | Asynchronous mode |
WRITEMULTIPLE | GPMC_CONFIG1_i[28] | 0 | Single access |
WRITETYPE | GPMC_CONFIG1_i[27] | 0 | Asynchronous mode |
CLKACTIVATIONTIME | GPMC_CONFIG1_i[26:25] | 0b00 | |
ATTACHEDDEVICEPAGELENGTH | GPMC_CONFIG1_i[24:23] | Don't care | Single-access mode |
WAITREADMONITORING | GPMC_CONFIG1_i[22] | 0 | Wait not monitored by GPMC access engine |
WAITWRITEMONITORING | GPMC_CONFIG1_i[21] | 0 | Wait not monitored by GPMC access engine |
WAITMONITORINGTIME | GPMC_CONFIG1_i[19:18] | Don't care | Wait not monitored by GPMC access engine |
WAITPINSELECT | GPMC_CONFIG1_i[17:16] | Select which wait is monitored by edge detectors | |
DEVICESIZE | GPMC_CONFIG1_i[13:12] | 0b00 or 0b01 | 8- or 16-bit interface |
DEVICETYPE | GPMC_CONFIG1_i[11:10] | 0b10 | NAND device in stream mode |
MUXADDDATA | GPMC_CONFIG1_i[9:8] | 0b00 | Nonmultiplexed mode |
TIMEPARAGRANULARITY | GPMC_CONFIG1_i[4] | 0 | Timing achieved with best GPMC clock granularity |
GPMCFCLKDIVIDER | GPMC_CONFIG1_i[1:0] | Don't care | Asynchronous mode |
The GPMC_CONFIG1_i to GPMC_CONFIG4_i registers (where i = 0 to 7) associated with a NAND device region must be initialized with the correct control-signal timing value according to the NAND device timing parameters.