SPRUI30H November 2015 – May 2024 DRA744 , DRA745 , DRA746 , DRA750 , DRA756
Table 14-21 summarizes the configuration of the L3_MAIN firewalls.
Device/Region: 0 | ||||||
---|---|---|---|---|---|---|
Permission Type | Reset Value | Reset Value | Reset Type | Run Time | Firewall Register (where j = 0) | Control Module Register |
ACCESS_ PERMISSION | All | 0xFFF | Exported | Configurable | MRM_PERMISSION_REGION_LOW_j[11:0] | CONTROL_CORE_L3_HW_FW_ EXPORTED_VALUES_CONF_LOCK_1[k] CONTROL_CORE_L3_HW_FW_ EXPORTED_VALUES_CONF_LOCK_2[j] |
DEBUG_ PERMISSION | All | 0xF | Exported | Configurable | MRM_PERMISSION_REGION_LOW_j[15:12] | CONTROL_CORE_L3_HW_FW_ EXPORTED_VALUES_CONF_LOCK_1[k] CONTROL_CORE_L3_HW_FW_ EXPORTED_VALUES_CONF_LOCK_2[j] |
INITIATOR_ PERMISSION | All | 0xFFFFFFFF | Tied | Configurable | MRM_PERMISSION_REGION_HIGH_j[31:0] | N/A |
For the values of k and j see Table 14-22, Table 14-13 and Table 14-14.
Variable Value | Module Name | Regions |
---|---|---|
k | ||
[0] | GPMC | 8 |
[3] | OCMC RAM1 | 16 |
[4] | DSS | 8 |
[6] | GPU | 1 |
[7] | IVAHD SL2IF | 4 |
[8] | IVAHD CONFIG | 1 |
[11] | EMIF | 8 |
[12] | DEBUGSS | 1 |
[13] | CT_TBR | 1 |
[16] | EVE1 | 1 |
[17] | EVE2 | 1 |
[20] | PCIESS1 | 8 |
[21] | PCIESS2 | 8 |
[22] | IPU1 | 4 |
[23] | IPU2 | 4 |
[24] | VCP1 | 1 |
[25] | VCP2 | 1 |
[26] | McASP1 | 1 |
[27] | McASP2 | 1 |
[28] | McASP3 | 1 |
[31] | BB2D | 1 |
j | ||
0 | DSP1 | 1 |
1 | DSP2 | 1 |
2 | OCMC RAM2 | 16 |
3 | OCMC RAM3 | 16 |
8 | QSPI | 1 |
9 | EDMA TC | 1 |
10 | EDMA TPCC | 1 |