SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
Table 26-6 lists the DPLL_SATA recommended values.
Field Name | Value | Description |
---|---|---|
DPLLCTRL_SATA.PLL_CONFIGURATION1[20:9] PLL_REGM | See (1). | Feedback clock divider |
DPLLCTRL_SATA.PLL_CONFIGURATION1[8:1] PLL_REGN | See (1). | Reference clock divider |
DPLLCTRL_SATA.PLL_CONFIGURATION2[10:9] PLL_LOCKSEL | 0x- | Criteria to lock the PLL |
DPLLCTRL_SATA.PLL_CONFIGURATION2[3:1] PLL_SELFREQDCO | See (1). | Program based on the PLL choice and lock frequency. |
DPLLCTRL_SATA.PLL_CONFIGURATION2[0] PLL_IDLE | 0 | PLL active |
DPLLCTRL_SATA.PLL_CONFIGURATION3[17:10] PLL_SD | See (1). | Ceiling { [PLL_REGM/(PLL_REGN + 1)] × CLKINP(MHz)/256 } |
DPLLCTRL_SATA.PLL_GO[0] PLL_GO | 0x1 | Write 1 when PLL is to be (re)locked with new parameters. This bit is cleared by hardware when the PLL request completes. |