SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The following programming model explains how to program the module to receive the IrDA frame with no parity, baud rate = 4 Mbps, FIFOs enabled, 8-bit word length.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Disable UART mode | UART_MDR1[2:0] MODE_SELECT | 0x7 |
Grant access to the UART_DLL and UART_DLH registers | UART_LCR[7:0] | 0x80 |
Enable access to change UART_FCR[0] | UART_DLL[7:0] CLOCK_LSB | 0x0 |
UART_DLH[7:0] CLOCK_MSB | ||
FIFO clear and enable | UART_FCR[2:0] | 0x7 |
Set the FIFO trigger level | see Section 24.3.5.4, Load FIFO trigger and DMA mode settings | |
Set FIR mode | UART_MDR1[2:0] MODE_SELECT | 0x5 |
Set frame length | UART_RXFLL[7:0] RXFLL | 0xA |
Disable access to the UART_DLL and UART_DLH registers | UART_LCR[7:0] | 0x00 |
Enable the UART_RHR interrupt | UART_IER_IRDA[0] RHR_IT | 1 |