SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
A single-bit mode can be entered by setting the appropriate bit in the control and status register (ONE_WIRE_SINGLE_BIT bit HDQ_CTRL_STATUS[7]). In this mode, only one bit of data at a time is transferred between the master and the slave. After the bit is transferred, an interrupt is generated (that is, there is an RX-complete for a read operation and a TX-complete for a write operation). The ONE_WIRE_SINGLE_BIT bit is cleared by hardware after every single bit is received. Software must set this bit to re-enable reception in single-bit mode. Bit 0 of the RX register (HDQ_RX_DATA) is updated each time a bit is received from the slave; bit 0 of the TX register (HDQ_TX_DATA) contains the bit to be sent.