SPRUI30H November   2015  – May 2024 DRA745 , DRA746 , DRA750 , DRA756

 

  1.   1
  2.   Read This First
    1.     Support Resources
    2.     Glossary
    3.     About This Manual
    4.     Information About Cautions and Warnings
    5.     Register, Field, and Bit Calls
    6.     Coding Rules
    7.     Flow Chart Rules
    8.     Export Control Notice
    9.     DRA75x, DRA74x MIPI® Disclaimer
    10.     Trademarks
  3. 1 Introduction
    1. 1.1 DRA75x, DRA74x Overview
    2. 1.2 DRA75x, DRA74x Environment
    3. 1.3 DRA75x, DRA74x Description
      1. 1.3.1  MPU Subsystem
      2. 1.3.2  DSP Subsystems
      3. 1.3.3  EVE Subsystems
      4. 1.3.4  IPU Subsystems
      5. 1.3.5  IVA-HD Subsystem
      6. 1.3.6  Display Subsystem
      7. 1.3.7  Video Processing Subsystem
      8. 1.3.8  Video Capture
      9. 1.3.9  3D GPU Subsystem
      10. 1.3.10 BB2D Subsystem
      11. 1.3.11 On-Chip Debug Support
      12. 1.3.12 Power, Reset, and Clock Management
      13. 1.3.13 On-Chip Memory
      14. 1.3.14 Memory Management
      15. 1.3.15 External Memory Interfaces
      16. 1.3.16 System and Connectivity Peripherals
        1. 1.3.16.1 System Peripherals
        2. 1.3.16.2 Media Connectivity Peripherals
        3. 1.3.16.3 Car Connectivity Peripherals
        4. 1.3.16.4 Audio Connectivity Peripherals
        5. 1.3.16.5 Serial Control Peripherals
        6. 1.3.16.6 Radio Accelerators
    4. 1.4 DRA75x, DRA74x Family
    5. 1.5 DRA75x, DRA74x Device Identification
    6. 1.6 DRA75x, DRA74x Package Characteristics Overview
  4. 2 Memory Mapping
    1. 2.1 Introduction
    2. 2.2 L3_MAIN Memory Map
      1. 2.2.1 L3_INSTR Memory Map
    3. 2.3 L4 Memory Map
      1. 2.3.1 L4_CFG Memory Map
      2. 2.3.2 L4_WKUP Memory Map
    4. 2.4 L4_PER Memory Map
      1. 2.4.1 L4_PER1 Memory Space Mapping
      2. 2.4.2 L4_PER2 Memory Map
      3. 2.4.3 L4_PER3 Memory Map
    5. 2.5 MPU Memory Map
    6. 2.6 IPU Memory Map
    7. 2.7 DSP Memory Map
    8. 2.8 EVE Memory Map
    9. 2.9 TILER View Memory Map
  5. 3 Power, Reset, and Clock Management
    1. 3.1  Device Power Management Introduction
      1. 3.1.1 Device Power-Management Architecture Building Blocks
        1. 3.1.1.1 Clock Management
          1. 3.1.1.1.1 Module Interface and Functional Clocks
          2. 3.1.1.1.2 63
          3. 3.1.1.1.3 Module-Level Clock Management
          4. 3.1.1.1.4 Clock Domain
          5. 3.1.1.1.5 Clock Domain-Level Clock Management
          6. 3.1.1.1.6 Clock Domain HW_AUTO Mode Sequences
          7. 3.1.1.1.7 Clock Domain Sleep/Wake-up
          8. 3.1.1.1.8 Clock Domain Dependency
            1. 3.1.1.1.8.1 Static Dependency
            2. 3.1.1.1.8.2 Dynamic Dependency
            3. 3.1.1.1.8.3 Wake-Up Dependency
        2. 3.1.1.2 Power Management
          1. 3.1.1.2.1 Power Domain
          2. 3.1.1.2.2 Module Logic and Memory Context
          3. 3.1.1.2.3 Power Domain Management
        3. 3.1.1.3 Voltage Management
          1. 3.1.1.3.1 Voltage Domain
          2. 3.1.1.3.2 Voltage Domain Management
          3. 3.1.1.3.3 AVS Overview
            1. 3.1.1.3.3.1 AVS Class 0 (SmartReflex™) Voltage Control
      2. 3.1.2 Power-Management Techniques
        1. 3.1.2.1 Standby Leakage Management
        2. 3.1.2.2 Dynamic Voltage and Frequency Scaling
        3. 3.1.2.3 Dynamic Power Switching
        4. 3.1.2.4 Adaptive Voltage Scaling
        5. 3.1.2.5 Adaptive Body Bias
        6. 3.1.2.6 SR3-APG (Automatic Power Gating)
        7. 3.1.2.7 Combining Power-Management Techniques
          1. 3.1.2.7.1 DPS Versus SLM
    2. 3.2  PRCM Subsystem Overview
      1. 3.2.1 Introduction
      2. 3.2.2 Power-Management Framework Features
    3. 3.3  PRCM Subsystem Environment
      1. 3.3.1 External Clock Signals
      2. 3.3.2 External Boot Signals
      3. 3.3.3 External Reset Signals
      4. 3.3.4 External Voltage Inputs
    4. 3.4  PRCM Subsystem Integration
      1. 3.4.1 Device Power-Management Layout
      2. 3.4.2 Power-Management Scheme, Reset, and Interrupt Requests
        1. 3.4.2.1 Power Domain
        2. 3.4.2.2 Resets
        3. 3.4.2.3 PRCM Interrupt Requests
        4. 3.4.2.4 105
    5. 3.5  Reset Management Functional Description
      1. 3.5.1 Overview
        1. 3.5.1.1 PRCM Reset Management Functional Description
          1. 3.5.1.1.1 Power-On Reset
          2. 3.5.1.1.2 Warm Reset
        2. 3.5.1.2 PRM Reset Management Functional Description
      2. 3.5.2 General Characteristics of Reset Signals
        1. 3.5.2.1 Scope
        2. 3.5.2.2 Occurrence
        3. 3.5.2.3 Source Type
        4. 3.5.2.4 Retention Type
      3. 3.5.3 Reset Sources
        1. 3.5.3.1 Global Reset Sources
        2. 3.5.3.2 Local Reset Sources
      4. 3.5.4 Reset Logging
      5. 3.5.5 Reset Domains
      6. 3.5.6 Reset Sequences
        1. 3.5.6.1  MPU Subsystem Power-On Reset Sequence
        2. 3.5.6.2  MPU Subsystem Warm Reset Sequence
        3. 3.5.6.3  MPU Subsystem Reset Sequence on Sleep and Wake-Up Transitions From RETENTION State
        4. 3.5.6.4  IVA Subsystem Power-On Reset Sequence
        5. 3.5.6.5  IVA Subsystem Software Warm Reset Sequence
        6. 3.5.6.6  DSP1 Subsystem Power-On Reset Sequence
        7. 3.5.6.7  DSP1 Subsystem Software Warm Reset Sequence
        8. 3.5.6.8  DSP2 Subsystem Power-On Reset Sequence
        9. 3.5.6.9  DSP2 Subsystem Software Warm Reset Sequence
        10. 3.5.6.10 IPU1 Subsystem Power-On Reset Sequence
        11. 3.5.6.11 IPU1 Subsystem Software Warm Reset Sequence
        12. 3.5.6.12 IPU2 Subsystem Power-On Reset Sequence
        13. 3.5.6.13 IPU2 Subsystem Software Warm Reset Sequence
        14. 3.5.6.14 EVE1 Subsystem Power-On Reset Sequence
        15. 3.5.6.15 EVE1 Subsystem Software Warm Reset Sequence
        16. 3.5.6.16 EVE2 Subsystem Power-On Reset Sequence
        17. 3.5.6.17 EVE2 Subsystem Software Warm Reset Sequence
        18. 3.5.6.18 Global Warm Reset Sequence
    6. 3.6  Clock Management Functional Description
      1. 3.6.1 Overview
      2. 3.6.2 External Clock Inputs
        1. 3.6.2.1 FUNC_32K_CLK Clock
        2. 3.6.2.2 High-Frequency System Clock Input
        3. 3.6.2.3 External Reference Clock Input
      3. 3.6.3 Internal Clock Sources and Generators
        1. 3.6.3.1  PRM Clock Source
        2. 3.6.3.2  CM Clock Source
          1. 3.6.3.2.1 CM_CORE_AON Clock Generator
          2. 3.6.3.2.2 CM_CORE_AON_CLKOUTMUX Overview
          3. 3.6.3.2.3 CM_CORE_AON_TIMER Overview
          4. 3.6.3.2.4 CM_CORE_AON_MCASP Overview
        3. 3.6.3.3  Generic DPLL Overview
          1. 3.6.3.3.1 Generic APLL Overview
          2. 3.6.3.3.2 DPLLs Output Clocks Parameters
          3. 3.6.3.3.3 Enable Control, Status, and Low-Power Operation Mode
          4. 3.6.3.3.4 DPLL Power Modes
          5. 3.6.3.3.5 DPLL Recalibration
          6. 3.6.3.3.6 DPLL Output Power Down
        4. 3.6.3.4  DPLL_PER Description
          1. 3.6.3.4.1 DPLL_PER Overview
          2. 3.6.3.4.2 DPLL_PER Synthesized Clock Parameters
          3. 3.6.3.4.3 DPLL_PER Power Modes
          4. 3.6.3.4.4 DPLL_PER Recalibration
        5. 3.6.3.5  DPLL_CORE Description
          1. 3.6.3.5.1 DPLL_CORE Overview
          2. 3.6.3.5.2 DPLL_CORE Synthesized Clock Parameters
          3. 3.6.3.5.3 DPLL_CORE Power Modes
          4. 3.6.3.5.4 DPLL_CORE Recalibration
        6. 3.6.3.6  DPLL_ABE Description
          1. 3.6.3.6.1 DPLL_ABE Overview
          2. 3.6.3.6.2 DPLL_ABE Synthesized Clock Parameters
          3. 3.6.3.6.3 DPLL_ABE Power Modes
          4. 3.6.3.6.4 DPLL_ABE Recalibration
        7. 3.6.3.7  DPLL_MPU Description
          1. 3.6.3.7.1 DPLL_MPU Overview
          2. 3.6.3.7.2 DPLL_MPU Tactical Clocking Adjustment
          3. 3.6.3.7.3 DPLL_MPU Synthesized Clock Parameters
          4. 3.6.3.7.4 DPLL_MPU Power Modes
          5. 3.6.3.7.5 DPLL_MPU Recalibration
        8. 3.6.3.8  DPLL_IVA Description
          1. 3.6.3.8.1 DPLL_IVA Overview
          2. 3.6.3.8.2 DPLL_IVA Synthesized Clock Parameters
          3. 3.6.3.8.3 DPLL_IVA Power Modes
          4. 3.6.3.8.4 DPLL_IVA Recalibration
        9. 3.6.3.9  DPLL_USB Description
          1. 3.6.3.9.1 DPLL_USB Overview
          2. 3.6.3.9.2 DPLL_USB Synthesized Clock Parameters
          3. 3.6.3.9.3 DPLL_USB Power Modes
          4. 3.6.3.9.4 DPLL_USB Recalibration
        10. 3.6.3.10 DPLL_EVE Description
          1. 3.6.3.10.1 DPLL_EVE Overview
          2. 3.6.3.10.2 DPLL_EVE Synthesized Clock Parameters
          3. 3.6.3.10.3 DPLL_EVE Power Modes
          4. 3.6.3.10.4 DPLL_EVE Recalibration
        11. 3.6.3.11 DPLL_DSP Description
          1. 3.6.3.11.1 DPLL_DSP Overview
          2. 3.6.3.11.2 DPLL_DSP Synthesized Clock Parameters
          3. 3.6.3.11.3 DPLL_DSP Power Modes
          4. 3.6.3.11.4 DPLL_DSP Recalibration
        12. 3.6.3.12 DPLL_GMAC Description
          1. 3.6.3.12.1 DPLL_GMAC Overview
          2. 3.6.3.12.2 DPLL_GMAC Synthesized Clock Parameters
          3. 3.6.3.12.3 DPLL_GMAC Power Modes
          4. 3.6.3.12.4 DPLL_GMAC Recalibration
        13. 3.6.3.13 DPLL_GPU Description
          1. 3.6.3.13.1 DPLL_GPU Overview
          2. 3.6.3.13.2 DPLL_GPU Synthesized Clock Parameters
          3. 3.6.3.13.3 DPLL_GPU Power Modes
          4. 3.6.3.13.4 DPLL_GPU Recalibration
        14. 3.6.3.14 DPLL_DDR Description
          1. 3.6.3.14.1 DPLL_DDR Overview
          2. 3.6.3.14.2 DPLL_DDR Synthesized Clock Parameters
          3. 3.6.3.14.3 DPLL_DDR Power Modes
          4. 3.6.3.14.4 DPLL_DDR Recalibration
        15. 3.6.3.15 DPLL_PCIE_REF Description
          1. 3.6.3.15.1 DPLL_PCIE_REF Overview
          2. 3.6.3.15.2 DPLL_PCIE_REF Synthesized Clock Parameters
          3. 3.6.3.15.3 DPLL_PCIE_REF Power Modes
        16. 3.6.3.16 APLL_PCIE Description
          1. 3.6.3.16.1 APLL_PCIE Overview
          2. 3.6.3.16.2 APLL_PCIE Synthesized Clock Parameters
          3. 3.6.3.16.3 APLL_PCIE Power Modes
      4. 3.6.4 Clock Domains
        1. 3.6.4.1  CD_WKUPAON Clock Domain
          1. 3.6.4.1.1 Overview
          2. 3.6.4.1.2 Clock Domain Modes
          3. 3.6.4.1.3 Clock Domain Dependency
            1. 3.6.4.1.3.1 Wake-Up Dependency
          4. 3.6.4.1.4 Clock Domain Module Attributes
        2. 3.6.4.2  CD_DSP1 Clock Domain
          1. 3.6.4.2.1 Overview
          2. 3.6.4.2.2 Clock Domain Modes
          3. 3.6.4.2.3 Clock Domain Dependency
            1. 3.6.4.2.3.1 Static Dependency
            2. 3.6.4.2.3.2 Dynamic Dependency
          4. 3.6.4.2.4 Clock Domain Module Attributes
        3. 3.6.4.3  CD_DSP2 Clock Domain
          1. 3.6.4.3.1 Overview
          2. 3.6.4.3.2 Clock Domain Modes
          3. 3.6.4.3.3 Clock Domain Dependency
            1. 3.6.4.3.3.1 Static Dependency
            2. 3.6.4.3.3.2 Dynamic Dependency
          4. 3.6.4.3.4 Clock Domain Module Attributes
        4. 3.6.4.4  CD_CUSTEFUSE Clock Domain
          1. 3.6.4.4.1 Overview
          2. 3.6.4.4.2 Clock Domain Modes
          3. 3.6.4.4.3 Clock Domain Dependency
          4. 3.6.4.4.4 Clock Domain Module Attributes
        5. 3.6.4.5  CD_MPU Clock Domain
          1. 3.6.4.5.1 Overview
          2. 3.6.4.5.2 Clock Domain Modes
          3. 3.6.4.5.3 Clock Domain Dependency
            1. 3.6.4.5.3.1 Static Dependency
            2. 3.6.4.5.3.2 Dynamic Dependency
          4. 3.6.4.5.4 Clock Domain Module Attributes
        6. 3.6.4.6  CD_L4PER1 Clock Domain
          1. 3.6.4.6.1 Overview
          2. 3.6.4.6.2 Clock Domain Modes
          3. 3.6.4.6.3 Clock Domain Dependency
            1. 3.6.4.6.3.1 Dynamic Dependency
            2. 3.6.4.6.3.2 Wake-Up Dependency
          4. 3.6.4.6.4 Clock Domain Module Attributes
        7. 3.6.4.7  CD_L4PER2 Clock Domain
          1. 3.6.4.7.1 Overview
          2. 3.6.4.7.2 Clock Domain Modes
          3. 3.6.4.7.3 Clock Domain Dependency
            1. 3.6.4.7.3.1 Dynamic Dependency
            2. 3.6.4.7.3.2 Wake-Up Dependency
          4. 3.6.4.7.4 Clock Domain Module Attributes
        8. 3.6.4.8  CD_L4PER3 Clock Domain
          1. 3.6.4.8.1 Overview
          2. 3.6.4.8.2 Clock Domain Modes
          3. 3.6.4.8.3 Clock Domain Dependency
            1. 3.6.4.8.3.1 Dynamic Dependency
            2. 3.6.4.8.3.2 Wake-Up Dependency
          4. 3.6.4.8.4 Clock Domain Module Attributes
        9. 3.6.4.9  CD_L4SEC Clock Domain
          1. 3.6.4.9.1 Overview
          2. 3.6.4.9.2 Clock Domain Modes
          3. 3.6.4.9.3 Clock Domain Dependency
            1. 3.6.4.9.3.1 Static Dependency
            2. 3.6.4.9.3.2 Dynamic Dependency
          4. 3.6.4.9.4 Clock Domain Module Attributes
          5. 3.6.4.9.5 286
        10. 3.6.4.10 CD_L3INIT Clock Domain
          1. 3.6.4.10.1 Overview
          2. 3.6.4.10.2 Clock Domain Modes
          3. 3.6.4.10.3 Clock Domain Dependency
            1. 3.6.4.10.3.1 Static Dependency
            2. 3.6.4.10.3.2 Dynamic Dependency
            3. 3.6.4.10.3.3 Wake-Up Dependency
          4. 3.6.4.10.4 Clock Domain Module Attributes
        11. 3.6.4.11 CD_IVA Clock Domain
          1. 3.6.4.11.1 Overview
          2. 3.6.4.11.2 Clock Domain Modes
          3. 3.6.4.11.3 Clock Domain Dependency
            1. 3.6.4.11.3.1 Static Dependency
            2. 3.6.4.11.3.2 Dynamic Dependency
          4. 3.6.4.11.4 Clock Domain Module Attributes
        12. 3.6.4.12 CD_GPU Description
          1. 3.6.4.12.1 Overview
          2. 3.6.4.12.2 Clock Domain Modes
          3. 3.6.4.12.3 Clock Domain Dependency
            1. 3.6.4.12.3.1 Static Dependency
            2. 3.6.4.12.3.2 Dynamic Dependency
          4. 3.6.4.12.4 Clock Domain Module Attributes
        13. 3.6.4.13 CD_EMU Clock Domain
          1. 3.6.4.13.1 Overview
          2. 3.6.4.13.2 Clock Domain Modes
          3. 3.6.4.13.3 Clock Domain Dependency
            1. 3.6.4.13.3.1 Dynamic Dependency
          4. 3.6.4.13.4 Clock Domain Module Attributes
        14. 3.6.4.14 CD_DSS Clock Domain
          1. 3.6.4.14.1 Overview
          2. 3.6.4.14.2 Clock Domain Modes
          3. 3.6.4.14.3 Clock Domain Dependency
            1. 3.6.4.14.3.1 Static Dependency
            2. 3.6.4.14.3.2 Dynamic Dependency
            3. 3.6.4.14.3.3 Wake-Up Dependency
          4. 3.6.4.14.4 Clock Domain Module Attributes
        15. 3.6.4.15 CD_L4_CFG Clock Domain
          1. 3.6.4.15.1 Overview
          2. 3.6.4.15.2 Clock Domain Modes
          3. 3.6.4.15.3 Clock Domain Dependency
            1. 3.6.4.15.3.1 Dynamic Dependency
          4. 3.6.4.15.4 Clock Domain Module Attributes
        16. 3.6.4.16 CD_L3_INSTR Clock Domain
          1. 3.6.4.16.1 Overview
          2. 3.6.4.16.2 Clock Domain Modes
          3. 3.6.4.16.3 Clock Domain Dependency
          4. 3.6.4.16.4 Clock Domain Module Attributes
        17. 3.6.4.17 CD_L3_MAIN1 Clock Domain
          1. 3.6.4.17.1 Overview
          2. 3.6.4.17.2 Clock Domain Modes
          3. 3.6.4.17.3 Clock Domain Dependency
            1. 3.6.4.17.3.1 Dynamic Dependency
          4. 3.6.4.17.4 Clock Domain Module Attributes
        18. 3.6.4.18 CD_EMIF Clock Domain
          1. 3.6.4.18.1 Overview
          2. 3.6.4.18.2 Clock Domain Modes
          3. 3.6.4.18.3 Clock Domain Dependency
          4. 3.6.4.18.4 Clock Domain Module Attributes
        19. 3.6.4.19 CD_IPU Clock Domain
          1. 3.6.4.19.1 Overview
          2. 3.6.4.19.2 Clock Domain Modes
          3. 3.6.4.19.3 Clock Domain Dependency
            1. 3.6.4.19.3.1 Static Dependency
            2. 3.6.4.19.3.2 Dynamic Dependency
          4. 3.6.4.19.4 Clock Domain Module Attributes
        20. 3.6.4.20 CD_IPU1 Clock Domain
          1. 3.6.4.20.1 Overview
          2. 3.6.4.20.2 Clock Domain Modes
          3. 3.6.4.20.3 Clock Domain Dependency
            1. 3.6.4.20.3.1 Static Dependency
            2. 3.6.4.20.3.2 Dynamic Dependency
          4. 3.6.4.20.4 Clock Domain Module Attributes
        21. 3.6.4.21 CD_IPU2 Clock Domain
          1. 3.6.4.21.1 Overview
          2. 3.6.4.21.2 Clock Domain Modes
          3. 3.6.4.21.3 Clock Domain Dependency
            1. 3.6.4.21.3.1 Static Dependency
            2. 3.6.4.21.3.2 Dynamic Dependency
          4. 3.6.4.21.4 Clock Domain Module Attributes
        22. 3.6.4.22 CD_DMA Clock Domain
          1. 3.6.4.22.1 Overview
          2. 3.6.4.22.2 Clock Domain Modes
          3. 3.6.4.22.3 Clock Domain Dependency
            1. 3.6.4.22.3.1 Static Dependency
            2. 3.6.4.22.3.2 Dynamic Dependency
          4. 3.6.4.22.4 Clock Domain Module Attributes
        23. 3.6.4.23 CD_ATL Clock Domain
          1. 3.6.4.23.1 Overview
          2. 3.6.4.23.2 Clock Domain Modes
          3. 3.6.4.23.3 Clock Domain Module Attributes
        24. 3.6.4.24 CD_CAM Clock Domain
          1. 3.6.4.24.1 Overview
          2. 3.6.4.24.2 Clock Domain Modes
          3. 3.6.4.24.3 Clock Domain Dependency
            1. 3.6.4.24.3.1 Static Dependency
            2. 3.6.4.24.3.2 Dynamic Dependency
          4. 3.6.4.24.4 Clock Domain Module Attributes
          5. 3.6.4.24.5 384
        25. 3.6.4.25 CD_GMAC Clock Domain
          1. 3.6.4.25.1 Overview
          2. 3.6.4.25.2 Clock Domain Modes
          3. 3.6.4.25.3 Clock Domain Dependency
            1. 3.6.4.25.3.1 Static Dependency
            2. 3.6.4.25.3.2 Dynamic Dependency
          4. 3.6.4.25.4 Clock Domain Module Attributes
        26. 3.6.4.26 CD_VPE Clock Domain
          1. 3.6.4.26.1 CD_VPE Overview
          2. 3.6.4.26.2 Clock Domain Modes
          3. 3.6.4.26.3 Clock Domain Dependency
            1. 3.6.4.26.3.1 Wake-Up Dependency
          4. 3.6.4.26.4 Clock Domain Module Attributes
        27. 3.6.4.27 CD_EVE1 Clock Domain
          1. 3.6.4.27.1 CD_EVE1 Overview
          2. 3.6.4.27.2 Clock Domain Modes
          3. 3.6.4.27.3 Clock Domain Dependency
            1. 3.6.4.27.3.1 Wake-Up Dependency
          4. 3.6.4.27.4 Clock Domain Module Attributes
        28. 3.6.4.28 CD_EVE2 Clock Domain
          1. 3.6.4.28.1 CD_EVE2 Overview
          2. 3.6.4.28.2 Clock Domain Modes
          3. 3.6.4.28.3 Clock Domain Dependency
            1. 3.6.4.28.3.1 Wake-Up Dependency
          4. 3.6.4.28.4 Clock Domain Module Attributes
        29. 3.6.4.29 CD_RTC Clock Domain
          1. 3.6.4.29.1 CD_RTC Overview
          2. 3.6.4.29.2 Clock Domain Modes
          3. 3.6.4.29.3 Clock Domain Dependency
            1. 3.6.4.29.3.1 Wake-Up Dependency
          4. 3.6.4.29.4 Clock Domain Module Attributes
        30. 3.6.4.30 CD_PCIE Clock Domain
          1. 3.6.4.30.1 CD_PCIE Overview
          2. 3.6.4.30.2 Clock Domain Modes
          3. 3.6.4.30.3 Clock Domain Dependency
            1. 3.6.4.30.3.1 Wake-Up Dependency
          4. 3.6.4.30.4 Clock Domain Module Attributes
    7. 3.7  Power Management Functional Description
      1. 3.7.1  PD_WKUPAON Description
        1. 3.7.1.1 Power Domain Modes
          1. 3.7.1.1.1 Logic and Memory Area Power Modes
      2. 3.7.2  PD_DSP1 Description
        1. 3.7.2.1 Power Domain Modes
          1. 3.7.2.1.1 Logic and Memory Area Power Modes
          2. 3.7.2.1.2 Logic and Memory Area Power Modes Control and Status
      3. 3.7.3  PD_DSP2 Description
        1. 3.7.3.1 Power Domain Modes
          1. 3.7.3.1.1 Logic and Memory Area Power Modes
          2. 3.7.3.1.2 Logic and Memory Area Power Modes Control and Status
      4. 3.7.4  PD_CUSTEFUSE Description
        1. 3.7.4.1 Power Domain Modes
          1. 3.7.4.1.1 Logic and Memory Area Power Modes
          2. 3.7.4.1.2 Logic and Memory Area Power Modes Control and Status
      5. 3.7.5  PD_MPU Description
        1. 3.7.5.1 Power Domain Modes
          1. 3.7.5.1.1 Logic and Memory Area Power Modes
          2. 3.7.5.1.2 Logic and Memory Area Power Modes Control and Status
          3. 3.7.5.1.3 Power State Override
      6. 3.7.6  PD_IPU Description
        1. 3.7.6.1 Power Domain Modes
          1. 3.7.6.1.1 Logic and Memory Area Power Modes
          2. 3.7.6.1.2 Logic and Memory Area Power Modes Control and Status
      7. 3.7.7  PD_L3INIT Description
        1. 3.7.7.1 Power Domain Modes
          1. 3.7.7.1.1 Logic and Memory Area Power Modes
          2. 3.7.7.1.2 Logic and Memory Area Power Modes Control and Status
      8. 3.7.8  PD_L4PER Description
        1. 3.7.8.1 Power Domain Modes
          1. 3.7.8.1.1 Logic and Memory Area Power Modes
          2. 3.7.8.1.2 Logic and Memory Area Power Modes Control and Status
      9. 3.7.9  PD_IVA Description
        1. 3.7.9.1 Power Domain Modes
          1. 3.7.9.1.1 Logic and Memory Area Power Modes
          2. 3.7.9.1.2 Logic and Memory Area Power Modes Control and Status
      10. 3.7.10 PD_GPU Description
        1. 3.7.10.1 Power Domain Modes
          1. 3.7.10.1.1 Logic and Memory Area Power Modes
          2. 3.7.10.1.2 Logic and Memory Area Power Modes Control and Status
      11. 3.7.11 PD_EMU Description
        1. 3.7.11.1 Power Domain Modes
          1. 3.7.11.1.1 Logic and Memory Area Power Modes
          2. 3.7.11.1.2 Logic and Memory Area Power Modes Control and Status
      12. 3.7.12 PD_DSS Description
        1. 3.7.12.1 Power Domain Modes
          1. 3.7.12.1.1 Logic and Memory Area Power Modes
          2. 3.7.12.1.2 Logic and Memory Area Power Mode Control and Status
      13. 3.7.13 PD_CORE Description
        1. 3.7.13.1 Power Domain Modes
          1. 3.7.13.1.1 Logic and Memory Area Power Modes
          2. 3.7.13.1.2 Logic and Memory Area Power Mode Control and Status
      14. 3.7.14 PD_CAM Description
        1. 3.7.14.1 Power Domain Modes
          1. 3.7.14.1.1 Logic and Memory Area Power Modes
          2. 3.7.14.1.2 Logic and Memory Area Power Mode Control and Status
      15. 3.7.15 PD_MPUAON Description
        1. 3.7.15.1 Power Domain Modes
      16. 3.7.16 PD_MMAON Description
        1. 3.7.16.1 Power Domain Modes
      17. 3.7.17 PD_COREAON Description
        1. 3.7.17.1 Power Domain Modes
      18. 3.7.18 PD_VPE Description
        1. 3.7.18.1 Power Domain Modes
          1. 3.7.18.1.1 Logic and Memory Area Power Modes
          2. 3.7.18.1.2 Logic and Memory Area Power Modes Control and Status
      19. 3.7.19 PD_EVE1 Description
        1. 3.7.19.1 Power Domain Modes
          1. 3.7.19.1.1 Logic and Memory Area Power Modes
          2. 3.7.19.1.2 Logic and Memory Area Power Modes Control and Status
      20. 3.7.20 PD_EVE2 Description
        1. 3.7.20.1 Power Domain Modes
          1. 3.7.20.1.1 Logic and Memory Area Power Modes
          2. 3.7.20.1.2 Logic and Memory Area Power Modes Control and Status
      21. 3.7.21 PD_RTC Description
        1. 3.7.21.1 Power Domain Modes
          1. 3.7.21.1.1 Logic and Memory Area Power Modes
    8. 3.8  Voltage-Management Functional Description
      1. 3.8.1 Overview
      2. 3.8.2 Voltage-Control Architecture
      3. 3.8.3 Internal LDOs Control
        1. 3.8.3.1 VDD_MPU_L, VDD_CORE_L, and VDD_IVAHD_L, VDD_GPU_L, VDD_DSPEVE_L Control
          1. 3.8.3.1.1 Adaptive Voltage Scaling
            1. 3.8.3.1.1.1 SmartReflex in the Device
        2. 3.8.3.2 Memory LDOs
        3. 3.8.3.3 ABB LDOs Control
        4. 3.8.3.4 ABB LDO Programming Sequence
          1. 3.8.3.4.1 ABB LDO Enable Sequence
          2. 3.8.3.4.2 ABB LDO Disable Sequence (Entering in Bypass Mode)
        5. 3.8.3.5 BANDGAPs Control
      4. 3.8.4 DVFS
    9. 3.9  Device Low-Power States
      1. 3.9.1 Device Wake-Up Source Summary
      2. 3.9.2 Wakeup Upon Global Warm Reset
      3. 3.9.3 Global Warm Reset During a Device Wake-Up Sequence
      4. 3.9.4 I/O Management
        1. 3.9.4.1 Isolation / Wakeup Sequence
          1. 3.9.4.1.1 Software-Controlled I/O Isolation
    10. 3.10 PRCM Module Programming Guide
      1. 3.10.1 DPLLs Low-Level Programming Models
        1. 3.10.1.1 Global Initialization
          1. 3.10.1.1.1 Surrounding Module Global Initialization
          2. 3.10.1.1.2 DPLL Global Initialization
            1. 3.10.1.1.2.1 Main Sequence – DPLL Global Initialization
            2. 3.10.1.1.2.2 Subsequence – Recalibration Parameter Configuration
            3. 3.10.1.1.2.3 Subsequence – Synthesized Clock Parameter Configuration
            4. 3.10.1.1.2.4 Subsequence – Output Clock Parameter Configuration
        2. 3.10.1.2 DPLL Output Frequency Change
      2. 3.10.2 Clock Management Low-Level Programming Models
        1. 3.10.2.1 Global Initialization
          1. 3.10.2.1.1 Surrounding Module Global Initialization
          2. 3.10.2.1.2 Clock Management Global Initialization
            1. 3.10.2.1.2.1 Main Sequence – Clock Domain Global Initialization
            2. 3.10.2.1.2.2 Subsequence – Slave Module Clock-Management Parameters Configuration
        2. 3.10.2.2 Clock Domain Sleep Transition and Troubleshooting
        3. 3.10.2.3 Enable/Disable Software-Programmable Static Dependency
      3. 3.10.3 Power Management Low-Level Programming Models
        1. 3.10.3.1 Global Initialization
          1. 3.10.3.1.1 Surrounding Module Global Initialization
          2. 3.10.3.1.2 Power Management Global Initialization
            1. 3.10.3.1.2.1 Main Sequence – Power Domain Global Initialization and Setting
        2. 3.10.3.2 Forced Memory Area State Change With Power Domain ON
        3. 3.10.3.3 Forced Power Domain Low-Power State Transition
    11. 3.11 546
    12. 3.12 PRCM Software Configuration for OPP_PLUS
    13. 3.13 PRCM Register Manual
      1. 3.13.1  PRCM Instance Summary
      2. 3.13.2  CM_CORE_AON__CKGEN Registers
        1. 3.13.2.1 CM_CORE_AON__CKGEN Register Summary
        2. 3.13.2.2 CM_CORE_AON__CKGEN Register Description
      3. 3.13.3  CM_CORE_AON__DSP1 Registers
        1. 3.13.3.1 CM_CORE_AON__DSP1 Register Summary
        2. 3.13.3.2 CM_CORE_AON__DSP1 Register Description
      4. 3.13.4  CM_CORE_AON__DSP2 Registers
        1. 3.13.4.1 CM_CORE_AON__DSP2 Register Summary
        2. 3.13.4.2 CM_CORE_AON__DSP2 Register Description
      5. 3.13.5  CM_CORE_AON__EVE1 Registers
        1. 3.13.5.1 CM_CORE_AON__EVE1 Register Summary
        2. 3.13.5.2 CM_CORE_AON__EVE1 Register Description
      6. 3.13.6  CM_CORE_AON__EVE2 Registers
        1. 3.13.6.1 CM_CORE_AON__EVE2 Register Summary
        2. 3.13.6.2 CM_CORE_AON__EVE2 Register Description
      7. 3.13.7  CM_CORE_AON__INSTR Registers
        1. 3.13.7.1 CM_CORE_AON__INSTR Register Summary
        2. 3.13.7.2 CM_CORE_AON__INSTR Register Description
      8. 3.13.8  CM_CORE_AON__IPU Registers
        1. 3.13.8.1 CM_CORE_AON__IPU Register Summary
        2. 3.13.8.2 CM_CORE_AON__IPU Register Description
      9. 3.13.9  CM_CORE_AON__MPU Registers
        1. 3.13.9.1 CM_CORE_AON__MPU Register Summary
        2. 3.13.9.2 CM_CORE_AON__MPU Register Description
      10. 3.13.10 CM_CORE_AON__OCP_SOCKET Registers
        1. 3.13.10.1 CM_CORE_AON__OCP_SOCKET Register Summary
        2. 3.13.10.2 CM_CORE_AON__OCP_SOCKET Register Description
      11. 3.13.11 CM_CORE_AON__RESTORE Registers
        1. 3.13.11.1 CM_CORE_AON__RESTORE Register Summary
        2. 3.13.11.2 CM_CORE_AON__RESTORE Register Description
      12. 3.13.12 CM_CORE_AON__RTC Registers
        1. 3.13.12.1 CM_CORE_AON__RTC Register Summary
        2. 3.13.12.2 CM_CORE_AON__RTC Register Description
      13. 3.13.13 CM_CORE_AON__VPE Registers
        1. 3.13.13.1 CM_CORE_AON__VPE Register Summary
        2. 3.13.13.2 CM_CORE_AON__VPE Register Description
      14. 3.13.14 CM_CORE__CAM Registers
        1. 3.13.14.1 CM_CORE__CAM Register Summary
        2. 3.13.14.2 CM_CORE__CAM Register Description
      15. 3.13.15 CM_CORE__CKGEN Registers
        1. 3.13.15.1 CM_CORE__CKGEN Register Summary
        2. 3.13.15.2 CM_CORE__CKGEN Register Description
      16. 3.13.16 CM_CORE__COREAON Registers
        1. 3.13.16.1 CM_CORE__COREAON Register Summary
        2. 3.13.16.2 CM_CORE__COREAON Register Description
      17. 3.13.17 CM_CORE__CORE Registers
        1. 3.13.17.1 CM_CORE__CORE Register Summary
        2. 3.13.17.2 CM_CORE__CORE Register Description
      18. 3.13.18 CM_CORE__CUSTEFUSE Registers
        1. 3.13.18.1 CM_CORE__CUSTEFUSE Register Summary
        2. 3.13.18.2 CM_CORE__CUSTEFUSE Register Description
      19. 3.13.19 CM_CORE__DSS Registers
        1. 3.13.19.1 CM_CORE__DSS Register Summary
        2. 3.13.19.2 CM_CORE__DSS Register Description
      20. 3.13.20 CM_CORE__GPU Registers
        1. 3.13.20.1 CM_CORE__GPU Register Summary
        2. 3.13.20.2 CM_CORE__GPU Register Description
      21. 3.13.21 CM_CORE__IVA Registers
        1. 3.13.21.1 CM_CORE__IVA Register Summary
        2. 3.13.21.2 CM_CORE__IVA Register Description
      22. 3.13.22 CM_CORE__L3INIT Registers
        1. 3.13.22.1 CM_CORE__L3INIT Register Summary
        2. 3.13.22.2 CM_CORE__L3INIT Register Description
      23. 3.13.23 CM_CORE__L4PER Registers
        1. 3.13.23.1 CM_CORE__L4PER Register Summary
        2. 3.13.23.2 CM_CORE__L4PER Register Description
      24. 3.13.24 CM_CORE__OCP_SOCKET Registers
        1. 3.13.24.1 CM_CORE__OCP_SOCKET Register Summary
        2. 3.13.24.2 CM_CORE__OCP_SOCKET Register Description
      25. 3.13.25 CM_CORE__RESTORE Registers
        1. 3.13.25.1 CM_CORE__RESTORE Register Summary
        2. 3.13.25.2 CM_CORE__RESTORE Register Description
      26. 3.13.26 CAM_PRM Registers
        1. 3.13.26.1 CAM_PRM Register Summary
        2. 3.13.26.2 CAM_PRM Register Description
      27. 3.13.27 CKGEN_PRM Registers
        1. 3.13.27.1 CKGEN_PRM Register Summary
        2. 3.13.27.2 CKGEN_PRM Register Description
      28. 3.13.28 CORE_PRM Registers
        1. 3.13.28.1 CORE_PRM Register Summary
        2. 3.13.28.2 CORE_PRM Register Description
      29. 3.13.29 CUSTEFUSE_PRM Registers
        1. 3.13.29.1 CUSTEFUSE_PRM Register Summary
        2. 3.13.29.2 CUSTEFUSE_PRM Register Description
      30. 3.13.30 DEVICE_PRM Registers
        1. 3.13.30.1 DEVICE_PRM Register Summary
        2. 3.13.30.2 DEVICE_PRM Register Description
      31. 3.13.31 DSP1_PRM Registers
        1. 3.13.31.1 DSP1_PRM Register Summary
        2. 3.13.31.2 DSP1_PRM Register Description
      32. 3.13.32 DSP2_PRM Registers
        1. 3.13.32.1 DSP2_PRM Register Summary
        2. 3.13.32.2 DSP2_PRM Register Description
      33. 3.13.33 DSS_PRM Registers
        1. 3.13.33.1 DSS_PRM Register Summary
        2. 3.13.33.2 DSS_PRM Register Description
      34. 3.13.34 EMU_CM Registers
        1. 3.13.34.1 EMU_CM Register Summary
        2. 3.13.34.2 EMU_CM Register Description
      35. 3.13.35 EMU_PRM Registers
        1. 3.13.35.1 EMU_PRM Register Summary
        2. 3.13.35.2 EMU_PRM Register Description
      36. 3.13.36 EVE1_PRM Registers
        1. 3.13.36.1 EVE1_PRM Register Summary
        2. 3.13.36.2 EVE1_PRM Register Description
      37. 3.13.37 EVE2_PRM Registers
        1. 3.13.37.1 EVE2_PRM Register Summary
        2. 3.13.37.2 EVE2_PRM Register Description
      38. 3.13.38 GPU_PRM Registers
        1. 3.13.38.1 GPU_PRM Register Summary
        2. 3.13.38.2 GPU_PRM Register Description
      39. 3.13.39 INSTR_PRM Registers
        1. 3.13.39.1 INSTR_PRM Register Summary
        2. 3.13.39.2 INSTR_PRM Register Description
      40. 3.13.40 IPU_PRM Registers
        1. 3.13.40.1 IPU_PRM Register Summary
        2. 3.13.40.2 IPU_PRM Register Description
      41. 3.13.41 IVA_PRM Registers
        1. 3.13.41.1 IVA_PRM Register Summary
        2. 3.13.41.2 IVA_PRM Register Description
      42. 3.13.42 L3INIT_PRM Registers
        1. 3.13.42.1 L3INIT_PRM Register Summary
        2. 3.13.42.2 L3INIT_PRM Register Description
      43. 3.13.43 L4PER_PRM Registers
        1. 3.13.43.1 L4PER_PRM Register Summary
        2. 3.13.43.2 L4PER_PRM Register Description
      44. 3.13.44 MPU_PRM Registers
        1. 3.13.44.1 MPU_PRM Register Summary
        2. 3.13.44.2 MPU_PRM Register Description
      45. 3.13.45 OCP_SOCKET_PRM Registers
        1. 3.13.45.1 OCP_SOCKET_PRM Register Summary
        2. 3.13.45.2 OCP_SOCKET_PRM Register Description
      46. 3.13.46 RTC_PRM Registers
        1. 3.13.46.1 RTC_PRM Register Summary
        2. 3.13.46.2 RTC_PRM Register Description
      47. 3.13.47 VPE_PRM Registers
        1. 3.13.47.1 VPE_PRM Register Summary
        2. 3.13.47.2 VPE_PRM Register Description
      48. 3.13.48 WKUPAON_CM Registers
        1. 3.13.48.1 WKUPAON_CM Register Summary
        2. 3.13.48.2 WKUPAON_CM Register Description
      49. 3.13.49 WKUPAON_PRM Registers
        1. 3.13.49.1 WKUPAON_PRM Register Summary
        2. 3.13.49.2 WKUPAON_PRM Register Description
  6. 4 Dual Cortex-A15 MPU Subsystem
    1. 4.1 Dual Cortex-A15 MPU Subsystem Overview
      1. 4.1.1 Introduction
      2. 4.1.2 Features
    2. 4.2 Dual Cortex-A15 MPU Subsystem Integration
      1. 4.2.1 Clock Distribution
      2. 4.2.2 Reset Distribution
    3. 4.3 Dual Cortex-A15 MPU Subsystem Functional Description
      1. 4.3.1 MPU Subsystem Block Diagram
      2. 4.3.2 Cortex-A15 MPCore (MPU_CLUSTER)
        1. 4.3.2.1 MPU L2 Cache Memory System
          1. 4.3.2.1.1 MPU L2 Cache Architecture
          2. 4.3.2.1.2 MPU L2 Cache Controller
          3. 4.3.2.1.3 707
      3. 4.3.3 MPU_AXI2OCP
      4. 4.3.4 Memory Adapter
        1. 4.3.4.1 MPU_MA Overview
        2. 4.3.4.2 AXI Input Interface
        3. 4.3.4.3 Interleaving
          1. 4.3.4.3.1 High-Order Fixed Interleaving Model
          2. 4.3.4.3.2 Lower 2-GiB Programmable Interleaving Model
          3. 4.3.4.3.3 Local Interconnect and Synchronization Agent (LISA) Section Manager
          4. 4.3.4.3.4 MA_LSM Registers
          5. 4.3.4.3.5 Posted and Nonposted Writes
          6. 4.3.4.3.6 Errors
        4. 4.3.4.4 Statistics Collector Probe Ports
        5. 4.3.4.5 MPU_MA Firewall
        6. 4.3.4.6 MPU_MA Power and Reset Management
        7. 4.3.4.7 MPU_MA Watchpoint
          1. 4.3.4.7.1 Watchpoint Types
          2. 4.3.4.7.2 Transaction Filtering Options
          3. 4.3.4.7.3 Transaction Match Effects
          4. 4.3.4.7.4 Trigger Generation
          5. 4.3.4.7.5 Programming Options Summary
      5. 4.3.5 Realtime Counter (Master Counter)
        1. 4.3.5.1 Counter Operation
        2. 4.3.5.2 Frequency Change Procedure
      6. 4.3.6 MPU Watchdog Timer
      7. 4.3.7 MPU Subsystem Power Management
        1. 4.3.7.1 Power Domains
        2. 4.3.7.2 Power States of MPU_Cx
        3. 4.3.7.3 Power States of MPU Subsystem
        4. 4.3.7.4 MPU_WUGEN
        5. 4.3.7.5 Power Transition Sequence
        6. 4.3.7.6 SR3-APG Technology Fail-Safe Mode
      8. 4.3.8 MPU Subsystem AMBA Interface Configuration
    4. 4.4 Dual Cortex-A15 MPU Subsystem Register Manual
      1. 4.4.1  Dual Cortex-A15 MPU Subsystem Instance Summary
      2. 4.4.2  MPU_CS_STM Registers
      3. 4.4.3  MPU_INTC Registers
      4. 4.4.4  MPU_PRCM_OCP_SOCKET Registers
        1. 4.4.4.1 MPU_PRCM_OCP_SOCKET Register Summary
        2. 4.4.4.2 MPU_PRCM_OCP_SOCKET Register Description
      5. 4.4.5  MPU_PRCM_DEVICE Registers
        1. 4.4.5.1 MPU_PRCM_DEVICE Register Summary
        2. 4.4.5.2 MPU_PRCM_DEVICE Register Description
      6. 4.4.6  MPU_PRCM_PRM_C0 Registers
        1. 4.4.6.1 MPU_PRCM_PRM_C0 Register Summary
        2. 4.4.6.2 MPU_PRCM_PRM_C0 Register Description
      7. 4.4.7  MPU_PRCM_CM_C0 Registers
        1. 4.4.7.1 MPU_PRCM_CM_C0 Register Summary
        2. 4.4.7.2 MPU_PRCM_CM_C0 Register Description
      8. 4.4.8  MPU_PRCM_PRM_C1 Registers
        1. 4.4.8.1 MPU_PRCM_PRM_C1 Register Summary
        2. 4.4.8.2 MPU_PRCM_PRM_C1 Register Description
      9. 4.4.9  MPU_PRCM_CM_C1 Registers
        1. 4.4.9.1 MPU_PRCM_CM_C1 Register Summary
        2. 4.4.9.2 MPU_PRCM_CM_C1 Register Description
      10. 4.4.10 MPU_WUGEN Registers
        1. 4.4.10.1 MPU_WUGEN Register Summary
        2. 4.4.10.2 MPU_WUGEN Register Description
      11. 4.4.11 MPU_WD_TIMER Registers
        1. 4.4.11.1 MPU_WD_TIMER Register Summary
        2. 4.4.11.2 MPU_WD_TIMER Register Description
      12. 4.4.12 MPU_AXI2OCP_MISC Registers
        1. 4.4.12.1 MPU_AXI2OCP_MISC Register Summary
        2. 4.4.12.2 MPU_AXI2OCP_MISC Register Description
      13. 4.4.13 MPU_MA_LSM Registers
        1. 4.4.13.1 MPU_MA_LSM Register Summary
        2. 4.4.13.2 MPU_MA_LSM Register Description
      14. 4.4.14 MPU_MA_WP Registers
        1. 4.4.14.1 MPU_MA_WP Register Summary
        2. 4.4.14.2 MPU_MA_WP Register Description
  7. 5 DSP Subsystems
    1. 5.1 DSP Subsystems Overview
      1. 5.1.1 DSP Subsystems Key Features
    2. 5.2 DSP Subsystem Integration
    3. 5.3 DSP Subsystems Functional Description
      1. 5.3.1  DSP Subsystems Block Diagram
      2. 5.3.2  DSP Subsystem Components
        1. 5.3.2.1 C66x DSP Subsystem Introduction
        2. 5.3.2.2 DSP TMS320C66x CorePac
          1. 5.3.2.2.1 DSP TMS320C66x CorePac CPU
          2. 5.3.2.2.2 DSP TMS320C66x CorePac Internal Memory Controllers and Memories
            1. 5.3.2.2.2.1 Level 1 Memories
            2. 5.3.2.2.2.2 Level 2 Memory
          3. 5.3.2.2.3 DSP C66x CorePac Internal Peripherals
            1. 5.3.2.2.3.1 DSP C66x CorePac Interrupt Controller (DSP INTC)
            2. 5.3.2.2.3.2 DSP C66x CorePac Power-Down Controller (DSP PDC)
            3. 5.3.2.2.3.3 DSP C66x CorePac Bandwidth Manager (BWM)
            4. 5.3.2.2.3.4 DSP C66x CorePac Memory Protection Hardware
            5. 5.3.2.2.3.5 DSP C66x CorePac Internal DMA (IDMA) Controller
            6. 5.3.2.2.3.6 DSP C66x CorePac External Memory Controller
            7. 5.3.2.2.3.7 DSP C66x CorePac Extended Memory Controller
              1. 5.3.2.2.3.7.1 XMC MDMA Accesses at DSP System Level
                1. 5.3.2.2.3.7.1.1 DSP System MPAX Logic
                2. 5.3.2.2.3.7.1.2 MDMA Non-Post Override Control
            8. 5.3.2.2.3.8 L1P Memory Error Detection Logic
            9. 5.3.2.2.3.9 L2 Memory Error Detection and Correction Logic
        3. 5.3.2.3 DSP Debug and Trace Support
          1. 5.3.2.3.1 DSP Advanced Event Triggering (AET)
          2. 5.3.2.3.2 DSP Trace Support
          3. 5.3.2.3.3 806
      3. 5.3.3  DSP System Control Logic
        1. 5.3.3.1 DSP System Clocks
        2. 5.3.3.2 DSP Hardware Resets
        3. 5.3.3.3 DSP Software Resets
        4. 5.3.3.4 DSP Power Management
          1. 5.3.3.4.1 DSP System Powerdown Protocols
          2. 5.3.3.4.2 DSP Software and Hardware Power Down Sequence Overview
          3. 5.3.3.4.3 DSP IDLE Wakeup
          4. 5.3.3.4.4 DSP SYSTEM IRQWAKEEN registers
          5. 5.3.3.4.5 DSP Automatic Power Transition
      4. 5.3.4  DSP Interrupt Requests
        1. 5.3.4.1 DSP Input Interrupts
          1. 5.3.4.1.1 DSP Non-maskable Interrupt Input
        2. 5.3.4.2 DSP Event and Interrupt Generation Outputs
          1. 5.3.4.2.1 DSP MDMA and DSP EDMA Mflag Event Outputs
          2. 5.3.4.2.2 DSP Aggregated Error Interrupt Output
          3. 5.3.4.2.3 Non-DSP C66x CorePac Generated Peripheral Interrupt Outputs
      5. 5.3.5  DSP DMA Requests
        1. 5.3.5.1 DSP EDMA Wakeup Interrupt
      6. 5.3.6  DSP Intergated Memory Management Units
        1. 5.3.6.1 DSP MMUs Overview
        2. 5.3.6.2 Routing MDMA Traffic through DSP MMU0
        3. 5.3.6.3 Routing EDMA Traffic thorugh DSP MMU1
      7. 5.3.7  DSP Integrated EDMA Subsystem
        1. 5.3.7.1 DSP EDMA Overview
        2. 5.3.7.2 DSP System and Device Level Settings of DSP EDMA
      8. 5.3.8  DSP L2 interconnect Network
        1. 5.3.8.1 DSP Public Firewall Settings
        2. 5.3.8.2 DSP NoC Flag Mux and Error Log Registers
        3. 5.3.8.3 DSP NoC Arbitration
      9. 5.3.9  DSP Boot Configuration
      10. 5.3.10 DSP Internal and External Memory Views
        1. 5.3.10.1 C66x CPU View of the Address Space
        2. 5.3.10.2 DSP_EDMA View of the Address Space
        3. 5.3.10.3 L3_MAIN View of the DSP Address Space
    4. 5.4 DSP Subsystem Register Manual
      1. 5.4.1 DSP Subsystem Instance Summary
      2. 5.4.2 DSP_ICFG Registers
        1. 5.4.2.1 DSP_ICFG Register Summary
        2. 5.4.2.2 DSP_ICFG Register Description
      3. 5.4.3 DSP_SYSTEM Registers
        1. 5.4.3.1 DSP_SYSTEM Register Summary
        2. 5.4.3.2 DSP_SYSTEM Register Description
      4. 5.4.4 DSP_FW_L2_NOC_CFG Registers
        1. 5.4.4.1 DSP_FW_L2_NOC_CFG Register Summary
        2. 5.4.4.2 DSP_FW_L2_NOC_CFG Register Description
  8. 6 IVA Subsystem
  9. 7 Dual Cortex-M4 IPU Subsystem
    1. 7.1 Dual Cortex-M4 IPU Subsystem Overview
      1. 7.1.1 Introduction
      2. 7.1.2 Features
    2. 7.2 Dual Cortex-M4 IPU Subsystem Integration
      1. 7.2.1 Dual Cortex-M4 IPU Subsystem Clock and Reset Distribution
        1. 7.2.1.1 Clock Distribution
        2. 7.2.1.2 Reset Distribution
    3. 7.3 Dual Cortex-M4 IPU Subsystem Functional Description
      1. 7.3.1 IPUx Subsystem Block Diagram
      2. 7.3.2 Power Management
        1. 7.3.2.1 Local Power Management
        2. 7.3.2.2 Power Domains
        3. 7.3.2.3 867
        4. 7.3.2.4 Voltage Domain
        5. 7.3.2.5 Power States and Modes
        6. 7.3.2.6 Wake-Up Generator (IPUx_WUGEN)
          1. 7.3.2.6.1 IPUx_WUGEN Main Features
      3. 7.3.3 IPUx_UNICACHE
      4. 7.3.4 IPUx_UNICACHE_MMU
      5. 7.3.5 IPUx_UNICACHE_SCTM
        1. 7.3.5.1 Counter Functions
          1. 7.3.5.1.1 Input Events
          2. 7.3.5.1.2 Counters
            1. 7.3.5.1.2.1 Counting Modes
            2. 7.3.5.1.2.2 Counter Overflow
            3. 7.3.5.1.2.3 Counters and Processor State
            4. 7.3.5.1.2.4 Chaining Counters
            5. 7.3.5.1.2.5 Enabling and Disabling Counters
            6. 7.3.5.1.2.6 Resetting Counters
        2. 7.3.5.2 Timer Functions
          1. 7.3.5.2.1 Periodic Intervals
          2. 7.3.5.2.2 Event Generation
      6. 7.3.6 IPUx_MMU
        1. 7.3.6.1 IPUx_MMU Behavior on Page-Fault in IPUx Subsystem
      7. 7.3.7 Interprocessor Communication (IPC)
        1. 7.3.7.1 Use of WFE and SEV
        2. 7.3.7.2 Use of Interrupt for IPC
        3. 7.3.7.3 Use of the Bit-Band Feature for Semaphore Operations
        4. 7.3.7.4 Private Memory Space
      8. 7.3.8 IPU Boot Options
    4. 7.4 Dual Cortex-M4 IPU Subsystem Register Manual
      1. 7.4.1 IPUx Subsystem Instance Summary
      2. 7.4.2 IPUx_UNICACHE_CFG Registers
        1. 7.4.2.1 IPUx_UNICACHE_CFG Register Summary
        2. 7.4.2.2 IPUx_UNICACHE_CFG Register Description
      3. 7.4.3 IPUx_UNICACHE_SCTM Registers
        1. 7.4.3.1 IPUx_UNICACHE_SCTM Register Summary
        2. 7.4.3.2 IPUx_UNICACHE_SCTM Register Description
      4. 7.4.4 IPUx_UNICACHE_MMU (AMMU) Registers
        1. 7.4.4.1 IPUx_UNICACHE_MMU (AMMU) Register Summary
        2. 7.4.4.2 IPUx_UNICACHE_MMU (AMMU) Register Description
      5. 7.4.5 IPUx_MMU Registers
      6. 7.4.6 IPUx_Cx_INTC Registers
      7. 7.4.7 IPUx_WUGEN Registers
        1. 7.4.7.1 IPUx_WUGEN Register Summary
        2. 7.4.7.2 IPUx_WUGEN Register Description
      8. 7.4.8 IPUx_Cx_RW_TABLE Registers
        1. 7.4.8.1 IPUx_Cx_RW_TABLE Register Summary
        2. 7.4.8.2 IPUx_Cx_RW_TABLE Register Description
  10. 8 Embedded Vision Engine
    1. 8.1 Embedded Vision Engine (EVE) Subsystem
      1. 8.1.1 EVE Overview
        1. 8.1.1.1 EVE Memories
      2. 8.1.2 EVE Integration
        1. 8.1.2.1 Multi-EVE Recommended Connections
      3. 8.1.3 EVE Functional Description
        1. 8.1.3.1  EVE Connection ID (ConnID) Mapping
        2. 8.1.3.2  EVE Processors Overview
          1. 8.1.3.2.1 Scalar Core (ARP32)
          2. 8.1.3.2.2 VCOP
          3. 8.1.3.2.3 Scalar-Vector Interaction
        3. 8.1.3.3  Internal Memory Overview
          1. 8.1.3.3.1 Program Cache/Memory
          2. 8.1.3.3.2 ARP32 Data Memory (DMEM)
          3. 8.1.3.3.3 WBUF
          4. 8.1.3.3.4 Image Buffers–IBUFLA, IBUFLB, IBUFHA, and IBUFHB
          5. 8.1.3.3.5 Memory Switch Error Registers
          6. 8.1.3.3.6 Memory Error Detection
            1. 8.1.3.3.6.1 Captured Address – EDADDR and EDADDR_BO
            2. 8.1.3.3.6.2 Modes of Operation
            3. 8.1.3.3.6.3 Parity Error Testability
            4. 8.1.3.3.6.4 Parity Error Recovery
          7. 8.1.3.3.7 VCOP System Error Halt Conditions
        4. 8.1.3.4  Program Cache Architecture
          1. 8.1.3.4.1 Basic Operation
          2. 8.1.3.4.2 Line Buffer
          3. 8.1.3.4.3 Software Direct Preload
          4. 8.1.3.4.4 User Coherence Operation
            1. 8.1.3.4.4.1 Global Invalidate
            2. 8.1.3.4.4.2 Range-Based Invalidate
            3. 8.1.3.4.4.3 Single-Address Invalidate – For Breakpoint Operation
          5. 8.1.3.4.5 Demand-Based Prefetch
          6. 8.1.3.4.6 Debug Support
            1. 8.1.3.4.6.1 Read/Write Accessibility through OCP Debug Target Port
            2. 8.1.3.4.6.2 Breakpoint Support
            3. 8.1.3.4.6.3 Cache Profiling
          7. 8.1.3.4.7 Error Detection
        5. 8.1.3.5  EDMA
          1. 8.1.3.5.1 DMA Channel Events
          2. 8.1.3.5.2 DMA Parameter Set
          3. 8.1.3.5.3 Channel Controller
          4. 8.1.3.5.4 EVE-Level Bus Width and Throughput
            1. 8.1.3.5.4.1 Concurrent Transfer Requirements
        6. 8.1.3.6  General-Purpose Inputs/Outputs
        7. 8.1.3.7  CME Signaling
        8. 8.1.3.8  Multi-EVE and VIP Usage Models
          1. 8.1.3.8.1 Data Partitioning
          2. 8.1.3.8.2 Task Partitioning
          3. 8.1.3.8.3 963
        9. 8.1.3.9  Memory Management Unit
        10. 8.1.3.10 Interrupt Control
          1. 8.1.3.10.1 EVE Interrupt Sources – Memory Switch and Parity Error Interrupts
          2. 8.1.3.10.2 ARP32 INTC
          3. 8.1.3.10.3 Output Interrupt Reduction
          4. 8.1.3.10.4 End of Interrupt Mapping
        11. 8.1.3.11 Interprocessor Communication
          1. 8.1.3.11.1 Mailbox Configuration
            1. 8.1.3.11.1.1 Mailbox 0 – EVE to DSP1, DSP2 and MPU
            2. 8.1.3.11.1.2 Mailbox 1 – EVE to Other Hosts
            3. 8.1.3.11.1.3 Mailbox 2 – EVE to EVE in a 2x EVE System
        12. 8.1.3.12 Powerdown
          1. 8.1.3.12.1 Extended Duration Sleep
            1. 8.1.3.12.1.1 Sequence Overview
            2. 8.1.3.12.1.2 Idle Protocol Overview
            3. 8.1.3.12.1.3 Mstandby Protocol Overview
            4. 8.1.3.12.1.4 IDLE Wakeup
        13. 8.1.3.13 Hardware-Assisted Software Self-Test – MISRs
          1. 8.1.3.13.1 Mapping of MISRs to Different Width Buses
          2. 8.1.3.13.2 Detection of Valid Address and Data Cycles
          3. 8.1.3.13.3 Creating a Unique Signature – Software Self-Test Implications
          4. 8.1.3.13.4 Multipass Tests Using WBUF MISR
        14. 8.1.3.14 Error Recovery – ARP32 and OCP Disconnect
          1. 8.1.3.14.1 ARP32 Disconnect
          2. 8.1.3.14.2 OCP Initiator Disconnect
        15. 8.1.3.15 Lock and Unlock Feature
        16. 8.1.3.16 EVE Memory Map
          1. 8.1.3.16.1 VCOP and Local EDMA: IBUF Memory Map Aliasing
          2. 8.1.3.16.2 ARP32 Write Model – Avoiding Race Conditions
        17. 8.1.3.17 Debug Support
          1. 8.1.3.17.1 ARP32 Debug Support
          2. 8.1.3.17.2 SCTM
            1. 8.1.3.17.2.1 SCTM Configuration
            2. 8.1.3.17.2.2 SCTM Resources Reserved for BIOS
            3. 8.1.3.17.2.3 SCTM Event Mapping
            4. 8.1.3.17.2.4 SCTM Halt and Idle Modes
          3. 8.1.3.17.3 SMSET
            1. 8.1.3.17.3.1 SMSET Configuration
            2. 8.1.3.17.3.2 SMSET Event Mapping
        18. 8.1.3.18 EVE L2_FNOC Interconnect
          1. 8.1.3.18.1 EVE L2_FNOC Flag Mux and Error Log Registers
      4. 8.1.4 EVE Programming Model
        1. 8.1.4.1 Boot
        2. 8.1.4.2 Task Change and Program Cache Prefetch
          1. 8.1.4.2.1 Simple or Unoptimized Branch to New Task
          2. 8.1.4.2.2 Prefetch, Wait, then Branch to New Task
          3. 8.1.4.2.3 Hidden Prefetch
        3. 8.1.4.3 Interrupts
        4. 8.1.4.4 Safety Considerations
          1. 8.1.4.4.1 Memory Error Detection
          2. 8.1.4.4.2 MMU
          3. 8.1.4.4.3 Firewall
          4. 8.1.4.4.4 Interconnect
          5. 8.1.4.4.5 Application Stability/Sequencing
          6. 8.1.4.4.6 Interrupt Servicing
      5. 8.1.5 EVE Subsystem Register Manual
        1. 8.1.5.1 EVE Instance Summary
        2. 8.1.5.2 EVE Register Summary and Description
          1. 8.1.5.2.1 EVE Register Summary
          2. 8.1.5.2.2 EVE Register Description
        3. 8.1.5.3 EVE L2_FNOC Register Summary and Description
          1. 8.1.5.3.1 EVE L2_FNOC Register Summary
          2. 8.1.5.3.2 EVE L2_FNOC Register Description
      6. 8.1.6 Subsystem Counter Timer Module
        1. 8.1.6.1 Introduction
          1. 8.1.6.1.1 Overview
          2. 8.1.6.1.2 Top-Level Requirements
          3. 8.1.6.1.3 Configuration
          4. 8.1.6.1.4 Block Diagram
        2. 8.1.6.2 Functional Description
          1. 8.1.6.2.1 Configuration Interface
          2. 8.1.6.2.2 Counter Function
            1. 8.1.6.2.2.1 Input Events
            2. 8.1.6.2.2.2 Counters
            3. 8.1.6.2.2.3 Counting Mode
            4. 8.1.6.2.2.4 Counter Overflow
            5. 8.1.6.2.2.5 Counters and Processor State
            6. 8.1.6.2.2.6 Chaining Counters
              1. 8.1.6.2.2.6.1 Reading Chained Counters
            7. 8.1.6.2.2.7 Enabling and Disabling Counters
            8. 8.1.6.2.2.8 Resetting Counters
          3. 8.1.6.2.3 Timer Function
            1. 8.1.6.2.3.1 Periodic Intervals
            2. 8.1.6.2.3.2 Event Generation
            3. 8.1.6.2.3.3 Watchdog Timer Function
          4. 8.1.6.2.4 System Trace Integration
            1. 8.1.6.2.4.1 Overview
            2. 8.1.6.2.4.2 STM Configuration
              1. 8.1.6.2.4.2.1 Periodic Counter State Export
              2. 8.1.6.2.4.2.2 Application Control of Counter State Export
              3. 8.1.6.2.4.2.3 Application Control of the Counter Configuration Export
        3. 8.1.6.3 Use Case Examples
          1. 8.1.6.3.1 Counter Enable
            1. 8.1.6.3.1.1 Enabling a Single Counter
            2. 8.1.6.3.1.2 Reading a Single Counter
            3. 8.1.6.3.1.3 Enabling a Group of Counters Simultaneously
            4. 8.1.6.3.1.4 Reading a Group of Counters Simultaneously
            5. 8.1.6.3.1.5 Configuring a Chained Counter
          2. 8.1.6.3.2 Timer Enable
          3. 8.1.6.3.3 Periodic STM Export Enable
          4. 8.1.6.3.4 Disabling the SCTM
        4. 8.1.6.4 SCTM Register Manual
          1. 8.1.6.4.1 SCTM Instance Summary
          2. 8.1.6.4.2 SCTM Registers
            1. 8.1.6.4.2.1 SCTM Register Summary
            2. 8.1.6.4.2.2 SCTM Register Description
      7. 8.1.7 Software Message and System Event Trace
        1. 8.1.7.1 Introduction
          1. 8.1.7.1.1 Overview
          2. 8.1.7.1.2 Configuration
          3. 8.1.7.1.3 Block Diagram
        2. 8.1.7.2 Functional Description
          1. 8.1.7.2.1 Connectivity
          2. 8.1.7.2.2 SMSET Event Mapping
          3. 8.1.7.2.3 Software Messages
          4. 8.1.7.2.4 SMSET Master Port
            1. 8.1.7.2.4.1 OCP Disconnect
          5. 8.1.7.2.5 SMSET Debug Features
          6. 8.1.7.2.6 Component Ownership
            1. 8.1.7.2.6.1 Ownership State
              1. 8.1.7.2.6.1.1 Available State
              2. 8.1.7.2.6.1.2 Claimed State
              3. 8.1.7.2.6.1.3 Enabled State
            2. 8.1.7.2.6.2 Ownership Commands
            3. 8.1.7.2.6.3 Claim Reset
        3. 8.1.7.3 Use Case Examples
          1. 8.1.7.3.1 Procedure to Enable System Event Capture
          2. 8.1.7.3.2 Procedure to Start and Stop System Event Capture from External Trigger Detection
          3. 8.1.7.3.3 Procedure to Disable System Event Capture
        4. 8.1.7.4 SMSET Register Manual
          1. 8.1.7.4.1 SMSET Instance Summary
          2. 8.1.7.4.2 SMSET Register Summary
          3. 8.1.7.4.3 SMSET Register Description
    2. 8.2 ARP32 CPU and Instruction Set
      1. 8.2.1 Overview
      2. 8.2.2 Features
      3. 8.2.3 Block Diagram
      4. 8.2.4 Architecture
        1. 8.2.4.1  Interface Description
          1. 8.2.4.1.1 Data Memory Interface
          2. 8.2.4.1.2 Instruction Memory Interface
        2. 8.2.4.2  Pipeline
          1. 8.2.4.2.1 Overview
          2. 8.2.4.2.2 Pipeline Operation
            1. 8.2.4.2.2.1 ARP32 CPU Pipeline Operation
            2. 8.2.4.2.2.2 1109
          3. 8.2.4.2.3 Pipeline Interlocks
        3. 8.2.4.3  Data Format
        4. 8.2.4.4  Endian Support
        5. 8.2.4.5  Architectural Register File
        6. 8.2.4.6  CPU Control Registers
          1. 8.2.4.6.1  Control Status Register (CSR)
          2. 8.2.4.6.2  Interrupt Enable Register (IER)
          3. 8.2.4.6.3  Interrupt Flag Register (IFR)
          4. 8.2.4.6.4  Interrupt Set Register (ISR)
          5. 8.2.4.6.5  Interrupt Clear Register (ICR)
          6. 8.2.4.6.6  Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)
          7. 8.2.4.6.7  Interrupt Return Pointer Register (IRP)
          8. 8.2.4.6.8  Stack Pointer Register (SP)
          9. 8.2.4.6.9  Global Data Pointer Register (GDP)
          10. 8.2.4.6.10 Link Register (LR)
          11. 8.2.4.6.11 Loop 0 Start Address Register (LSA0)
          12. 8.2.4.6.12 Loop 0 End Address Register (LEA0)
          13. 8.2.4.6.13 Loop 0 Iteration Count Register (LCNT0)
          14. 8.2.4.6.14 Loop 1 Start Address Register (LSA1)
          15. 8.2.4.6.15 Loop 1 End Address Register (LEA1)
          16. 8.2.4.6.16 Loop 1 Iteration Count Register (LCNT1)
          17. 8.2.4.6.17 Loop 0 Iteration Count Reload Value Register (LCNT0RLD)
          18. 8.2.4.6.18 Shadow Control Status Register (SCSR)
          19. 8.2.4.6.19 NMI Shadow Control Status Register (NMISCSR)
          20. 8.2.4.6.20 CPU Identification Register (CPUID)
          21. 8.2.4.6.21 Decode Program Counter Register (DPC)
          22. 8.2.4.6.22 Time Stamp Counter Registers (TSCL and TSCH)
            1. 8.2.4.6.22.1 Initialization
            2. 8.2.4.6.22.2 Enabling Counting
            3. 8.2.4.6.22.3 Disabling Counting
            4. 8.2.4.6.22.4 Reading the Counter
        7. 8.2.4.7  CPU Shadow Registers
        8. 8.2.4.8  Functional Units
        9. 8.2.4.9  Instruction Fetch
        10. 8.2.4.10 Alignment of 32-bit Instructions
        11. 8.2.4.11 Instruction Execution in Branch Delay Slot
        12. 8.2.4.12 Address Space
        13. 8.2.4.13 Program Counter Convention
        14. 8.2.4.14 Stack Pointer Convention
        15. 8.2.4.15 Global Data Pointer Convention
        16. 8.2.4.16 Conditional Execution
        17. 8.2.4.17 Hardware Loop Acceleration
          1. 8.2.4.17.1  Overview
          2. 8.2.4.17.2  Loop Registers
          3. 8.2.4.17.3  Loop Setup Instructions
          4. 8.2.4.17.4  Loop Operation
          5. 8.2.4.17.5  Call and Branch within Loop Context
          6. 8.2.4.17.6  Dynamic Changes to Loop Iteration Count
          7. 8.2.4.17.7  Interrupt Processing During HLA
          8. 8.2.4.17.8  HLA Usage in Interrupt Context
          9. 8.2.4.17.9  HLA Usage Restrictions
          10. 8.2.4.17.10 HLA Mapping Examples
            1. 8.2.4.17.10.1 Loops With Single Level of Nesting
              1. 8.2.4.17.10.1.1 C memset-like Loop, Single Level, Minimum Instructions
              2. 8.2.4.17.10.1.2 1164
              3. 8.2.4.17.10.1.3 C memcpy-like Loop, Single Level, Minimum Instructions
              4. 8.2.4.17.10.1.4 1166
            2. 8.2.4.17.10.2 Loops With Two Levels of Nesting
              1. 8.2.4.17.10.2.1 Two-level Nesting, Both Loops Ending at Same Instruction
              2. 8.2.4.17.10.2.2 1169
              3. 8.2.4.17.10.2.3 Two-level Nesting, Different Ending Instructions for Two Levels
              4. 8.2.4.17.10.2.4 1171
        18. 8.2.4.18 Interrupts
          1. 8.2.4.18.1  Overview
          2. 8.2.4.18.2  Interrupt Processing
          3. 8.2.4.18.3  Interrupt Acknowledgment
          4. 8.2.4.18.4  Interrupt Priorities
          5. 8.2.4.18.5  Interrupt Service Table (IST)
          6. 8.2.4.18.6  Interrupt Flags
            1. 8.2.4.18.6.1 Setting Interrupt Flag
            2. 8.2.4.18.6.2 Setting Interrupt Flag
            3. 8.2.4.18.6.3 1181
          7. 8.2.4.18.7  Interrupt Behavior
            1. 8.2.4.18.7.1 Reset Interrupt
            2. 8.2.4.18.7.2 Non-maskable Interrupt (NMI)
            3. 8.2.4.18.7.3 SWI Interrupt
            4. 8.2.4.18.7.4 Maskable Interrupts
            5. 8.2.4.18.7.5 UNDEF Interrupt
          8. 8.2.4.18.8  Interrupt Context Save and Restore
          9. 8.2.4.18.9  Nested Interrupts
            1. 8.2.4.18.9.1 Non-nested Interrupt Model
            2. 8.2.4.18.9.2 Nested Interrupt Model
          10. 8.2.4.18.10 Non-nested Interrupt Latency
            1. 8.2.4.18.10.1 Best Case Interrupt Latency
            2. 8.2.4.18.10.2 Worst Case Interrupt Latency
      5.      8.2.A Instruction Set
        1.       8.2.A.1 Instruction Operation and Execution Notations
        2.       8.2.A.2 Instruction Syntax and Opcode Notations
        3.       8.2.A.3 Instruction Scheduling Restrictions
          1.        8.2.A.3.1 Restrictions Applicable to a Branch Delay Slot
          2.        8.2.A.3.2 Restrictions on Loops Using Hardware Loop Assist (HLA)
          3.        8.2.A.3.3 Restrictions on Other Types of Control Flow Instructions
          4.        8.2.A.3.4 Restrictions for Write Data Bypass to Control Register Reads
          5.        8.2.A.3.5 Restrictions for Write Data Bypass to Shadow Register Reads
          6.        8.2.A.3.6 Restrictions for Link Register Update
        4.       8.2.A.4 Instruction Set Encoding
        5.       8.2.A.5 Instruction Descriptions
          1.        ABS
          2.        ADD
          3.        ADD
          4.        ADD
          5.        ADD
          6.        ADD
          7.        AND
          8.        AND
          9.        B(cc)
          10.        B(cc)
          11.        B(cc)
          12.        BIRP
          13.        BKPT
          14.        BNRP
          15.        CALL
          16.        CALL
          17.        CLR
          18.        CLR
          19.        CMP
          20.        CMP
          21.        CMP
          22.        CMPU
          23.        CMPU
          24.        CMPU
          25.        DIV
          26.        DIVU
          27.        EXT
          28.        EXT
          29.        EXTU
          30.        EXTU
          31.        IDLE
          32.        LDB(U)
          33.        LDB(U)
          34.        LDB(U)
          35.        LDB(U)
          36.        LDB(U)
          37.        LDB(U)
          38.        LDB(U)
          39.        LDB(U)
          40.        LDH(U)
          41.        LDH(U)
          42.        LDH(U)
          43.        LDH(U)
          44.        LDH(U)
          45.        LDH(U)
          46.        LDH(U)
          47.        LDH(U)
          48.        LDW
          49.        LDW
          50.        LDW
          51.        LDW
          52.        LDW
          53.        LDW
          54.        LDW
          55.        LDW
          56.        LDRF
          57.        LMBD
          58.        MAX
          59.        MAXU
          60.        MIN
          61.        MINU
          62.        MOD
          63.        MODU
          64.        MPY
          65.        MPYU
          66.        MV
          67.        MVC
          68.        MVC
          69.        MVC
          70.        MVCH
          71.        MVK
          72.        MVKH
          73.        MVKLS
          74.        MVKS
          75.        MVS
          76.        MVS
          77.        NEG
          78.        NOP
          79.        NOT
          80.        OR
          81.        OR
          82.        RET
          83.        REV
          84.        ROT
          85.        ROTC
          86.        SADD
          87.        SATN
          88.        SET
          89.        SET
          90.        SHL
          91.        SHL
          92.        SHRA
          93.        SHRA
          94.        SHRU
          95.        SHRU
          96.        SLA
          97.        SSUB
          98.        STB
          99.        STB
          100.        STB
          101.        STB
          102.        STB
          103.        STB
          104.        STB
          105.        STB
          106.        STH
          107.        STH
          108.        STH
          109.        STH
          110.        STH
          111.        STH
          112.        STH
          113.        STH
          114.        STW
          115.        STW
          116.        STW
          117.        STW
          118.        STW
          119.        STW
          120.        STW
          121.        STW
          122.        STHI
          123.        STRF
          124.        SUB
          125.        SUB
          126.        SUB
          127.        SUB
          128.        SUB
          129.        SWI
          130.        XOR
          131.        XOR
      6.      8.2.B Clock, Reset, and Dynamic Power Management
        1.       8.2.B.1 Introduction
        2.       8.2.B.2 CPU Reset Modes
        3.       8.2.B.3 Dynamic Power Management
      7.      8.2.C Notes on Programming Model
        1.       8.2.C.1 Booting
        2.       8.2.C.2 Enabling and Disabling Interrupts
          1.        8.2.C.2.1 Globally Enabling or Disabling Maskable Interrupts
          2.        8.2.C.2.2 Enabling or Disabling Individual Interrupts
        3.       8.2.C.3 Stack Usage in Interrupt Service Routine
        4.       8.2.C.4 General Restrictions
    3. 8.3 VCOP CPU and Instruction Set
      1. 8.3.1 Module Overview
      2. 8.3.2 Features
      3. 8.3.3 Block Diagram
      4. 8.3.4 System Interfaces
        1. 8.3.4.1 Interrupts
        2. 8.3.4.2 Configuration Bus Slave Port
        3. 8.3.4.3 Performance Counter Interface
        4. 8.3.4.4 Data Memory Map
      5. 8.3.5 Functional Description
        1. 8.3.5.1 Scalar-Vector Architecture
          1. 8.3.5.1.1 Scalar Core
          2. 8.3.5.1.2 Scalar-Vector Interaction
        2. 8.3.5.2 Vector Core Overview
          1. 8.3.5.2.1 Nested for Loop Model
            1. 8.3.5.2.1.1 Nested Loop Model Skeleton
            2. 8.3.5.2.1.2 1365
          2. 8.3.5.2.2 Instruction Organization
        3. 8.3.5.3 Vector Control
          1. 8.3.5.3.1 Repeat End Count
          2. 8.3.5.3.2 Parameter Pointer
          3. 8.3.5.3.3 Switch Buffers
        4. 8.3.5.4 Vector-Scalar Synchronization
          1. 8.3.5.4.1 Wait for Vector Core Done
          2. 8.3.5.4.2 Wait for Vector Core Ready
        5. 8.3.5.5 Vector Computation
          1. 8.3.5.5.1  Vector Loop
            1. 8.3.5.5.1.1 Retention of State Between VLOOPs
          2. 8.3.5.5.2  Vector Register Initialization
          3. 8.3.5.5.3  Address Generator (agen)
          4. 8.3.5.5.4  Vector Load
          5. 8.3.5.5.5  Vector Arithmetic/Logic Operations
          6. 8.3.5.5.6  Vector Store
          7. 8.3.5.5.7  Table Lookup Operation
          8. 8.3.5.5.8  Histogram Operation
          9. 8.3.5.5.9  Circular Buffer Addressing Support
          10. 8.3.5.5.10 Load/Store Address Alignment Constraints
        6. 8.3.5.6 Load/Store Buffer and Scheduling
          1. 8.3.5.6.1 3-Tap Horizontal Filtering, Byte Type
          2. 8.3.5.6.2 1388
          3. 8.3.5.6.3 Horizontal Filtering, Short Type
          4. 8.3.5.6.4 1390
        7. 8.3.5.7 VCOP Per-Loop Overhead
        8. 8.3.5.8 VCOP Error Handling
        9. 8.3.5.9 Vector Operation Details
          1. 8.3.5.9.1  VABS
          2. 8.3.5.9.2  VABSDIF
          3. 8.3.5.9.3  VADD
          4. 8.3.5.9.4  VADDH
          5. 8.3.5.9.5  VADDSUB
          6. 8.3.5.9.6  VADD3
          7. 8.3.5.9.7  VADIF3
          8. 8.3.5.9.8  VAND
          9. 8.3.5.9.9  VANDN
          10. 8.3.5.9.10 VAND3
          11. 8.3.5.9.11 VBINLOG
          12. 8.3.5.9.12 VBITC
          13. 8.3.5.9.13 VBITDI
          14. 8.3.5.9.14 VBITI
          15. 8.3.5.9.15 VBITPK
          16. 8.3.5.9.16 VBITR
          17. 8.3.5.9.17 VBITTR
          18. 8.3.5.9.18 VBITUNPK
          19. 8.3.5.9.19 VCMOV
          20. 8.3.5.9.20 VCMPEQ
          21. 8.3.5.9.21 VCMPGE
          22. 8.3.5.9.22 VCMPGT
          23. 8.3.5.9.23 VDINTRLV
          24. 8.3.5.9.24 VDINTRLV2
          25. 8.3.5.9.25 VEXITNZ
          26. 8.3.5.9.26 VINTRLV
          27. 8.3.5.9.27 VINTRLV2
          28. 8.3.5.9.28 VINTRLV4
          29. 8.3.5.9.29 VLMBD
          30. 8.3.5.9.30 VMADD
          31. 8.3.5.9.31 VMAX
          32. 8.3.5.9.32 VMAXSETF
          33. 8.3.5.9.33 VMIN
          34. 8.3.5.9.34 VMINSETF
          35. 8.3.5.9.35 VMPY
          36. 8.3.5.9.36 VMSUB
          37. 8.3.5.9.37 VNOP
          38. 8.3.5.9.38 VNOT
          39. 8.3.5.9.39 VOR
          40. 8.3.5.9.40 VOR3
          41. 8.3.5.9.41 VRND
          42. 8.3.5.9.42 VSAD
          43. 8.3.5.9.43 VSEL
          44. 8.3.5.9.44 VSHF
          45. 8.3.5.9.45 VSHFOR
          46. 8.3.5.9.46 VSHF16
          47. 8.3.5.9.47 VSIGN
          48. 8.3.5.9.48 VSORT2
          49. 8.3.5.9.49 VSUB
          50. 8.3.5.9.50 VSWAP
          51. 8.3.5.9.51 VXOR
      6. 8.3.6 Debug Support
      7. 8.3.7 VCOP Register Manual
        1. 8.3.7.1 VCOP Instance Summary
        2. 8.3.7.2 VCOP Registers
          1. 8.3.7.2.1 VCOP Registers Mapping Summary
          2. 8.3.7.2.2 VCOP Register Description
  11. 9 Video Input Port
    1. 9.1 VIP Overview
    2. 9.2 VIP Environment
    3. 9.3 VIP Integration
    4. 9.4 VIP Functional Description
      1. 9.4.1 VIP Block Diagram
      2. 9.4.2 VIP Software Reset
      3. 9.4.3 VIP Power and Clocks Management
        1. 9.4.3.1 VIP Clocks
        2. 9.4.3.2 VIP Idle Mode
        3. 9.4.3.3 VIP StandBy Mode
      4. 9.4.4 VIP Slice
        1. 9.4.4.1 VIP Slice Processing Path Overview
        2. 9.4.4.2 VIP Slice Processing Path Multiplexers
          1. 9.4.4.2.1 VIP_CSC Multiplexers
          2. 9.4.4.2.2 VIP_SC Multiplexer
          3. 9.4.4.2.3 Output to VPDMA Multiplexers
        3. 9.4.4.3 VIP Slice Processing Path Examples
          1. 9.4.4.3.1 Input: A=RGB, B=YUV422; Output: A=RGB, B=RGB
          2. 9.4.4.3.2 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=RGB
          3. 9.4.4.3.3 Input: A=RGB, B=YUV422; Output: A=RGB, B=Scaled YUV420
          4. 9.4.4.3.4 Input: A=YUV444, B=YUV422; Output: A=YUV422, A=Scaled YUV422, B=YUV422
          5. 9.4.4.3.5 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV420
          6. 9.4.4.3.6 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV444
          7. 9.4.4.3.7 Input: A=YUV422 8/16; Output: A=Scaled YUV420, A=YUV444
          8. 9.4.4.3.8 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=YUV420
          9. 9.4.4.3.9 Input: A=YUV422 8/16, B=YUV422; Output: A=YUV420, B=YUV420
      5. 9.4.5 VIP Parser
        1. 9.4.5.1  Features
        2. 9.4.5.2  Repacker
        3. 9.4.5.3  Analog Video
        4. 9.4.5.4  Digitized Video
        5. 9.4.5.5  Frame Buffers
        6. 9.4.5.6  Input Data Interface
          1. 9.4.5.6.1  8b Interface Mode
          2. 9.4.5.6.2  16b Interface Mode
          3. 9.4.5.6.3  24b Interface Mode
          4. 9.4.5.6.4  Signal Relationships
          5. 9.4.5.6.5  General 5 Pin Interfaces
          6. 9.4.5.6.6  Signal Subsets—4 Pin VSYNC, ACTVID, and FID
          7. 9.4.5.6.7  Signal Subsets—4 Pin VSYNC, HSYNC, and FID
          8. 9.4.5.6.8  Vertical Sync
          9. 9.4.5.6.9  Field ID Determination Using Dedicated Signal
          10. 9.4.5.6.10 Field ID Determination Using VSYNC Skew
          11. 9.4.5.6.11 Rationale for FID Determination By VSYNC Skew
          12. 9.4.5.6.12 ACTVID Framing
          13. 9.4.5.6.13 Ancillary Data Storage in Descrete Sync Mode
        7. 9.4.5.7  BT.656 Style Embedded Sync
          1. 9.4.5.7.1 Data Input
          2. 9.4.5.7.2 Sync Words
          3. 9.4.5.7.3 Error Correction
          4. 9.4.5.7.4 Embedded Sync Ancillary Data
          5. 9.4.5.7.5 Embedded Sync RGB 24-bit Data
        8. 9.4.5.8  Source Multiplexing
          1. 9.4.5.8.1  Multiplexing Scenarios
          2. 9.4.5.8.2  2-Way Multiplexing
          3. 9.4.5.8.3  4-Way Multiplexing
          4. 9.4.5.8.4  Line Multiplexing
          5. 9.4.5.8.5  Super Frame Concept in Line Multiplexing
          6. 9.4.5.8.6  8-bit Data Interface in Line Multiplexing
          7. 9.4.5.8.7  16-bit Data Interface in Line Multiplexing
          8. 9.4.5.8.8  Split Lines in Line Multiplex Mode
          9. 9.4.5.8.9  Meta Data
          10. 9.4.5.8.10 TI Line Mux Mode, Split Lines, and Channel ID Remapping
        9. 9.4.5.9  Channel ID Extraction for 2x/4x Multiplexed Source
          1. 9.4.5.9.1 Channel ID Extraction Overview
          2. 9.4.5.9.2 Channel ID Embedded in Protection Bits for 2- and 4-Way Multiplexing
          3. 9.4.5.9.3 Channel ID Embedded in Horizontal Blanking Pixel Data for 2- and 4-Way Multiplexing
        10. 9.4.5.10 Embedded Sync Mux Modes and Data Bus Widths
        11. 9.4.5.11 Ancillary and Active Video Cropping
        12. 9.4.5.12 Interrupts
        13. 9.4.5.13 VDET Interrupt
        14. 9.4.5.14 Source Video Size
        15. 9.4.5.15 Clipping
        16. 9.4.5.16 Current and Last FID Value
        17. 9.4.5.17 Disable Handling
        18. 9.4.5.18 Picture Size Interrupt
        19. 9.4.5.19 Discrete Sync Signals
          1. 9.4.5.19.1 VBLNK and HBLNK
          2. 9.4.5.19.2 BLNK and ACTVID (1)
          3. 9.4.5.19.3 VBLNK and ACTVID(2)
          4. 9.4.5.19.4 VBLNK and HSYNC
          5. 9.4.5.19.5 VSYNC and HBLNK
          6. 9.4.5.19.6 VSYNC and ACTIVID(1)
          7. 9.4.5.19.7 VSYNC and ACTIVID(2)
          8. 9.4.5.19.8 VSYNC and HSYNC
          9. 9.4.5.19.9 Line and Pixel Capture Examples
        20. 9.4.5.20 VIP Overflow Detection and Recovery
      6. 9.4.6 VIP Color Space Converter (CSC)
        1. 9.4.6.1 CSC Features
        2. 9.4.6.2 CSC Functional Description
          1. 9.4.6.2.1 HDTV Application
            1. 9.4.6.2.1.1 HDTV Application with Video Data Range
            2. 9.4.6.2.1.2 HDTV Application with Graphics Data Range
            3. 9.4.6.2.1.3 Quantized Coefficients for Color Space Converter in HDTV
          2. 9.4.6.2.2 SDTV Application
            1. 9.4.6.2.2.1 SDTV Application with Video Data Range
            2. 9.4.6.2.2.2 SDTV Application with Graphics Data Range
            3. 9.4.6.2.2.3 Quantized Coefficients for Color Space Converter in SDTV
        3. 9.4.6.3 CSC Bypass Mode
      7. 9.4.7 VIP Scaler (SC)
        1. 9.4.7.1 SC Features
        2. 9.4.7.2 SC Functional Description
          1. 9.4.7.2.1 Trimmer
          2. 9.4.7.2.2 1555
          3. 9.4.7.2.3 Peaking
          4. 9.4.7.2.4 Vertical Scaler
            1. 9.4.7.2.4.1 Running Average Filter
            2. 9.4.7.2.4.2 Vertical Scaler Configuration Parameters
          5. 9.4.7.2.5 Horizontal Scaler
            1. 9.4.7.2.5.1 Half Decimation Filter
            2. 9.4.7.2.5.2 Polyphase Filter
            3. 9.4.7.2.5.3 Nonlinear Horizontal Scaling
            4. 9.4.7.2.5.4 Horizontal Scaler Configuration Registers
          6. 9.4.7.2.6 Basic Configurations
          7. 9.4.7.2.7 Coefficient Memory
            1. 9.4.7.2.7.1 Overview
            2. 9.4.7.2.7.2 Physical Coefficient SRAM Layout
            3. 9.4.7.2.7.3 Scaler Coefficients Packing on 128-bit VPI Control I/F
            4. 9.4.7.2.7.4 VPI Control I/F Memory Map for Scaler Coefficients
            5. 9.4.7.2.7.5 VPI Control Interface
            6. 9.4.7.2.7.6 Coefficient Table Selection Guide
        3. 9.4.7.3 SC Code
          1. 9.4.7.3.1 Generate Coefficient Memory Image
          2. 9.4.7.3.2 Scaler Configuration Calculation
          3. 9.4.7.3.3 Typical Configuration Values
        4. 9.4.7.4 SC Coefficient Data Files
          1. 9.4.7.4.1 HS Polyphase Filter Coefficients
            1. 9.4.7.4.1.1 ppfcoef_scale_eq_1_32_phases_flip.dat
            2. 9.4.7.4.1.2 ppfcoef_scale_eq_8div16_32_phases_flip.dat
            3. 9.4.7.4.1.3 ppfcoef_scale_eq_9div16_32_phases_flip.dat
            4. 9.4.7.4.1.4 ppfcoef_scale_eq_10div16_32_phases_flip.dat
            5. 9.4.7.4.1.5 ppfcoef_scale_eq_11div16_32_phases_flip.dat
            6. 9.4.7.4.1.6 ppfcoef_scale_eq_12div16_32_phases_flip.dat
            7. 9.4.7.4.1.7 ppfcoef_scale_eq_13div16_32_phases_flip.dat
            8. 9.4.7.4.1.8 ppfcoef_scale_eq_14div16_32_phases_flip.dat
            9. 9.4.7.4.1.9 ppfcoef_scale_eq_15div16_32_phases_flip.dat
          2. 9.4.7.4.2 VS Polyphase Filter Coefficients
            1. 9.4.7.4.2.1 ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
            2. 9.4.7.4.2.2 ppfcoef_scale_eq_3_32_phases_flip.dat
            3. 9.4.7.4.2.3 ppfcoef_scale_eq_4_32_phases_flip.dat
            4. 9.4.7.4.2.4 ppfcoef_scale_eq_5_32_phases_flip.dat
            5. 9.4.7.4.2.5 ppfcoef_scale_eq_6_32_phases_flip.dat
            6. 9.4.7.4.2.6 ppfcoef_scale_eq_7_32_phases_flip.dat
              1. 9.4.7.4.2.6.1 ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
              2. 9.4.7.4.2.6.2 ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
              3. 9.4.7.4.2.6.3 ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
              4. 9.4.7.4.2.6.4 ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
              5. 9.4.7.4.2.6.5 ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
              6. 9.4.7.4.2.6.6 ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
              7. 9.4.7.4.2.6.7 ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
              8. 9.4.7.4.2.6.8 ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
          3. 9.4.7.4.3 VS (Bilinear Filter Coefficients)
            1. 9.4.7.4.3.1 ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
      8. 9.4.8 VIP Video Port Direct Memory Access (VPDMA)
        1. 9.4.8.1  VPDMA Introduction
        2. 9.4.8.2  VPDMA Basic Definitions
          1. 9.4.8.2.1 Client
          2. 9.4.8.2.2 Channel
          3. 9.4.8.2.3 List
          4. 9.4.8.2.4 Data Formats Supported
        3. 9.4.8.3  1612
        4. 9.4.8.4  VPDMA Client Buffering and Functionality
        5. 9.4.8.5  VPDMA Channels Assignment
        6. 9.4.8.6  VPDMA MFLAG Mechanism
        7. 9.4.8.7  VPDMA Interrupts
        8. 9.4.8.8  VPDMA Descriptors
          1. 9.4.8.8.1 Data Transfer Descriptors
            1. 9.4.8.8.1.1 Data Packet Descriptor Word 0 (Data)
              1. 9.4.8.8.1.1.1 Data Type
              2. 9.4.8.8.1.1.2 Notify
              3. 9.4.8.8.1.1.3 Field
              4. 9.4.8.8.1.1.4 Even Line Skip
              5. 9.4.8.8.1.1.5 Odd Line Skip
              6. 9.4.8.8.1.1.6 Line Stride
            2. 9.4.8.8.1.2 Data Packet Descriptor Word 1
              1. 9.4.8.8.1.2.1 Line Length
              2. 9.4.8.8.1.2.2 Transfer Height
            3. 9.4.8.8.1.3 Data Packet Descriptor Word 2
              1. 9.4.8.8.1.3.1 Start Address
            4. 9.4.8.8.1.4 Data Packet Descriptor Word 3
              1. 9.4.8.8.1.4.1 Packet Type
              2. 9.4.8.8.1.4.2 Mode
              3. 9.4.8.8.1.4.3 Direction
              4. 9.4.8.8.1.4.4 Channel
              5. 9.4.8.8.1.4.5 Priority
              6. 9.4.8.8.1.4.6 Next Channel
            5. 9.4.8.8.1.5 Data Packet Descriptor Word 4
              1. 9.4.8.8.1.5.1 Inbound data
                1. 9.4.8.8.1.5.1.1 Frame Width
                2. 9.4.8.8.1.5.1.2 Frame Height
              2. 9.4.8.8.1.5.2 Outbound data
                1. 9.4.8.8.1.5.2.1 Descriptor Write Address
                2. 9.4.8.8.1.5.2.2 Write Descriptor
                3. 9.4.8.8.1.5.2.3 Drop Data
            6. 9.4.8.8.1.6 Data Packet Descriptor Word 5
              1. 9.4.8.8.1.6.1 Outbound data
                1. 9.4.8.8.1.6.1.1 Max Width
                2. 9.4.8.8.1.6.1.2 Max Height
          2. 9.4.8.8.2 Configuration Descriptor
            1. 9.4.8.8.2.1 Configuration Descriptor Header Word0
            2. 9.4.8.8.2.2 Configuration Descriptor Header Word1
              1. 9.4.8.8.2.2.1 Number of Data Words
            3. 9.4.8.8.2.3 Configuration Descriptor Header Word2
              1. 9.4.8.8.2.3.1 Payload Location
            4. 9.4.8.8.2.4 Configuration Descriptor Header Word3
              1. 9.4.8.8.2.4.1 Packet Type
              2. 9.4.8.8.2.4.2 Direct
              3. 9.4.8.8.2.4.3 Class
                1. 9.4.8.8.2.4.3.1 Address Data Block Format
              4. 9.4.8.8.2.4.4 Destination
              5. 9.4.8.8.2.4.5 Descriptor Length
          3. 9.4.8.8.3 Control Descriptor
            1. 9.4.8.8.3.1 Generic Control Descriptor Format
            2. 9.4.8.8.3.2 Control Descriptor Header Description
              1. 9.4.8.8.3.2.1 Packet Type
              2. 9.4.8.8.3.2.2 Source
              3. 9.4.8.8.3.2.3 Control
            3. 9.4.8.8.3.3 Control Descriptor Types
              1. 9.4.8.8.3.3.1 Sync on Client
              2. 9.4.8.8.3.3.2 Sync on List
              3. 9.4.8.8.3.3.3 Sync on External Event
              4. 9.4.8.8.3.3.4 Sync on Channel
              5. 9.4.8.8.3.3.5 Sync on LM Timer
              6. 9.4.8.8.3.3.6 Change Client Interrupt
              7. 9.4.8.8.3.3.7 Send Interrupt
              8. 9.4.8.8.3.3.8 Reload List
              9. 9.4.8.8.3.3.9 Abort Channel
        9. 9.4.8.9  VPDMA Configuration
          1. 9.4.8.9.1 Regular List
          2. 9.4.8.9.2 Video Input Ports
            1. 9.4.8.9.2.1 Multiplexed Data Streams
            2. 9.4.8.9.2.2 Single YUV Color Separate
            3. 9.4.8.9.2.3 Dual YUV Interleaved
        10. 9.4.8.10 VPDMA Data Formats
          1. 9.4.8.10.1 YUV Data Formats
            1. 9.4.8.10.1.1 Y 4:4:4 (Data Type 0)
            2. 9.4.8.10.1.2 Y 4:2:2 (Data Type 1)
            3. 9.4.8.10.1.3 Y 4:2:0 (Data Type 2)
            4. 9.4.8.10.1.4 C 4:4:4 (Data Type 4)
            5. 9.4.8.10.1.5 C 4:2:2 (Data Type 5)
            6. 9.4.8.10.1.6 C 4:2:0 (Data Type 6)
            7. 9.4.8.10.1.7 YC 4:2:2 (Data Type 7)
            8. 9.4.8.10.1.8 YC 4:4:4 (Data Type 8)
            9. 9.4.8.10.1.9 CY 4:2:2 (Data Type 23)
          2. 9.4.8.10.2 RGB Data Formats
            1. 9.4.8.10.2.1  RGB16-565 (Data Type 0)
            2. 9.4.8.10.2.2  ARGB-1555 (Data Type 1)
            3. 9.4.8.10.2.3  ARGB-4444 (Data Type 2)
            4. 9.4.8.10.2.4  RGBA-5551 (Data Type 3)
            5. 9.4.8.10.2.5  RGBA-4444 (Data Type 4)
            6. 9.4.8.10.2.6  ARGB24-6666 (Data Type 5)
            7. 9.4.8.10.2.7  RGB24-888 (Data Type 6)
            8. 9.4.8.10.2.8  ARGB32-8888 (Data Type 7)
            9. 9.4.8.10.2.9  RGBA24-6666 (Data Type 8)
            10. 9.4.8.10.2.10 RGBA32-8888 (Data Type 9)
          3. 9.4.8.10.3 Miscellaneous Data Type
    5. 9.5 VIP Register Manual
      1. 9.5.1 VIP Instance Summary
      2. 9.5.2 VIP Top Level Registers
        1. 9.5.2.1 VIP Top Level Register Summary
        2. 9.5.2.2 VIP Top Level Register Description
      3. 9.5.3 VIP Parser Registers
        1. 9.5.3.1 VIP Parser Register Summary
        2. 9.5.3.2 VIP Parser Register Description
      4. 9.5.4 VIP CSC Registers
        1. 9.5.4.1 VIP CSC Register Summary
        2. 9.5.4.2 VIP CSC Register Description
      5. 9.5.5 VIP SC registers
        1. 9.5.5.1 VIP SC Register Summary
        2. 9.5.5.2 VIP SC Register Description
      6. 9.5.6 VIP VPDMA Registers
        1. 9.5.6.1 VIP VPDMA Register Summary
        2. 9.5.6.2 VIP VPDMA Register Description
  12. 10Video Processing Engine
    1. 10.1 VPE Overview
    2. 10.2 VPE Integration
    3. 10.3 VPE Functional Description
      1. 10.3.1  VPE Block Diagram
      2. 10.3.2  VPE VC1 Range Mapping/Range Reduction
      3. 10.3.3  VPE Deinterlacer (DEI)
        1. 10.3.3.1 Functional Description
        2. 10.3.3.2 Bypass Mode
        3. 10.3.3.3 1734
          1. 10.3.3.3.1 VPDMA Interface
          2. 10.3.3.3.2 MDT
          3. 10.3.3.3.3 EDI
          4. 10.3.3.3.4 FMD
          5. 10.3.3.3.5 MUX
          6. 10.3.3.3.6 LINE BUFFER
      4. 10.3.4  VPE Scaler (SC)
        1. 10.3.4.1 SC Features
        2. 10.3.4.2 SC Functional Description
          1. 10.3.4.2.1 Trimmer
          2. 10.3.4.2.2 1745
          3. 10.3.4.2.3 Peaking
          4. 10.3.4.2.4 Vertical Scaler
            1. 10.3.4.2.4.1 Running Average Filter
            2. 10.3.4.2.4.2 Vertical Scaler Configuration Parameters
          5. 10.3.4.2.5 Horizontal Scaler
            1. 10.3.4.2.5.1 Half Decimation Filter
            2. 10.3.4.2.5.2 Polyphase Filter
            3. 10.3.4.2.5.3 Nonlinear Horizontal Scaling
            4. 10.3.4.2.5.4 Horizontal Scaler Configuration Registers
          6. 10.3.4.2.6 Basic Configurations
          7. 10.3.4.2.7 Coefficient Memory
            1. 10.3.4.2.7.1 Overview
            2. 10.3.4.2.7.2 Physical Coefficient SRAM Layout
            3. 10.3.4.2.7.3 Scaler Coefficients Packing on 128-bit VPI Control I/F
            4. 10.3.4.2.7.4 VPI Control I/F Memory Map for Scaler Coefficients
            5. 10.3.4.2.7.5 VPI Control Interface
            6. 10.3.4.2.7.6 Coefficient Table Selection Guide
        3. 10.3.4.3 SC Code
          1. 10.3.4.3.1 Generate Coefficient Memory Image
          2. 10.3.4.3.2 Scaler Configuration Calculation
          3. 10.3.4.3.3 Typical Configuration Values
        4. 10.3.4.4 SC Coefficient Data Files
          1. 10.3.4.4.1 HS Polyphase Filter Coefficients
            1. 10.3.4.4.1.1 ppfcoef_scale_eq_1_32_phases_flip.dat
            2. 10.3.4.4.1.2 ppfcoef_scale_eq_8div16_32_phases_flip.dat
            3. 10.3.4.4.1.3 ppfcoef_scale_eq_9div16_32_phases_flip.dat
            4. 10.3.4.4.1.4 ppfcoef_scale_eq_10div16_32_phases_flip.dat
            5. 10.3.4.4.1.5 ppfcoef_scale_eq_11div16_32_phases_flip.dat
            6. 10.3.4.4.1.6 ppfcoef_scale_eq_12div16_32_phases_flip.dat
            7. 10.3.4.4.1.7 ppfcoef_scale_eq_13div16_32_phases_flip.dat
            8. 10.3.4.4.1.8 ppfcoef_scale_eq_14div16_32_phases_flip.dat
            9. 10.3.4.4.1.9 ppfcoef_scale_eq_15div16_32_phases_flip.dat
          2. 10.3.4.4.2 VS Polyphase Filter Coefficients
            1. 10.3.4.4.2.1 ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
            2. 10.3.4.4.2.2 ppfcoef_scale_eq_3_32_phases_flip.dat
            3. 10.3.4.4.2.3 ppfcoef_scale_eq_4_32_phases_flip.dat
            4. 10.3.4.4.2.4 ppfcoef_scale_eq_5_32_phases_flip.dat
            5. 10.3.4.4.2.5 ppfcoef_scale_eq_6_32_phases_flip.dat
            6. 10.3.4.4.2.6 ppfcoef_scale_eq_7_32_phases_flip.dat
              1. 10.3.4.4.2.6.1 ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
              2. 10.3.4.4.2.6.2 ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
              3. 10.3.4.4.2.6.3 ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
              4. 10.3.4.4.2.6.4 ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
              5. 10.3.4.4.2.6.5 ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
              6. 10.3.4.4.2.6.6 ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
              7. 10.3.4.4.2.6.7 ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
              8. 10.3.4.4.2.6.8 ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
              9. 10.3.4.4.2.6.9 ppcoef_scale_1x_ver_5tap.dat
          3. 10.3.4.4.3 VS (Bilinear Filter Coefficients)
            1. 10.3.4.4.3.1 ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
      5. 10.3.5  VPE Color Space Converter (CSC)
        1. 10.3.5.1 CSC Features
        2. 10.3.5.2 CSC Functional Description
        3. 10.3.5.3 1799
          1. 10.3.5.3.1 HDTV Application
            1. 10.3.5.3.1.1 HDTV Application with Video Data Range
            2. 10.3.5.3.1.2 HDTV Application with Graphics Data Range
            3. 10.3.5.3.1.3 Quantized Coefficients for Color Space Converter in HDTV
          2. 10.3.5.3.2 SDTV Application
            1. 10.3.5.3.2.1 SDTV Application with Video Data Range
            2. 10.3.5.3.2.2 SDTV Application with Graphics Data Range
            3. 10.3.5.3.2.3 Quantized Coefficients for Color Space Converter in SDTV
        4. 10.3.5.4 CSC Bypass Mode
      6. 10.3.6  VPE Chroma Up-Sampler (CHR_US)
        1. 10.3.6.1 Features
        2. 10.3.6.2 Functional Description
        3. 10.3.6.3 For Interlaced YUV420 Input Data
        4. 10.3.6.4 Edge Effects
        5. 10.3.6.5 Modes of Operation (VPDMA)
        6. 10.3.6.6 Coefficient Configuration
      7. 10.3.7  VPE Chroma Down-Sampler (CHR_DS)
      8. 10.3.8  VPE YUV422 to YUV444 Conversion
      9. 10.3.9  VPE Video Port Direct Memory Access (VPDMA)
        1. 10.3.9.1 VPDMA Introduction
        2. 10.3.9.2 VPDMA Basic Definitions
          1. 10.3.9.2.1 Client
          2. 10.3.9.2.2 Channel
          3. 10.3.9.2.3 List
          4. 10.3.9.2.4 Data Formats Supported
        3. 10.3.9.3 VPDMA Client Buffering and Functionality
        4. 10.3.9.4 VPDMA Channels Assignment
        5. 10.3.9.5 VPDMA Interrupts
        6. 10.3.9.6 VPDMA Descriptors
          1. 10.3.9.6.1 Data Transfer Descriptors
            1. 10.3.9.6.1.1 Data Packet Descriptor Word 0 (Data)
              1. 10.3.9.6.1.1.1 Data Type
              2. 10.3.9.6.1.1.2 Notify
              3. 10.3.9.6.1.1.3 Field
              4. 10.3.9.6.1.1.4 1D
              5. 10.3.9.6.1.1.5 Even Line Skip
              6. 10.3.9.6.1.1.6 Odd Line Skip
              7. 10.3.9.6.1.1.7 Line Stride
            2. 10.3.9.6.1.2 Data Packet Descriptor Word 1
              1. 10.3.9.6.1.2.1 Line Length
              2. 10.3.9.6.1.2.2 Transfer Height
            3. 10.3.9.6.1.3 Data Packet Descriptor Word 2
              1. 10.3.9.6.1.3.1 Start Address
            4. 10.3.9.6.1.4 Data Packet Descriptor Word 3
              1. 10.3.9.6.1.4.1 Packet Type
              2. 10.3.9.6.1.4.2 Mode
              3. 10.3.9.6.1.4.3 Direction
              4. 10.3.9.6.1.4.4 Channel
              5. 10.3.9.6.1.4.5 Priority
              6. 10.3.9.6.1.4.6 Next Channel
            5. 10.3.9.6.1.5 Data Packet Descriptor Word 4
              1. 10.3.9.6.1.5.1 Inbound data
                1. 10.3.9.6.1.5.1.1 Frame Width
                2. 10.3.9.6.1.5.1.2 Frame Height
              2. 10.3.9.6.1.5.2 Outbound data
                1. 10.3.9.6.1.5.2.1 Descriptor Write Address
                2. 10.3.9.6.1.5.2.2 Write Descriptor
                3. 10.3.9.6.1.5.2.3 Drop Data
                4. 10.3.9.6.1.5.2.4 Use Descriptor Register
            6. 10.3.9.6.1.6 Data Packet Descriptor Word 5
              1. 10.3.9.6.1.6.1 Outbound data
                1. 10.3.9.6.1.6.1.1 Max Width
                2. 10.3.9.6.1.6.1.2 Max Height
            7. 10.3.9.6.1.7 Data Packet Descriptor Word 6/7 (Data)
          2. 10.3.9.6.2 Configuration Descriptor
            1. 10.3.9.6.2.1 Configuration Descriptor Header Word0
            2. 10.3.9.6.2.2 Configuration Descriptor Header Word1
              1. 10.3.9.6.2.2.1 Number of Data Words
            3. 10.3.9.6.2.3 Configuration Descriptor Header Word2
              1. 10.3.9.6.2.3.1 Payload Location
            4. 10.3.9.6.2.4 Configuration Descriptor Header Word3
              1. 10.3.9.6.2.4.1 Packet Type
              2. 10.3.9.6.2.4.2 Direct
              3. 10.3.9.6.2.4.3 Class
                1. 10.3.9.6.2.4.3.1 Address Data Block Format
              4. 10.3.9.6.2.4.4 Destination
              5. 10.3.9.6.2.4.5 Descriptor Length
          3. 10.3.9.6.3 Control Descriptor
            1. 10.3.9.6.3.1 Generic Control Descriptor Format
            2. 10.3.9.6.3.2 Control Descriptor Header Description
              1. 10.3.9.6.3.2.1 Packet Type
              2. 10.3.9.6.3.2.2 Source
              3. 10.3.9.6.3.2.3 Control
            3. 10.3.9.6.3.3 Control Descriptor Types
              1. 10.3.9.6.3.3.1 Sync on Client
              2. 10.3.9.6.3.3.2 Sync on List
              3. 10.3.9.6.3.3.3 Sync on External Event
              4. 10.3.9.6.3.3.4 Sync on Channel
              5. 10.3.9.6.3.3.5 Sync on LM Timer
              6. 10.3.9.6.3.3.6 Change Client Interrupt
              7. 10.3.9.6.3.3.7 Send Interrupt
              8. 10.3.9.6.3.3.8 Reload List
              9. 10.3.9.6.3.3.9 Abort Channel
        7. 10.3.9.7 VPDMA Configuration
          1. 10.3.9.7.1 Regular List
          2. 10.3.9.7.2 Video Input Ports
            1. 10.3.9.7.2.1 Single YUV Color Separate
            2. 10.3.9.7.2.2 Dual YUV Interleaved
            3. 10.3.9.7.2.3 Single RGB Stream
        8. 10.3.9.8 VPDMA Data Formats
          1. 10.3.9.8.1 YUV Data Formats
            1. 10.3.9.8.1.1 Y 4:4:4 (Data Type 0)
            2. 10.3.9.8.1.2 Y 4:2:2 (Data Type 1)
            3. 10.3.9.8.1.3 Y 4:2:0 (Data Type 2)
            4. 10.3.9.8.1.4 C 4:4:4 (Data Type 4)
            5. 10.3.9.8.1.5 C 4:2:2 (Data Type 5)
            6. 10.3.9.8.1.6 C 4:2:0 (Data Type 6)
            7. 10.3.9.8.1.7 YC 4:2:2 (Data Type 7)
            8. 10.3.9.8.1.8 YC 4:4:4 (Data Type 8)
            9. 10.3.9.8.1.9 CY 4:2:2 (Data Type 23)
          2. 10.3.9.8.2 RGB Data Formats
            1. 10.3.9.8.2.1 Input Data Formats
              1. 10.3.9.8.2.1.1  RGB16-565 (Data Type 0)
              2. 10.3.9.8.2.1.2  ARGB-1555 (Data Type 1)
              3. 10.3.9.8.2.1.3  ARGB-4444 (Data Type 2)
              4. 10.3.9.8.2.1.4  RGBA-5551 (Data Type 3)
              5. 10.3.9.8.2.1.5  RGBA-4444 (Data Type 4)
              6. 10.3.9.8.2.1.6  ARGB24-6666 (Data Type 5)
              7. 10.3.9.8.2.1.7  RGB24-888 (Data Type 6)
              8. 10.3.9.8.2.1.8  ARGB32-8888 (Data Type 7)
              9. 10.3.9.8.2.1.9  RGBA24-6666 (Data Type 8)
              10. 10.3.9.8.2.1.10 RGBA32-8888 (Data Type 9)
            2. 10.3.9.8.2.2 Output Data Formats
              1. 10.3.9.8.2.2.1  RGB16-565 (Data Type 0)
              2. 10.3.9.8.2.2.2  ARGB-1555 (Data Type 1)
              3. 10.3.9.8.2.2.3  ARGB-4444 (Data Type 2)
              4. 10.3.9.8.2.2.4  RGBA-5551 (Data Type 3)
              5. 10.3.9.8.2.2.5  RGBA-4444 (Data Type 4)
              6. 10.3.9.8.2.2.6  ARGB24-6666 (Data Type 5)
              7. 10.3.9.8.2.2.7  RGB24-888 (Data Type 6)
              8. 10.3.9.8.2.2.8  ARGB32-8888 (Data Type 7)
              9. 10.3.9.8.2.2.9  RGBA24-6666 (Data Type 8)
              10. 10.3.9.8.2.2.10 RGBA32-8888 (Data Type 9)
          3. 10.3.9.8.3 Miscellaneous Data Type
      10. 10.3.10 VPE Software Reset
      11. 10.3.11 VPE Power and Clocks Management
        1. 10.3.11.1 VPE Clocks
        2. 10.3.11.2 VPE Idle Mode
        3. 10.3.11.3 VPE StandBy Mode
    4. 10.4 VPE Register Manual
      1. 10.4.1 VPE Instance Summary
      2. 10.4.2 VPE_CSC Registers
        1. 10.4.2.1 VPE_CSC Register Summary
        2. 10.4.2.2 VPE_CSC Register Description
      3. 10.4.3 VPE_SC Registers
        1. 10.4.3.1 VPE_SC Register Summary
        2. 10.4.3.2 VPE_SC Register Description
      4. 10.4.4 VPE_CHR_US Registers
        1. 10.4.4.1 VPE_CHR_US Register Summary
        2. 10.4.4.2 VPE_CHR_US Register Description
      5. 10.4.5 VPE_DEI Registers
        1. 10.4.5.1 VPE_DEI Register Summary
        2. 10.4.5.2 VPE_DEI Register Description
      6. 10.4.6 VPE_VPDMA Registers
        1. 10.4.6.1 VPE_VPDMA Register Summary
        2. 10.4.6.2 VPE_VPDMA Register Description
      7. 10.4.7 VPE_TOP_LEVEL Registers
        1. 10.4.7.1 VPE_TOP_LEVEL Register Summary
        2. 10.4.7.2 VPE_TOP_LEVEL Register Description
  13. 11Display Subsystem
    1. 11.1 Display Subsystem Overview
      1. 11.1.1 Display Subsystem Environment
        1. 11.1.1.1 Display Subsystem LCD Support
          1. 11.1.1.1.1 Display Subsystem LCD with Parallel Interfaces
        2. 11.1.1.2 Display Subsystem TV Display Support
          1. 11.1.1.2.1 Display Subsystem TV With Parallel Interfaces
          2. 11.1.1.2.2 Display Subsystem TV With Serial Interfaces
      2. 11.1.2 Display Subsystem Integration
        1. 11.1.2.1 Display Subsystem Clocks
        2. 11.1.2.2 Display Subsystem Resets
        3. 11.1.2.3 Display Subsystem Power Management
          1. 11.1.2.3.1 Display Subsystem Standby Mode
          2. 11.1.2.3.2 1972
          3. 11.1.2.3.3 Display Subsystem Wake-Up Mode
      3. 11.1.3 Display Subsystem DPLL Controllers Functional Description
        1. 11.1.3.1 DPLL Controllers Overview
        2. 11.1.3.2 OCP2SCP2 Functional Description
          1. 11.1.3.2.1 OCP2SCP2 Reset
            1. 11.1.3.2.1.1 Hardware Reset
            2. 11.1.3.2.1.2 Software Reset
          2. 11.1.3.2.2 OCP2SCP2 Power Management
            1. 11.1.3.2.2.1 Idle Mode
            2. 11.1.3.2.2.2 Clock Gating
          3. 11.1.3.2.3 OCP2SCP2 Timing Registers
        3. 11.1.3.3 DPLL_VIDEO Functional Description
          1. 11.1.3.3.1 DPLL_VIDEO Controller Architecture
          2. 11.1.3.3.2 DPLL_VIDEO Operations
          3. 11.1.3.3.3 DPLL_VIDEO Error Handling
          4. 11.1.3.3.4 DPLL_VIDEO Software Reset
          5. 11.1.3.3.5 DPLL_VIDEO Power Management
          6. 11.1.3.3.6 DPLL_VIDEO HSDIVIDER Loading Operation
          7. 11.1.3.3.7 DPLL_VIDEO Clock Sequence
          8. 11.1.3.3.8 DPLL_VIDEO Go Sequence
          9. 11.1.3.3.9 DPLL_VIDEO Recommended Values
        4. 11.1.3.4 DPLL_HDMI Functional Description
          1. 11.1.3.4.1  DPLL_HDMI and PLLCTRL_HDMI Overview
          2. 11.1.3.4.2  DPLL_HDMI and PLLCTRL_HDMI Architecture
          3. 11.1.3.4.3  DPLL_HDMI Operations
          4. 11.1.3.4.4  DPLL_HDMI Register Access
          5. 11.1.3.4.5  DPLL_HDMI Error Handling
          6. 11.1.3.4.6  DPLL_HDMI Software Reset
          7. 11.1.3.4.7  DPLL_HDMI Power Management
          8. 11.1.3.4.8  DPLL_HDMI Lock Sequence
          9. 11.1.3.4.9  DPLL_HDMI Go Sequence
          10. 11.1.3.4.10 DPLL_HDMI Recommended Values
      4. 11.1.4 Display Subsystem Programming Guide
      5. 11.1.5 Display Subsystem Register Manual
        1. 11.1.5.1 Display Subsystem Instance Summary
        2. 11.1.5.2 Display Subsystem Registers
          1. 11.1.5.2.1 Display Subsystem Registers Mapping Summary
          2. 11.1.5.2.2 Display Subsystem Register Description
        3. 11.1.5.3 OCP2SCP2 registers
          1. 11.1.5.3.1 OCP2SCP2 Register Summary
          2. 11.1.5.3.2 OCP2SCP Register Description
        4. 11.1.5.4 DPLL_VIDEO Registers
          1. 11.1.5.4.1 DPLL_VIDEO Register Summary
          2. 11.1.5.4.2 DPLL_VIDEO Register Description
        5. 11.1.5.5 DPLL_HDMI Registers
          1. 11.1.5.5.1 DPLL_HDMI Registers Mapping Summary
          2. 11.1.5.5.2 DPLL_HDMI Register Description
        6. 11.1.5.6 HDMI_WP Registers
          1. 11.1.5.6.1 HDMI_WP Registers Mapping Summary
          2. 11.1.5.6.2 HDMI_WP Register Description
        7. 11.1.5.7 DSI Registers
          1. 11.1.5.7.1 DSI Register Summary
          2. 11.1.5.7.2 DSI Register Description
    2. 11.2 Display Controller
      1. 11.2.1 DISPC Overview
      2. 11.2.2 DISPC Environment
        1. 11.2.2.1 DISPC LCD Output and Data Format for the Parallel Interface
        2. 11.2.2.2 DISPC Transaction Timing Diagrams
        3. 11.2.2.3 DISPC TV Output and Data Format for the Parallel Interface
      3. 11.2.3 DISPC Integration
      4. 11.2.4 DISPC Functional Description
        1. 11.2.4.1  DISPC Clock Configuration
        2. 11.2.4.2  DISPC Software Reset
        3. 11.2.4.3  DISPC Power Management
          1. 11.2.4.3.1 DISPC Idle Mode
          2. 11.2.4.3.2 DISPC StandBy Mode
          3. 11.2.4.3.3 DISPC Wakeup
        4. 11.2.4.4  DISPC Interrupt Requests
        5. 11.2.4.5  DISPC DMA Requests
        6. 11.2.4.6  DISPC DMA Engine
          1. 11.2.4.6.1 DISPC Addressing and Bursts
          2. 11.2.4.6.2 DISPC Immediate Base Address Flip Mechanism
          3. 11.2.4.6.3 DISPC DMA Buffers
            1. 11.2.4.6.3.1 DISPC READ DMA Buffers (GFX and VID Pipelines)
            2. 11.2.4.6.3.2 DISPC WRITE DMA Buffer (WB Pipeline)
          4. 11.2.4.6.4 DISPC MFLAG Mechanism and Arbitration
          5. 11.2.4.6.5 DISPC Predecimation
          6. 11.2.4.6.6 DISPC Progressive-to-Interlaced Format Conversion
          7. 11.2.4.6.7 DISPC Arbitration
          8. 11.2.4.6.8 DISPC DMA Power Modes
            1. 11.2.4.6.8.1 DISPC DMA Low-Power Mode
            2. 11.2.4.6.8.2 DISPC DMA Ultralow-Power Mode
        7. 11.2.4.7  DISPC Rotation and Mirroring
        8. 11.2.4.8  DISPC Memory Format
        9. 11.2.4.9  DISPC Graphics Pipeline
          1. 11.2.4.9.1 DISPC Replication Logic
          2. 11.2.4.9.2 DISPC Antiflicker Filter
        10. 11.2.4.10 DISPC Video Pipelines
          1. 11.2.4.10.1 DISPC Replication Logic
          2. 11.2.4.10.2 DISPC VC-1 Range Mapping Unit
          3. 11.2.4.10.3 DISPC CSC Unit YUV to RGB
            1. 11.2.4.10.3.1 DISPC Chrominance Resampling
          4. 11.2.4.10.4 DISPC Scaler Unit
            1. 11.2.4.10.4.1 DISPC Scaling Algorithms
            2. 11.2.4.10.4.2 DISPC Scaling limitations
        11. 11.2.4.11 DISPC Write-Back Pipeline
          1. 11.2.4.11.1 DISPC Write-Back CSC Unit RGB to YUV
          2. 11.2.4.11.2 DISPC Write-Back Scaler Unit
          3. 11.2.4.11.3 DISPC Write-Back RGB Truncation Logic
        12. 11.2.4.12 DISPC Hardware Cursor
        13. 11.2.4.13 DISPC LCD Outputs
          1. 11.2.4.13.1 DISPC Overlay Manager
            1. 11.2.4.13.1.1 DISPC Priority Rule
            2. 11.2.4.13.1.2 DISPC Alpha Blender
            3. 11.2.4.13.1.3 DISPC Transparency Color Keys
            4. 11.2.4.13.1.4 DISPC Overlay Optimization
          2. 11.2.4.13.2 DISPC Gamma Correction Unit
          3. 11.2.4.13.3 DISPC Color Phase Rotation Unit
          4. 11.2.4.13.4 DISPC Color Space Conversion
          5. 11.2.4.13.5 DISPC BT.656 and BT.1120 Modes
            1. 11.2.4.13.5.1 Blanking
            2. 11.2.4.13.5.2 EAV and SAV
          6. 11.2.4.13.6 DISPC Active Matrix
            1. 11.2.4.13.6.1 DISPC Spatial/Temporal Dithering
            2. 11.2.4.13.6.2 DISPC Multiple Cycle Output Format (TDM)
          7. 11.2.4.13.7 DISPC Synchronized Buffer Update
          8. 11.2.4.13.8 DISPC Timing Generator and Panel Settings
        14. 11.2.4.14 DISPC TV Output
          1. 11.2.4.14.1 DISPC Overlay Manager
          2. 11.2.4.14.2 DISPC Gamma Correction Unit
          3. 11.2.4.14.3 DISPC Synchronized Buffer Update
          4. 11.2.4.14.4 DISPC Timing and TV Format Settings
        15. 11.2.4.15 DISPC Frame Width Considerations
        16. 11.2.4.16 DISPC Extended 3D Support
          1. 11.2.4.16.1 DISPC Extended 3D Support - Line Alternative Format
          2. 11.2.4.16.2 2098
          3. 11.2.4.16.3 DISPC Extended 3D Support - Frame Packing Format Format
          4. 11.2.4.16.4 DISPC Extended 3D Support - DLP 3D Format
        17. 11.2.4.17 DISPC Shadow Registers
      5. 11.2.5 DISPC Programming Guide
        1. 11.2.5.1 DISPC Low-Level Programming Models
          1. 11.2.5.1.1 DISPC Global Initialization
            1. 11.2.5.1.1.1 DISPC Surrounding Modules Global Initialization
          2. 11.2.5.1.2 DISPC Operational Modes Configuration
            1. 11.2.5.1.2.1 DISPC DMA Configuration
              1. 11.2.5.1.2.1.1 DISPC Main Sequence – DISPC DMA Channel Configuration
            2. 11.2.5.1.2.2 DISPC GFX Pipeline Configuration
              1. 11.2.5.1.2.2.1 DISPC Main Sequence – Configure the GFX Pipeline
              2. 11.2.5.1.2.2.2 DISPC Subsequence – Configure the GFX Window
              3. 11.2.5.1.2.2.3 DISPC Subsequence – Configure the GFX Pipeline Processing
              4. 11.2.5.1.2.2.4 DISPC Subsequence – Configure the GFX Pipeline Layer Output
            3. 11.2.5.1.2.3 DISPC Video Pipeline Configuration
              1. 11.2.5.1.2.3.1 DISPC Main Sequence – Configure the Video Pipeline
              2. 11.2.5.1.2.3.2 DISPC Subsequence – Configure the Video Window
              3. 11.2.5.1.2.3.3 DISPC Subsequence – Configure the Video Pipeline Processing
              4. 11.2.5.1.2.3.4 DISPC Subsequence – Configure the VC-1 Range Mapping
              5. 11.2.5.1.2.3.5 DISPC Subsequence – Configure the Video Color Space Conversion
              6. 11.2.5.1.2.3.6 DISPC Subsequence – Configure the Video Scaler Unit
              7. 11.2.5.1.2.3.7 DISPC Subsequence – Configure the Video Pipeline Layer Output
            4. 11.2.5.1.2.4 DISPC WB Pipeline Configuration
              1. 11.2.5.1.2.4.1 DISPC Main Sequence – Configure the WB Pipeline
              2. 11.2.5.1.2.4.2 DISPC Subsequence – Configure the Capture Window
              3. 11.2.5.1.2.4.3 DISPC Subsequence – Configure the WB Scaler Unit
              4. 11.2.5.1.2.4.4 DISPC Subsequence – Configure the WB Color Space Conversion Unit
            5. 11.2.5.1.2.5 DISPC LCD Output Configuration
              1. 11.2.5.1.2.5.1 DISPC Main Sequence – Configure the LCD Output
              2. 11.2.5.1.2.5.2 DISPC Subsequence – Configure the Overlay Manager
              3. 11.2.5.1.2.5.3 DISPC Subsequence – Configure the Gamma Table for Gamma Correction
              4. 11.2.5.1.2.5.4 DISPC Subsequence – Configure the Color Phase Rotation
              5. 11.2.5.1.2.5.5 DISPC Subsequence – Configure the LCD Panel Timings and Parameters
              6. 11.2.5.1.2.5.6 DISPC Subsequence – Configure BT.656 or BT.1120 Mode
            6. 11.2.5.1.2.6 DISPC TV Output Configuration
              1. 11.2.5.1.2.6.1 DISPC Main Sequence – Configure the TV Output
                1. 11.2.5.1.2.6.1.1 DISPC Subsequence – Configure the TV Overlay Manager
                2. 11.2.5.1.2.6.1.2 DISPC Subsequence – Configure the Gamma Table for Gamma Correction
                3. 11.2.5.1.2.6.1.3 DISPC Subsequence – Configure the TV Panel Timings and Parameters
      6. 11.2.6 DISPC Register Manual
        1. 11.2.6.1 DISPC Instance Summary
        2. 11.2.6.2 DISPC Logical Register Mapping
        3. 11.2.6.3 DISPC Registers
          1. 11.2.6.3.1 DISPC Register Summary
          2. 11.2.6.3.2 DISPC Register Description
    3. 11.3 High-Definition Multimedia Interface
      1. 11.3.1 HDMI Overview
        1. 11.3.1.1 HDMI Main Features
        2. 11.3.1.2 HDMI Video Formats and Timings
          1. 11.3.1.2.1 HDMI CEA-861-D Video Formats and Timings
          2. 11.3.1.2.2 VESA DMT Video Formats and Timings
  14. 123D Graphics Accelerator
    1. 12.1 GPU Overview
      1. 12.1.1 GPU Features Overview
      2. 12.1.2 Graphics Feature Overview
    2. 12.2 GPU Integration
    3. 12.3 GPU Functional Description
      1. 12.3.1 GPU Block Diagram
      2. 12.3.2 GPU Clock Configuration
      3. 12.3.3 GPU Software Reset
      4. 12.3.4 GPU Power Management
      5. 12.3.5 GPU Thermal Management
      6. 12.3.6 GPU Interrupt Requests
    4. 12.4 GPU Register Manual
      1. 12.4.1 GPU Instance Summary
      2. 12.4.2 GPU Registers
        1. 12.4.2.1 GPU_WRAPPER Register Summary
        2. 12.4.2.2 GPU_WRAPPER Register Description
  15. 132D Graphics Accelerator
    1. 13.1 BB2D Overview
      1. 13.1.1 BB2D Key Features Overview
    2. 13.2 BB2D Integration
    3. 13.3 BB2D Functional Description
      1. 13.3.1 BB2D Block Diagram
      2. 13.3.2 BB2D Clock Configuration
      3. 13.3.3 BB2D Software Reset
      4. 13.3.4 BB2D Power Management
    4. 13.4 BB2D Register Manual
      1. 13.4.1 BB2D Instance Summary
      2. 13.4.2 BB2D Registers
        1. 13.4.2.1 BB2D Register Summary
        2. 13.4.2.2 BB2D Register Description
  16. 14Interconnect
    1. 14.1 Interconnect Overview
      1. 14.1.1 Terminology
      2. 14.1.2 Architecture Overview
    2. 14.2 L3_MAIN Interconnect
      1. 14.2.1 L3_MAIN Interconnect Overview
      2. 14.2.2 L3_MAIN Interconnect Integration
      3. 14.2.3 L3_MAIN Interconnect Functional Description
        1. 14.2.3.1 Module Use in L3_MAIN Interconnect
        2. 14.2.3.2 Module Distribution
          1. 14.2.3.2.1 L3_MAIN Interconnect Agents
          2. 14.2.3.2.2 L3_MAIN Connectivity Matrix
            1. 14.2.3.2.2.1 Clock Domain Mapping of the L3_MAIN Interconnect Modules
            2. 14.2.3.2.2.2 2195
          3. 14.2.3.2.3 Master NIU Identification
        3. 14.2.3.3 Bandwidth Regulators
        4. 14.2.3.4 Bandwidth Limiters
        5. 14.2.3.5 Flag Muxing
          1. 14.2.3.5.1 Flag Mux Time-out
        6. 14.2.3.6 Statistic Collectors Group
        7. 14.2.3.7 L3_MAIN Protection and Firewalls
          1. 14.2.3.7.1 L3_MAIN Firewall Reset
            1. 14.2.3.7.1.1 L3_MAIN Firewall – Exported Reset Values
          2. 14.2.3.7.2 Power Management
          3. 14.2.3.7.3 L3_MAIN Firewall Functionality
            1. 14.2.3.7.3.1 Protection Regions
            2. 14.2.3.7.3.2 L3_MAIN Firewall Registers Overview
            3. 14.2.3.7.3.3 Protection Mechanism per Region Examples
            4. 14.2.3.7.3.4 L3_MAIN Firewall Error Logging
            5. 14.2.3.7.3.5 L3_MAIN Firewall Default Configuration
        8. 14.2.3.8 L3_MAIN Interconnect Error Handling
          1. 14.2.3.8.1 Global Error-Routing Scheme
          2. 14.2.3.8.2 Slave NIU Error Logging
          3. 14.2.3.8.3 Flag Mux Error Logging
          4. 14.2.3.8.4 Severity Level of Standard and Custom Errors
          5. 14.2.3.8.5 Example for Decoding Standard/Custom Errors Logged in L3_MAIN
      4. 14.2.4 L3_MAIN Interconnect Programming Guide
        1. 14.2.4.1 L3 _MAIN Interconnect Low-Level Programming Models
          1. 14.2.4.1.1 Global Initialization
            1. 14.2.4.1.1.1 Global Initialization of Surrounding Modules
        2. 14.2.4.2 Operational Modes Configuration
          1. 14.2.4.2.1 L3_MAIN Interconnect Error Analysis Mode
            1. 14.2.4.2.1.1 Main Sequence: L3_MAIN Interconnect Error Analysis Mode
              1. 14.2.4.2.1.1.1 Subsequence: L3_MAIN Custom Error Identification
              2. 14.2.4.2.1.1.2 Subsequence: L3_MAIN Interconnect Protection Violation Error Identification
              3. 14.2.4.2.1.1.3 Subsequence: L3_MAIN Interconnect Standard Error Identification
              4. 14.2.4.2.1.1.4 Subsequence: L3_MAIN Interconnect FLAGMUX Configuration
      5. 14.2.5 L3_MAIN Interconnect Register Manual
        1. 14.2.5.1 L3_MAIN Register Group Summary
          1. 14.2.5.1.1 L3_MAIN Firewall Registers Summary and Description
            1. 14.2.5.1.1.1 L3_MAIN Firewall Registers Summary
            2. 14.2.5.1.1.2 L3_MAIN Firewall Registers Description
          2. 14.2.5.1.2 L3_MAIN Host Register Summary and Description
            1. 14.2.5.1.2.1 L3_MAIN HOST Register Summary
            2. 14.2.5.1.2.2 L3_MAIN HOST Register Description
          3. 14.2.5.1.3 L3_MAIN TARG Register Summary and Description
            1. 14.2.5.1.3.1 L3_MAIN TARG Register Summary
            2. 14.2.5.1.3.2 L3_MAIN TARG Register Description
          4. 14.2.5.1.4 L3_MAIN FLAGMUX Registers Summary and Description
            1. 14.2.5.1.4.1 L3_MAIN FLAGMUX Registers Summary
            2. 14.2.5.1.4.2 L3_MAIN FLAGMUX Rebisters Description
          5. 14.2.5.1.5 L3_MAIN FLAGMUX CLK1MERGE Registers Summary and Description
            1. 14.2.5.1.5.1 L3_MAIN FLAGMUX CLK1MERGE Registers Summary
            2. 14.2.5.1.5.2 L3_MAIN FLAGMUX CLK1MERGE Registers Description
          6. 14.2.5.1.6 L3_MAIN FLAGMUX TIMEOUT Registers Summary and Description
            1. 14.2.5.1.6.1 L3_MAIN FLAGMUX TIMEOUT Registers Summary
            2. 14.2.5.1.6.2 L3_MAIN FLAGMUX TIMEOUT Registers Description
          7. 14.2.5.1.7 L3_MAIN BW Regulator Register Summary and Description
            1. 14.2.5.1.7.1 L3_MAIN BW_REGULATOR Register Summary
            2. 14.2.5.1.7.2 L3_MAIN BW_REGULATOR Register Description
          8. 14.2.5.1.8 L3_MAIN Bandwidth Limiter Register Summary and Description
            1. 14.2.5.1.8.1 L3_MAIN BW Limiter Register Summary
            2. 14.2.5.1.8.2 L3_MAIN BW Limiter Register Description
          9. 14.2.5.1.9 L3_MAIN STATCOLL Register Summary and Description
            1. 14.2.5.1.9.1 L3_MAIN STATCOLL Register Summary
            2. 14.2.5.1.9.2 L3_MAIN STATCOLL Register Description
    3. 14.3 L4 Interconnects
      1. 14.3.1 L4 Interconnect Overview
      2. 14.3.2 L4 Interconnect Integration
      3. 14.3.3 L4 Interconnect Functional Description
        1. 14.3.3.1 Module Distribution
          1. 14.3.3.1.1 L4_PER1 Interconnect Agents
          2. 14.3.3.1.2 L4_PER2 Interconnect Agents
          3. 14.3.3.1.3 L4_PER3 Interconnect Agents
          4. 14.3.3.1.4 L4_CFG Interconnect Agents
          5. 14.3.3.1.5 L4_WKUP Interconnect Agents
        2. 14.3.3.2 Power Management
        3. 14.3.3.3 L4 Firewalls
          1. 14.3.3.3.1 Protection Group
          2. 14.3.3.3.2 Segments and Regions
          3. 14.3.3.3.3 L4 Firewall Address and Protection Register Settings
        4. 14.3.3.4 L4 Error Detection and Reporting
          1. 14.3.3.4.1 IA and TA Error Detection and Logging
          2. 14.3.3.4.2 Time-Out
          3. 14.3.3.4.3 Error Reporting
          4. 14.3.3.4.4 Error Recovery
          5. 14.3.3.4.5 Firewall Error Logging in the Control Module
      4. 14.3.4 L4 Interconnect Programming Guide
        1. 14.3.4.1 L4 Interconnect Low-level Programming Models
          1. 14.3.4.1.1 Global Initialization
            1. 14.3.4.1.1.1 Surrounding Modules Global Initialization
          2. 14.3.4.1.2 Operational Modes Configuration
            1. 14.3.4.1.2.1 L4 Interconnect Error Analysis Mode
              1. 14.3.4.1.2.1.1 Main Sequence: L4 Interconnect Error Analysis Mode
              2. 14.3.4.1.2.1.2 Subsequence: L4 Interconnect Protection Violation Error Identification
              3. 14.3.4.1.2.1.3 Subsequence: L4 Interconnect Unsupported Command/Address Hole Error Identification
              4. 14.3.4.1.2.1.4 Subsequence: L4 Interconnect Reset TA and Module
            2. 14.3.4.1.2.2 L4 Interconnect Time-Out Configuration Mode
              1. 14.3.4.1.2.2.1 Main Sequence: L4 Interconnect Time-Out Configuration Mode
            3. 14.3.4.1.2.3 L4 Interconnect Firewall Configuration Mode
              1. 14.3.4.1.2.3.1 Main Sequence: L4 Interconnect Firewall Configuration Mode
      5. 14.3.5 L4 Interconnects Register Manual
        1. 14.3.5.1 L4 Interconnects Instance Summary
        2. 14.3.5.2 L4 Initiator Agent (L4 IA)
          1. 14.3.5.2.1 L4 Initiator Agent (L4 IA) Register Summary
          2. 14.3.5.2.2 L4 Initiator Agent (L4 IA) Register Description
        3. 14.3.5.3 L4 Target Agent (L4 TA)
          1. 14.3.5.3.1 L4 Target Agent (L4 TA) Register Summary
          2. 14.3.5.3.2 L4 Target Agent (L4 TA) Register Description
        4. 14.3.5.4 L4 Link Agent (L4 LA)
          1. 14.3.5.4.1 L4 Link Agent (L4 LA) Register Summary
          2. 14.3.5.4.2 L4 Link Agent (L4 LA) Register Description
        5. 14.3.5.5 L4 Address Protection (L4 AP)
          1. 14.3.5.5.1 L4 Address Protection (L4 AP) Register Summary
          2. 14.3.5.5.2 L4 Address Protection (L4 AP) Register Description
  17. 15Memory Subsystem
    1. 15.1 Memory Subsystem Overview
      1. 15.1.1 DMM Overview
      2. 15.1.2 TILER Overview
      3. 15.1.3 EMIF Overview
      4. 15.1.4 GPMC Overview
      5. 15.1.5 ELM Overview
      6. 15.1.6 OCM Overview
    2. 15.2 Dynamic Memory Manager
      1. 15.2.1 DMM Overview
      2. 15.2.2 DMM Integration
        1. 15.2.2.1 DMM Configuration
      3. 15.2.3 DMM Functional Description
        1. 15.2.3.1 DMM Block Diagram
        2. 15.2.3.2 DMM Clock Configuration
        3. 15.2.3.3 DMM Power Management
        4. 15.2.3.4 DMM Interrupt Requests
        5. 15.2.3.5 DMM
          1. 15.2.3.5.1 DMM Concepts
            1. 15.2.3.5.1.1 Dynamic Mapping
            2. 15.2.3.5.1.2 Address Mapping
            3. 15.2.3.5.1.3 Address Translation
              1. 15.2.3.5.1.3.1 PAT View Mappings
              2. 15.2.3.5.1.3.2 PAT View Map Base Address
              3. 15.2.3.5.1.3.3 PAT Views
                1. 15.2.3.5.1.3.3.1 PAT Direct Access Translation
                2. 15.2.3.5.1.3.3.2 PAT Indirect Access Translation
                3. 15.2.3.5.1.3.3.3 PAT View Configuration
                4. 15.2.3.5.1.3.3.4 PAT Address Translation LUT
                5. 15.2.3.5.1.3.3.5 Direct Access to the PAT Table Vectors
                6. 15.2.3.5.1.3.3.6 Automatic Refill Through the Refill Engines
          2. 15.2.3.5.2 DMM Transaction Flows
            1. 15.2.3.5.2.1 Nontiled Transaction Flow
            2. 15.2.3.5.2.2 Tiled Transaction Flow
          3. 15.2.3.5.3 DMM Internal Macro-Architecture
            1. 15.2.3.5.3.1 LISA Description
            2. 15.2.3.5.3.2 PAT Description
            3. 15.2.3.5.3.3 PEG Description
            4. 15.2.3.5.3.4 LISA Interconnect Arbitration
            5. 15.2.3.5.3.5 ROBIN Description
            6. 15.2.3.5.3.6 TILER Description
        6. 15.2.3.6 TILER
          1. 15.2.3.6.1 TILER Concepts
            1. 15.2.3.6.1.1 TILER Rationale
              1. 15.2.3.6.1.1.1 The TILER is a 4-GiB Virtual Address Space Composed of Eight Views
              2. 15.2.3.6.1.1.2 A View is a 512-MiB Virtual Address Space Composed of Four Containers
              3. 15.2.3.6.1.1.3 A Container is a 128-MiB Virtual Address Space
              4. 15.2.3.6.1.1.4 A Page is a 4-kiB Virtual Address Space
              5. 15.2.3.6.1.1.5 A Tile is a 1-kiB Address Space
              6. 15.2.3.6.1.1.6 2356
              7. 15.2.3.6.1.1.7 A Subtile is a 128-Bit Address Space
            2. 15.2.3.6.1.2 TILER Modes
              1. 15.2.3.6.1.2.1 Bypass Mode
              2. 15.2.3.6.1.2.2 Page Mode
              3. 15.2.3.6.1.2.3 Tiled Mode
            3. 15.2.3.6.1.3 Object Container Definition
            4. 15.2.3.6.1.4 Page Definition
              1. 15.2.3.6.1.4.1 Container Geometry With 4-kiB Pages
              2. 15.2.3.6.1.4.2 Container Geometry and Page Mapping Summary
            5. 15.2.3.6.1.5 Orientation
            6. 15.2.3.6.1.6 Tile Definition
            7. 15.2.3.6.1.7 Subtiles
              1. 15.2.3.6.1.7.1 Subtiling Definition
            8. 15.2.3.6.1.8 TILER Virtual Addressing
              1. 15.2.3.6.1.8.1 Page Mode Virtual Addressing and Characteristics
              2. 15.2.3.6.1.8.2 Tiled Mode Virtual Addressing and Characteristics
              3. 15.2.3.6.1.8.3 Element Ordering in the TILER Container
                1. 15.2.3.6.1.8.3.1 Natural View or 0-Degree View (Orientation 0)
                2. 15.2.3.6.1.8.3.2 0-Degree View With Vertical Mirror or 180-Degree View With Horizontal Mirror (Orientation 1)
                3. 15.2.3.6.1.8.3.3 0-Degree View With Horizontal Mirror or 180-Degree View With Vertical Mirror (Orientation 2)
                4. 15.2.3.6.1.8.3.4 180-Degree View (Orientation 3)
                5. 15.2.3.6.1.8.3.5 90-Degree View With Vertical Mirror or 270-Degree View With Horizontal Mirror (Orientation 4)
                6. 15.2.3.6.1.8.3.6 270-Degree View (Orientation 5)
                7. 15.2.3.6.1.8.3.7 90-Degree View (Orientation 6)
                8. 15.2.3.6.1.8.3.8 90-Degree View With Horizontal Mirror or 270-Degree View With Vertical Mirror (Orientation 7)
          2. 15.2.3.6.2 TILER Macro-Architecture
          3. 15.2.3.6.3 TILER Guidelines for Initiators
            1. 15.2.3.6.3.1 Buffered Raster-Based Initiators
              1. 15.2.3.6.3.1.1 Buffer Size
              2. 15.2.3.6.3.1.2 Performance
      4. 15.2.4 DMM Use Cases and Tips
        1. 15.2.4.1 PAT Use Cases
          1. 15.2.4.1.1 Simple Manual Area Refill
          2. 15.2.4.1.2 Single Auto-Configured Area Refill
          3. 15.2.4.1.3 Chained Auto-Configured Area Refill
          4. 15.2.4.1.4 Synchronized Auto-Configured Area Refill
          5. 15.2.4.1.5 Cyclic Synchronized Auto-Configured Area Refill
        2. 15.2.4.2 Addressing Management with LISA
          1. 15.2.4.2.1 Case 1: Use of One Memory Controller
          2. 15.2.4.2.2 Case 2: Use of Two Memory Controllers
            1. 15.2.4.2.2.1 Address Upper Bits Shifting
      5. 15.2.5 DMM Basic Programming Model
        1. 15.2.5.1 Global Initialization
        2. 15.2.5.2 DMM Module Global Initialization
        3. 15.2.5.3 DMM Operational Modes Configuration
          1. 15.2.5.3.1 Different Operational Modes
          2. 15.2.5.3.2 Configuration Settings and LUT Refill
          3. 15.2.5.3.3 Interleaving Settings
          4. 15.2.5.3.4 Aliased Tiled View Orientation Settings and LUT Refill
          5. 15.2.5.3.5 Priority Settings
          6. 15.2.5.3.6 Error Handling
          7. 15.2.5.3.7 PAT Programming Model
            1. 15.2.5.3.7.1 PAT in Direct Translation Mode
            2. 15.2.5.3.7.2 PAT in Indirect Translation Mode
        4. 15.2.5.4 Addressing an Object in Tiled Mode
          1. 15.2.5.4.1 Frame-Buffer Addressing
          2. 15.2.5.4.2 TILER Page Mapping
        5. 15.2.5.5 Addressing an Object in Page Mode
        6. 15.2.5.6 Sharing Containers Between Different Modes
      6. 15.2.6 DMM Register Manual
        1. 15.2.6.1 DMM Instance Summary
        2. 15.2.6.2 DMM Registers
          1. 15.2.6.2.1 DMM Register Summary
          2. 15.2.6.2.2 DMM Register Description
    3. 15.3 EMIF Controller
      1. 15.3.1 EMIF Controller Overview
      2. 15.3.2 EMIF Module Environment
      3. 15.3.3 EMIF Module Integration
      4. 15.3.4 EMIF Functional Description
        1. 15.3.4.1  Block Diagram
          1. 15.3.4.1.1 Local Interface
          2. 15.3.4.1.2 FIFO Description
          3. 15.3.4.1.3 MPU Port Restrictions
          4. 15.3.4.1.4 Arbitration of Commands in the Command FIFO
        2. 15.3.4.2  Clock Management
          1. 15.3.4.2.1 EMIF_FICLK Overview
          2. 15.3.4.2.2 EMIF Dependency on MPU Clock Rate
        3. 15.3.4.3  Reset
        4. 15.3.4.4  System Power Management
          1. 15.3.4.4.1 Power-Down Mode
          2. 15.3.4.4.2 Self-Refresh Mode
        5. 15.3.4.5  Interrupt Requests
        6. 15.3.4.6  SDRAM Refresh Scheduling
        7. 15.3.4.7  SDRAM Initialization
          1. 15.3.4.7.1 DDR2 SDRAM Initialization
          2. 15.3.4.7.2 DDR3 SDRAM Initialization
        8. 15.3.4.8  DDR3 Read-Write Leveling
          1. 15.3.4.8.1 Full Leveling
          2. 15.3.4.8.2 Software Leveling
        9. 15.3.4.9  EMIF Access Cycles
        10. 15.3.4.10 Turnaround Time
        11. 15.3.4.11 PHY DLL Calibration
        12. 15.3.4.12 SDRAM Address Mapping
          1. 15.3.4.12.1 Address Mapping for IBANK_POS = 0 and EBANK_POS = 0
          2. 15.3.4.12.2 Address Mapping for IBANK_POS = 1 and EBANK_POS = 0
          3. 15.3.4.12.3 Address Mapping for IBANK_POS = 2 and EBANK_POS = 0
          4. 15.3.4.12.4 Address Mapping for IBANK_POS = 3 and EBANK_POS = 0
          5. 15.3.4.12.5 Address Mapping for IBANK_POS = 0 and EBANK_POS = 1
          6. 15.3.4.12.6 Address Mapping for IBANK_POS = 1 and EBANK_POS = 1
          7. 15.3.4.12.7 Address Mapping for IBANK_POS = 2 and EBANK_POS = 1
          8. 15.3.4.12.8 2457
          9. 15.3.4.12.9 Address Mapping for IBANK_POS = 3 and EBANK_POS = 1
        13. 15.3.4.13 DDR3 Output Impedance Calibration
        14. 15.3.4.14 Error Correction And Detection Feature
        15. 15.3.4.15 Class of Service
        16. 15.3.4.16 Performance Counters
          1. 15.3.4.16.1 Performance Counters General Examples
        17. 15.3.4.17 Forcing CKE to tri-state
      5. 15.3.5 EMIF Programming Guide
        1. 15.3.5.1 EMIF Low-Level Programming Models
          1. 15.3.5.1.1 Global Initialization
            1. 15.3.5.1.1.1 EMIF Configuration Sequence
          2. 15.3.5.1.2 Operational Modes Configuration
            1. 15.3.5.1.2.1 EMIF Output Impedance Calibration Mode
            2. 15.3.5.1.2.2 EMIF SDRAM Self-Refresh
            3. 15.3.5.1.2.3 EMIF SDRAM Power-Down Mode
            4. 15.3.5.1.2.4 EMIF ECC Configuration
      6. 15.3.6 EMIF Register Manual
        1. 15.3.6.1 EMIF Instance Summary
        2. 15.3.6.2 EMIF Registers
          1. 15.3.6.2.1 EMIF Register Summary
          2. 15.3.6.2.2 EMIF Register Description
    4. 15.4 General-Purpose Memory Controller
      1. 15.4.1 GPMC Overview
      2. 15.4.2 GPMC Environment
        1. 15.4.2.1 GPMC Modes
        2. 15.4.2.2 GPMC Signals
      3. 15.4.3 GPMC Integration
      4. 15.4.4 GPMC Functional Description
        1. 15.4.4.1  GPMC Block Diagram
        2. 15.4.4.2  GPMC Clock Configuration
        3. 15.4.4.3  GPMC Software Reset
        4. 15.4.4.4  GPMC Power Management
        5. 15.4.4.5  GPMC Interrupt Requests
        6. 15.4.4.6  L3 Interconnect Interface
        7. 15.4.4.7  GPMC Address and Data Bus
          1. 15.4.4.7.1 GPMC I/O Configuration Setting
          2. 15.4.4.7.2 GPMC CS0 Default Configuration at Device Reset
        8. 15.4.4.8  Address Decoder and Chip-Select Configuration
          1. 15.4.4.8.1 Chip-Select Base Address and Region Size
          2. 15.4.4.8.2 Access Protocol
            1. 15.4.4.8.2.1 Supported Devices
            2. 15.4.4.8.2.2 Access Size Adaptation and Device Width
            3. 15.4.4.8.2.3 Address/Data-Multiplexing Interface
          3. 15.4.4.8.3 External Signals
            1. 15.4.4.8.3.1 Wait Pin Monitoring Control
              1. 15.4.4.8.3.1.1 Wait Monitoring During Asynchronous Read Access
              2. 15.4.4.8.3.1.2 Wait Monitoring During Asynchronous Write Access
              3. 15.4.4.8.3.1.3 Wait Monitoring During Synchronous Read Access
              4. 15.4.4.8.3.1.4 Wait Monitoring During Synchronous Write Access
              5. 15.4.4.8.3.1.5 Wait With NAND Device
              6. 15.4.4.8.3.1.6 Idle Cycle Control Between Successive Accesses
                1. 15.4.4.8.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                2. 15.4.4.8.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                3. 15.4.4.8.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
              7. 15.4.4.8.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
            2. 15.4.4.8.3.2 Reset
            3. 15.4.4.8.3.3 Byte Enable (nBE1/nBE0)
          4. 15.4.4.8.4 Error Handling
        9. 15.4.4.9  Timing Setting
          1. 15.4.4.9.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
          2. 15.4.4.9.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
          3. 15.4.4.9.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
          4. 15.4.4.9.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
          5. 15.4.4.9.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
          6. 15.4.4.9.6  GPMC_CLK
          7. 15.4.4.9.7  GPMC_CLK and Control Signals Setup and Hold
          8. 15.4.4.9.8  Access Time (RDACCESSTIME / WRACCESSTIME)
            1. 15.4.4.9.8.1 Access Time on Read Access
            2. 15.4.4.9.8.2 Access Time on Write Access
          9. 15.4.4.9.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
            1. 15.4.4.9.9.1 Page Burst Access Time on Read Access
            2. 15.4.4.9.9.2 Page Burst Access Time on Write Access
          10. 15.4.4.9.10 Bus Keeping Support
        10. 15.4.4.10 NOR Access Description
          1. 15.4.4.10.1 Asynchronous Access Description
            1. 15.4.4.10.1.1 Access on Address/Data Multiplexed Devices
              1. 15.4.4.10.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
              2. 15.4.4.10.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
              3. 15.4.4.10.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
            2. 15.4.4.10.1.2 Access on Address/Address/Data-Multiplexed Devices
              1. 15.4.4.10.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
              2. 15.4.4.10.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
              3. 15.4.4.10.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
          2. 15.4.4.10.2 Synchronous Access Description
            1. 15.4.4.10.2.1 Synchronous Single Read
            2. 15.4.4.10.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
            3. 15.4.4.10.2.3 Synchronous Single Write
            4. 15.4.4.10.2.4 Synchronous Multiple (Burst) Write
          3. 15.4.4.10.3 Asynchronous and Synchronous Accesses in Nonmultiplexed Mode
            1. 15.4.4.10.3.1 Asynchronous Single-Read Operation on Nonmultiplexed Device
            2. 15.4.4.10.3.2 Asynchronous Single-Write Operation on Nonmultiplexed Device
            3. 15.4.4.10.3.3 Asynchronous Multiple (Page Mode) Read Operation on Nonmultiplexed Device
            4. 15.4.4.10.3.4 Synchronous Operations on a Nonmultiplexed Device
          4. 15.4.4.10.4 Page and Burst Support
          5. 15.4.4.10.5 System Burst vs External Device Burst Support
        11. 15.4.4.11 pSRAM Access Specificities
        12. 15.4.4.12 NAND Access Description
          1. 15.4.4.12.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
            1. 15.4.4.12.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
            2. 15.4.4.12.1.2 NAND Device Command and Address Phase Control
            3. 15.4.4.12.1.3 Command Latch Cycle
            4. 15.4.4.12.1.4 Address Latch Cycle
            5. 15.4.4.12.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
            6. 15.4.4.12.1.6 NAND Device General Chip-Select Timing Control Requirement
            7. 15.4.4.12.1.7 Read and Write Access Size Adaptation
              1. 15.4.4.12.1.7.1 8-Bit-Wide NAND Device
              2. 15.4.4.12.1.7.2 16-Bit-Wide NAND Device
          2. 15.4.4.12.2 NAND Device-Ready Pin
            1. 15.4.4.12.2.1 Ready Pin Monitored by Software Polling
            2. 15.4.4.12.2.2 Ready Pin Monitored by Hardware Interrupt
          3. 15.4.4.12.3 ECC Calculator
            1. 15.4.4.12.3.1 Hamming Code
              1. 15.4.4.12.3.1.1 ECC Result Register and ECC Computation Accumulation Size
              2. 15.4.4.12.3.1.2 ECC Enabling
              3. 15.4.4.12.3.1.3 ECC Computation
              4. 15.4.4.12.3.1.4 ECC Comparison and Correction
              5. 15.4.4.12.3.1.5 ECC Calculation Based on 8-Bit Word
              6. 15.4.4.12.3.1.6 ECC Calculation Based on 16-Bit Word
            2. 15.4.4.12.3.2 BCH Code
              1. 15.4.4.12.3.2.1 Requirements
              2. 15.4.4.12.3.2.2 Memory Mapping of BCH Codeword
                1. 15.4.4.12.3.2.2.1 Memory Mapping of Data Message
                2. 15.4.4.12.3.2.2.2 Memory-Mapping of the ECC
                3. 15.4.4.12.3.2.2.3 Wrapping Modes
                  1. 4.4.12.3.2.2.3.1  Manual Mode (0x0)
                  2. 4.4.12.3.2.2.3.2  Mode 0x1
                  3. 4.4.12.3.2.2.3.3  Mode 0xA (10)
                  4. 4.4.12.3.2.2.3.4  Mode 0x2
                  5. 4.4.12.3.2.2.3.5  Mode 0x3
                  6. 4.4.12.3.2.2.3.6  Mode 0x7
                  7. 4.4.12.3.2.2.3.7  Mode 0x8
                  8. 4.4.12.3.2.2.3.8  Mode 0x4
                  9. 4.4.12.3.2.2.3.9  Mode 0x9
                  10. 4.4.12.3.2.2.3.10 Mode 0x5
                  11. 4.4.12.3.2.2.3.11 Mode 0xB (11)
                  12. 4.4.12.3.2.2.3.12 Mode 0x6
              3. 15.4.4.12.3.2.3 Supported NAND Page Mappings and ECC Schemes
                1. 15.4.4.12.3.2.3.1 Per-Sector Spare Mappings
                2. 15.4.4.12.3.2.3.2 Pooled Spare Mapping
                3. 15.4.4.12.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
          4. 15.4.4.12.4 Prefetch and Write-Posting Engine
            1. 15.4.4.12.4.1 General Facts About the Engine Configuration
            2. 15.4.4.12.4.2 Prefetch Mode
            3. 15.4.4.12.4.3 FIFO Control in Prefetch Mode
            4. 15.4.4.12.4.4 Write-Posting Mode
            5. 15.4.4.12.4.5 FIFO Control in Write-Posting Mode
            6. 15.4.4.12.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
            7. 15.4.4.12.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
      5. 15.4.5 GPMC Basic Programming Model
        1. 15.4.5.1 GPMC High-Level Programming Model Overview
        2. 15.4.5.2 GPMC Initialization
        3. 15.4.5.3 GPMC Configuration in NOR Mode
        4. 15.4.5.4 GPMC Configuration in NAND Mode
        5. 15.4.5.5 Set Memory Access
        6. 15.4.5.6 GPMC Timing Parameters
          1. 15.4.5.6.1 GPMC Timing Parameters Formulas
            1. 15.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
            2. 15.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
            3. 15.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
      6. 15.4.6 GPMC Use Cases and Tips
        1. 15.4.6.1 How to Set GPMC Timing Parameters for Typical Accesses
          1. 15.4.6.1.1 External Memory Attached to the GPMC Module
          2. 15.4.6.1.2 Typical GPMC Setup
            1. 15.4.6.1.2.1 GPMC Configuration for Synchronous Burst Read Access
            2. 15.4.6.1.2.2 GPMC Configuration for Asynchronous Read Access
            3. 15.4.6.1.2.3 GPMC Configuration for Asynchronous Single Write Access
        2. 15.4.6.2 How to Choose a Suitable Memory to Use With the GPMC
          1. 15.4.6.2.1 Supported Memories or Devices
            1. 15.4.6.2.1.1 Memory Pin Multiplexing
            2. 15.4.6.2.1.2 NAND Interface Protocol
            3. 15.4.6.2.1.3 NOR Interface Protocol
            4. 15.4.6.2.1.4 Other Technologies
            5. 15.4.6.2.1.5 Supported Protocols
          2. 15.4.6.2.2 GPMC Features and Settings
      7. 15.4.7 GPMC Register Manual
        1. 15.4.7.1 GPMC Register Summary
        2. 15.4.7.2 GPMC Register Descriptions
    5. 15.5 Error Location Module
      1. 15.5.1 Error Location Module Overview
      2. 15.5.2 ELM Integration
      3. 15.5.3 ELM Functional Description
        1. 15.5.3.1 ELM Software Reset
        2. 15.5.3.2 ELM Power Management
        3. 15.5.3.3 ELM Interrupt Requests
        4. 15.5.3.4 Processing Initialization
        5. 15.5.3.5 Processing Sequence
        6. 15.5.3.6 Processing Completion
      4. 15.5.4 ELM Basic Programming Model
        1. 15.5.4.1 ELM Low-Level Programming Model
          1. 15.5.4.1.1 Processing Initialization
          2. 15.5.4.1.2 Read Results
          3. 15.5.4.1.3 2649
        2. 15.5.4.2 Use Case: ELM Used in Continuous Mode
        3. 15.5.4.3 Use Case: ELM Used in Page Mode
      5. 15.5.5 ELM Register Manual
        1. 15.5.5.1 ELM Instance Summary
        2. 15.5.5.2 ELM Registers
          1. 15.5.5.2.1 ELM Register Summary
          2. 15.5.5.2.2 ELM Register Description
    6. 15.6 On-Chip Memory (OCM) Subsystem
      1. 15.6.1 OCM Subsystem Overview
      2. 15.6.2 OCM Subsystem Integration
      3. 15.6.3 OCM Subsystem Functional Desctiption
        1. 15.6.3.1  Block Diagram
        2. 15.6.3.2  Resets
        3. 15.6.3.3  Clock Management
        4. 15.6.3.4  Interrupt Requests
        5. 15.6.3.5  OCM Subsystem Memory Regions
        6. 15.6.3.6  OCM Controller Modes Of Operation
        7. 15.6.3.7  ECC Associated FIFOs
        8. 15.6.3.8  ECC Counters And Corrected Bit Distribution Register
        9. 15.6.3.9  ECC Support
        10. 15.6.3.10 Circular Buffer (CBUF) Support
        11. 15.6.3.11 CBUF Mode Error Handling
          1. 15.6.3.11.1 VBUF Address Not Mapped to a CBUF Memory Space
          2. 15.6.3.11.2 VBUF Access Not Starting At The Base Address
          3. 15.6.3.11.3 Illegal Address Change Between Two Same Type Accesses
          4. 15.6.3.11.4 Illegal Frame SIze (Short Frame Detection)
          5. 15.6.3.11.5 CBUF Overflow
          6. 15.6.3.11.6 CBUF Underflow
        12. 15.6.3.12 Status Reporting
      4. 15.6.4 OCM Subsystem Register Manual
        1. 15.6.4.1 OCM Subsystem Instance Summary
        2. 15.6.4.2 OCM Subsystem Registers
          1. 15.6.4.2.1 OCM Subsystem Register Summary
          2. 15.6.4.2.2 OCM Subsystem Register Description
  18. 16DMA Controllers
    1. 16.1 System DMA
      1. 16.1.1 DMA_SYSTEM Module Overview
      2. 16.1.2 DMA_SYSTEM Controller Environment
      3. 16.1.3 DMA_SYSTEM Module Integration
        1. 16.1.3.1 DMA Requests to the DMA_SYSTEM Controller
        2. 16.1.3.2 Mapping of DMA Requests to DMA_CROSSBAR Inputs
      4. 16.1.4 DMA_SYSTEM Functional Description
        1. 16.1.4.1  DMA_SYSTEM Controller Power Management
        2. 16.1.4.2  DMA_SYSTEM Controller Interrupt Requests
          1. 16.1.4.2.1 Interrupt Generation
        3. 16.1.4.3  Logical Channel Transfer Overview
        4. 16.1.4.4  FIFO Queue Memory Pool
        5. 16.1.4.5  Addressing Modes
        6. 16.1.4.6  Packed Accesses
        7. 16.1.4.7  Burst Transactions
        8. 16.1.4.8  Endianism Conversion
        9. 16.1.4.9  Transfer Synchronization
          1. 16.1.4.9.1 Software Synchronization
          2. 16.1.4.9.2 Hardware Synchronization
        10. 16.1.4.10 Thread Budget Allocation
        11. 16.1.4.11 FIFO Budget Allocation
        12. 16.1.4.12 Chained Logical Channel Transfers
        13. 16.1.4.13 Reprogramming an Active Channel
        14. 16.1.4.14 Packet Synchronization
        15. 16.1.4.15 Graphics Acceleration Support
        16. 16.1.4.16 Supervisor Modes
        17. 16.1.4.17 Posted and Nonposted Writes
        18. 16.1.4.18 Disabling a Channel During Transfer
        19. 16.1.4.19 FIFO Draining Mechanism
        20. 16.1.4.20 Linked List
          1. 16.1.4.20.1 Overview
          2. 16.1.4.20.2 Link-List Transfer Profile
          3. 16.1.4.20.3 Descriptors
            1. 16.1.4.20.3.1 Type 1
            2. 16.1.4.20.3.2 Type 2
            3. 16.1.4.20.3.3 Type 3
          4. 16.1.4.20.4 Linked-List Control and Monitoring
            1. 16.1.4.20.4.1 Transfer Mode Setting
            2. 16.1.4.20.4.2 Starting a Linked List
            3. 16.1.4.20.4.3 Monitoring a Linked-List Progression
            4. 16.1.4.20.4.4 Interrupt During Linked-List Execution
            5. 16.1.4.20.4.5 Pause a Linked List
            6. 16.1.4.20.4.6 Stop a Linked List (Abort or Drain)
              1. 16.1.4.20.4.6.1 Drain
              2. 16.1.4.20.4.6.2 Abort
            7. 16.1.4.20.4.7 Status Bit Behavior
            8. 16.1.4.20.4.8 Linked-List Channel Linking
      5. 16.1.5 DMA_SYSTEM Basic Programming Model
        1. 16.1.5.1 Setup Configuration
        2. 16.1.5.2 Software-Triggered (Nonsynchronized) Transfer
        3. 16.1.5.3 Hardware-Synchronized Transfer
        4. 16.1.5.4 Synchronized Transfer Monitoring Using CDAC
        5. 16.1.5.5 Concurrent Software and Hardware Synchronization
        6. 16.1.5.6 Chained Transfer
        7. 16.1.5.7 90-Degree Clockwise Image Rotation
        8. 16.1.5.8 Graphic Operations
        9. 16.1.5.9 Linked-List Programming Guidelines
      6. 16.1.6 DMA_SYSTEM Register Manual
        1. 16.1.6.1 DMA_SYSTEM Instance Summary
        2. 16.1.6.2 DMA_SYSTEM Registers
          1. 16.1.6.2.1 DMA_SYSTEM Register Summary
          2. 16.1.6.2.2 DMA_SYSTEM Register Description
    2. 16.2 Enhanced DMA
      1. 16.2.1 EDMA Module Overview
        1. 16.2.1.1 EDMA Features
        2. 16.2.1.2 2750
        3. 16.2.1.3 EDMA Controllers Configuration
      2. 16.2.2 EDMA Controller Environment
      3. 16.2.3 EDMA Controller Integration
        1. 16.2.3.1 EDMA Requests to the EDMA Controller
      4. 16.2.4 EDMA Controller Functional Description
        1. 16.2.4.1  Block Diagram
          1. 16.2.4.1.1 Third-Party Channel Controller
          2. 16.2.4.1.2 Third-Party Transfer Controller
        2. 16.2.4.2  Types of EDMA controller Transfers
          1. 16.2.4.2.1 A-Synchronized Transfers
          2. 16.2.4.2.2 AB-Synchronized Transfers
        3. 16.2.4.3  Parameter RAM (PaRAM)
          1. 16.2.4.3.1 PaRAM
          2. 16.2.4.3.2 EDMA Channel PaRAM Set Entry Fields
            1. 16.2.4.3.2.1  Channel Options Parameter (OPT)
            2. 16.2.4.3.2.2  Channel Source Address (SRC)
            3. 16.2.4.3.2.3  Channel Destination Address (DST)
            4. 16.2.4.3.2.4  Count for 1st Dimension (ACNT)
            5. 16.2.4.3.2.5  Count for 2nd Dimension (BCNT)
            6. 16.2.4.3.2.6  Count for 3rd Dimension (CCNT)
            7. 16.2.4.3.2.7  BCNT Reload (BCNTRLD)
            8. 16.2.4.3.2.8  Source B Index (SBIDX)
            9. 16.2.4.3.2.9  Destination B Index (DBIDX)
            10. 16.2.4.3.2.10 Source C Index (SCIDX)
            11. 16.2.4.3.2.11 Destination C Index (DCIDX)
            12. 16.2.4.3.2.12 Link Address (LINK)
          3. 16.2.4.3.3 Null PaRAM Set
          4. 16.2.4.3.4 Dummy PaRAM Set
          5. 16.2.4.3.5 Dummy Versus Null Transfer Comparison
          6. 16.2.4.3.6 Parameter Set Updates
          7. 16.2.4.3.7 Linking Transfers
          8. 16.2.4.3.8 Constant Addressing Mode Transfers/Alignment Issues
          9. 16.2.4.3.9 Element Size
        4. 16.2.4.4  Initiating a DMA Transfer
          1. 16.2.4.4.1 DMA Channel
            1. 16.2.4.4.1.1 Event-Triggered Transfer Request
            2. 16.2.4.4.1.2 Manually-Triggered Transfer Request
            3. 16.2.4.4.1.3 Chain-Triggered Transfer Request
          2. 16.2.4.4.2 QDMA Channels
            1. 16.2.4.4.2.1 Auto-triggered and Link-Triggered Transfer Request
          3. 16.2.4.4.3 Comparison Between DMA and QDMA Channels
        5. 16.2.4.5  Completion of a DMA Transfer
          1. 16.2.4.5.1 Normal Completion
          2. 16.2.4.5.2 Early Completion
          3. 16.2.4.5.3 Dummy or Null Completion
        6. 16.2.4.6  Event, Channel, and PaRAM Mapping
          1. 16.2.4.6.1 DMA Channel to PaRAM Mapping
          2. 16.2.4.6.2 QDMA Channel to PaRAM Mapping
        7. 16.2.4.7  EDMA Channel Controller Regions
          1. 16.2.4.7.1 Region Overview
          2. 16.2.4.7.2 Channel Controller Regions
            1. 16.2.4.7.2.1 Resource Pool Division Across Two Regions
          3. 16.2.4.7.3 Region Interrupts
        8. 16.2.4.8  Chaining EDMA Channels
        9. 16.2.4.9  EDMA Interrupts
          1. 16.2.4.9.1 Transfer Completion Interrupts
            1. 16.2.4.9.1.1 Enabling Transfer Completion Interrupts
            2. 16.2.4.9.1.2 Clearing Transfer Completion Interrupts
          2. 16.2.4.9.2 EDMA Interrupt Servicing
          3. 16.2.4.9.3 Interrupt Servicing
          4. 16.2.4.9.4 2811
          5. 16.2.4.9.5 Interrupt Servicing
          6. 16.2.4.9.6 Interrupt Evaluation Operations
          7. 16.2.4.9.7 Error Interrupts
          8. 16.2.4.9.8 2815
        10. 16.2.4.10 Memory Protection
          1. 16.2.4.10.1 Active Memory Protection
          2. 16.2.4.10.2 Proxy Memory Protection
        11. 16.2.4.11 Event Queue(s)
          1. 16.2.4.11.1 DMA/QDMA Channel to Event Queue Mapping
          2. 16.2.4.11.2 Queue RAM Debug Visibility
          3. 16.2.4.11.3 Queue Resource Tracking
          4. 16.2.4.11.4 Performance Considerations
        12. 16.2.4.12 EDMA Transfer Controller (EDMA_TPTC)
          1. 16.2.4.12.1 Architecture Details
            1. 16.2.4.12.1.1 Command Fragmentation
            2. 16.2.4.12.1.2 TR Pipelining
            3. 16.2.4.12.1.3 Command Fragmentation (DBS = 64)
            4. 16.2.4.12.1.4 Performance Tuning
          2. 16.2.4.12.2 Memory Protection
          3. 16.2.4.12.3 Error Generation
          4. 16.2.4.12.4 Debug Features
            1. 16.2.4.12.4.1 Destination FIFO Register Pointer
          5. 16.2.4.12.5 EDMA_TPTC Configuration
        13. 16.2.4.13 Event Dataflow
        14. 16.2.4.14 EDMA controller Prioritization
          1. 16.2.4.14.1 Channel Priority
          2. 16.2.4.14.2 Trigger Source Priority
          3. 16.2.4.14.3 Dequeue Priority
        15. 16.2.4.15 EDMA Power, Reset and Clock Management
          1. 16.2.4.15.1 Clock and Power Management
          2. 16.2.4.15.2 Reset Considerations
        16. 16.2.4.16 Emulation Considerations
      5. 16.2.5 EDMA Transfer Examples
        1. 16.2.5.1 Block Move Example
        2. 16.2.5.2 Subframe Extraction Example
        3. 16.2.5.3 Data Sorting Example
        4. 16.2.5.4 Peripheral Servicing Example
          1. 16.2.5.4.1 Non-bursting Peripherals
          2. 16.2.5.4.2 Bursting Peripherals
          3. 16.2.5.4.3 Continuous Operation
            1. 16.2.5.4.3.1 Receive Channel
            2. 16.2.5.4.3.2 Transmit Channel
            3. 16.2.5.4.3.3 2854
          4. 16.2.5.4.4 Ping-Pong Buffering
            1. 16.2.5.4.4.1 Synchronization with the CPU
          5. 16.2.5.4.5 Transfer Chaining Examples
            1. 16.2.5.4.5.1 Servicing Input/Output FIFOs with a Single Event
            2. 16.2.5.4.5.2 Breaking Up Large Transfers with Intermediate Chaining
        5. 16.2.5.5 Setting Up an EDMA Transfer
          1. 16.2.5.5.1 2861
      6. 16.2.6 EDMA Debug Checklist and Programming Tips
        1. 16.2.6.1 EDMA Debug Checklist
        2. 16.2.6.2 EDMA Programming Tips
      7. 16.2.7 EDMA Register Manual
        1. 16.2.7.1 EDMA Instance Summary
        2. 16.2.7.2 EDMA Registers
          1. 16.2.7.2.1 EDMA Register Summary
          2. 16.2.7.2.2 EDMA Register Description
            1. 16.2.7.2.2.1 EDMA_TPCC Register Description
            2. 16.2.7.2.2.2 EDMA_TPTC0 and EDMA_TPTC1 Register Description
  19. 17Interrupt Controllers
    1. 17.1 Interrupt Controllers Overview
    2. 17.2 Interrupt Controllers Environment
    3. 17.3 Interrupt Controllers Integration
      1. 17.3.1 Interrupt Requests to MPU_INTC
      2. 17.3.2 Interrupt Requests to DSP1_INTC
      3. 17.3.3 Interrupt Requests to DSP2_INTC
      4. 17.3.4 Interrupt Requests to IPU1_Cx_INTC
      5. 17.3.5 Interrupt Requests to IPU2_Cx_INTC
      6. 17.3.6 Interrupt Requests to EVE1_INTC1
      7. 17.3.7 Interrupt Requests to EVE2_INTC1
      8. 17.3.8 Mapping of Device Interrupts to IRQ_CROSSBAR Inputs
    4. 17.4 Interrupt Controllers Functional Description
  20. 18Control Module
    1. 18.1 Control Module Overview
    2. 18.2 Control Module Environment
    3. 18.3 Control Module Integration
    4. 18.4 Control Module Functional Description
      1. 18.4.1 Control Module Clock Configuration
      2. 18.4.2 Control Module Resets
      3. 18.4.3 Control Module Power Management
        1. 18.4.3.1 Power Management Protocols
      4. 18.4.4 Hardware Requests
      5. 18.4.5 Control Module Initialization
      6. 18.4.6 Functional Description Of The Various Register Types In CTRL_MODULE_CORE Submodule
        1. 18.4.6.1  Pad Configuration
          1. 18.4.6.1.1 Pad Configuration Registers
            1. 18.4.6.1.1.1 Permanent PU/PD disabling (SR 2.0 only)
          2. 18.4.6.1.2 Pull Selection
          3. 18.4.6.1.3 Pad multiplexing
          4. 18.4.6.1.4 IOSETs
          5. 18.4.6.1.5 Virtual IO Timing Modes
          6. 18.4.6.1.6 Manual IO Timing Modes
          7. 18.4.6.1.7 Isolation Requirements
          8. 18.4.6.1.8 IO Delay Recalibration
        2. 18.4.6.2  Thermal Management Related Registers
          1. 18.4.6.2.1 Temperature Sensors Control Registers
          2. 18.4.6.2.2 Registers For The Thermal Alert Comparators
          3. 18.4.6.2.3 Thermal Shutdown Comparators
          4. 18.4.6.2.4 Temperature Timestamp Registers
          5. 18.4.6.2.5 Other Thermal Management Related Registers
          6. 18.4.6.2.6 Summary of the Thermal Management Related Registers
          7. 18.4.6.2.7 ADC Values Versus Temperature
        3. 18.4.6.3  PBIAS Cell And MMC1 I/O Cells Control Registers
        4. 18.4.6.4  IRQ_CROSSBAR Module Functional Description
        5. 18.4.6.5  DMA_CROSSBAR Module Functional Description
        6. 18.4.6.6  SDRAM Initiator Priority Registers
        7. 18.4.6.7  L3_MAIN Initiator Priority Registers
        8. 18.4.6.8  Memory Region Lock Registers
        9. 18.4.6.9  NMI Mapping To Respective Cores
        10. 18.4.6.10 Software Controls for the DDR2/DDR3 I/O Cells
        11. 18.4.6.11 Reference Voltage for the Device DDR2/DDR3 Receivers
        12. 18.4.6.12 AVS Class 0 Associated Registers
        13. 18.4.6.13 ABB Associated Registers
        14. 18.4.6.14 Registers For Other Miscellaneous Functions
          1. 18.4.6.14.1 System Boot Status Settings
          2. 18.4.6.14.2 Force MPU Write Nonposted Transactions
          3. 18.4.6.14.3 Firewall Error Status Registers
          4. 18.4.6.14.4 Settings Related To Different Peripheral Modules
      7. 18.4.7 Functional Description Of The Various Register Types In CTRL_MODULE_WKUP Submodule
        1. 18.4.7.1 Registers For Basic EMIF Configuration
    5. 18.5 Control Module Register Manual
    6. 18.6 IODELAYCONFIG Module Integration
    7. 18.7 IODELAYCONFIG Module Register Manual
  21. 19Mailbox
    1. 19.1 Mailbox Overview
    2. 19.2 Mailbox Integration
      1. 19.2.1 System MAILBOX Integration
      2. 19.2.2 IVA Mailbox Integration
      3. 19.2.3 EVE Mailbox Integration
    3. 19.3 Mailbox Functional Description
      1. 19.3.1 Mailbox Block Diagram
        1. 19.3.1.1 2944
      2. 19.3.2 Mailbox Software Reset
      3. 19.3.3 Mailbox Power Management
      4. 19.3.4 Mailbox Interrupt Requests
      5. 19.3.5 Mailbox Assignment
        1. 19.3.5.1 Description
      6. 19.3.6 Sending and Receiving Messages
        1. 19.3.6.1 Description
      7. 19.3.7 16-Bit Register Access
        1. 19.3.7.1 Description
      8. 19.3.8 Example of Communication
    4. 19.4 Mailbox Programming Guide
      1. 19.4.1 Mailbox Low-level Programming Models
        1. 19.4.1.1 Global Initialization
          1. 19.4.1.1.1 Surrounding Modules Global Initialization
          2. 19.4.1.1.2 Mailbox Global Initialization
            1. 19.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
        2. 19.4.1.2 Mailbox Operational Modes Configuration
          1. 19.4.1.2.1 Mailbox Processing modes
            1. 19.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
            2. 19.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
            3. 19.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
            4. 19.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
        3. 19.4.1.3 Mailbox Events Servicing
          1. 19.4.1.3.1 Events Servicing in Sending Mode
          2. 19.4.1.3.2 Events Servicing in Receiving Mode
    5. 19.5 Mailbox Register Manual
      1. 19.5.1 Mailbox Instance Summary
      2. 19.5.2 Mailbox Registers
        1. 19.5.2.1 Mailbox Register Summary
        2. 19.5.2.2 Mailbox Register Description
  22. 20Memory Management Units
    1. 20.1 MMU Overview
    2. 20.2 MMU Integration
    3. 20.3 MMU Functional Description
      1. 20.3.1 MMU Block Diagram
        1. 20.3.1.1 MMU Address Translation Process
        2. 20.3.1.2 Translation Tables
          1. 20.3.1.2.1 Translation Table Hierarchy
          2. 20.3.1.2.2 First-Level Translation Table
            1. 20.3.1.2.2.1 First-Level Descriptor Format
            2. 20.3.1.2.2.2 First-Level Page Descriptor Format
            3. 20.3.1.2.2.3 First-Level Section Descriptor Format
            4. 20.3.1.2.2.4 Section Translation Summary
            5. 20.3.1.2.2.5 Supersection Translation Summary
          3. 20.3.1.2.3 Two-Level Translation
            1. 20.3.1.2.3.1 Second-Level Descriptor Format
            2. 20.3.1.2.3.2 Small Page Translation Summary
            3. 20.3.1.2.3.3 Large Page Translation Summary
        3. 20.3.1.3 Translation Lookaside Buffer
          1. 20.3.1.3.1 TLB Entry Format
        4. 20.3.1.4 No Translation (Bypass) Regions
      2. 20.3.2 MMU Software Reset
      3. 20.3.3 MMU Power Management
      4. 20.3.4 MMU Interrupt Requests
      5. 20.3.5 MMU Error Handling
    4. 20.4 MMU Low-level Programming Models
      1. 20.4.1 Global Initialization
        1. 20.4.1.1 Surrounding Modules Global Initialization
        2. 20.4.1.2 MMU Global Initialization
          1. 20.4.1.2.1 Main Sequence - MMU Global Initialization
          2. 20.4.1.2.2 Subsequence - Configure a TLB entry
        3. 20.4.1.3 Operational Modes Configuration
          1. 20.4.1.3.1 Main Sequence - Writing TLB Entries Statically
          2. 20.4.1.3.2 Main Sequence - Protecting TLB Entries
          3. 20.4.1.3.3 Main Sequence - Deleting TLB Entries
          4. 20.4.1.3.4 Main Sequence - Read TLB Entries
    5. 20.5 MMU Register Manual
      1. 20.5.1 MMU Instance Summary
      2. 20.5.2 MMU Registers
        1. 20.5.2.1 MMU Register Summary
        2. 20.5.2.2 MMU Register Description
  23. 21Spinlock
    1. 21.1 Spinlock Overview
    2. 21.2 Spinlock Integration
    3. 21.3 Spinlock Functional Description
      1. 21.3.1 Spinlock Software Reset
      2. 21.3.2 Spinlock Power Management
      3. 21.3.3 About Spinlocks
      4. 21.3.4 Spinlock Functional Operation
    4. 21.4 Spinlock Programming Guide
      1. 21.4.1 Spinlock Low-level Programming Models
        1. 21.4.1.1 Surrounding Modules Global Initialization
        2. 21.4.1.2 Basic Spinlock Operations
          1. 21.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
          2. 21.4.1.2.2 Take and Release Spinlock
    5. 21.5 Spinlock Register Manual
      1. 21.5.1 Spinlock Instance Summary
      2. 21.5.2 Spinlock Registers
        1. 21.5.2.1 Spinlock Register Summary
        2. 21.5.2.2 Spinlock Register Description
  24. 22Timers
    1. 22.1 Timers Overview
    2. 22.2 General-Purpose Timers
      1. 22.2.1 General-Purpose Timers Overview
        1. 22.2.1.1 GP Timer Features
      2. 22.2.2 GP Timer Environment
        1. 22.2.2.1 GP Timer External System Interface
      3. 22.2.3 GP Timer Integration
      4. 22.2.4 GP Timer Functional Description
        1. 22.2.4.1  GP Timer Block Diagram
        2. 22.2.4.2  TIMER1, TIMER2 and TIMER10 Power Management
          1. 22.2.4.2.1 Wake-Up Capability
        3. 22.2.4.3  Power Management of Other GP Timers
          1. 22.2.4.3.1 Wake-Up Capability
        4. 22.2.4.4  Software Reset
        5. 22.2.4.5  GP Timer Interrupts
        6. 22.2.4.6  Timer Mode Functionality
          1. 22.2.4.6.1 1-ms Tick Generation (Only TIMER1, TIMER2 and TIMER10)
        7. 22.2.4.7  Capture Mode Functionality
        8. 22.2.4.8  Compare Mode Functionality
        9. 22.2.4.9  Prescaler Functionality
        10. 22.2.4.10 Pulse-Width Modulation
        11. 22.2.4.11 Timer Counting Rate
        12. 22.2.4.12 Timer Under Emulation
        13. 22.2.4.13 Accessing GP Timer Registers
          1. 22.2.4.13.1 Writing to Timer Registers
            1. 22.2.4.13.1.1 Write Posting Synchronization Mode
            2. 22.2.4.13.1.2 Write Nonposting Synchronization Mode
          2. 22.2.4.13.2 Reading From Timer Counter Registers
            1. 22.2.4.13.2.1 Read Posted
            2. 22.2.4.13.2.2 Read Non-Posted
        14. 22.2.4.14 Posted Mode Selection
      5. 22.2.5 GP Timer Low-Level Programming Models
        1. 22.2.5.1 Global Initialization
          1. 22.2.5.1.1 Global Initialization of Surrounding Modules
          2. 22.2.5.1.2 GP Timer Module Global Initialization
            1. 22.2.5.1.2.1 Main Sequence – GP Timer Module Global Initialization
        2. 22.2.5.2 Operational Mode Configuration
          1. 22.2.5.2.1 GP Timer Mode
            1. 22.2.5.2.1.1 Main Sequence – GP Timer Mode Configuration
          2. 22.2.5.2.2 GP Timer Compare Mode
            1. 22.2.5.2.2.1 Main Sequence – GP Timer Compare Mode Configuration
          3. 22.2.5.2.3 GP Timer Capture Mode
            1. 22.2.5.2.3.1 Main Sequence – GP Timer Capture Mode Configuration
            2. 22.2.5.2.3.2 Subsequence – Initialize Capture Mode
            3. 22.2.5.2.3.3 Subsequence – Detect Event
          4. 22.2.5.2.4 GP Timer PWM Mode
            1. 22.2.5.2.4.1 Main Sequence – GP Timer PWM Mode Configuration
      6. 22.2.6 GP Timer Register Manual
        1. 22.2.6.1 GP Timer Instance Summary
        2. 22.2.6.2 GP Timer Registers
          1. 22.2.6.2.1 GP Timer Register Summary
          2. 22.2.6.2.2 GP Timer Register Description
          3. 22.2.6.2.3 TIMER1, TIMER2, and TIMER10 Register Description
    3. 22.3 32-kHz Synchronized Timer (COUNTER_32K)
      1. 22.3.1 32-kHz Synchronized Timer Overview
        1. 22.3.1.1 32-kHz Synchronized Timer Features
      2. 22.3.2 32-kHz Synchronized Timer Integration
      3. 22.3.3 32-kHz Synchronized Timer Functional Description
        1. 22.3.3.1 Reading the 32-kHz Synchronized Timer
      4. 22.3.4 COUNTER_32K Timer Register Manual
        1. 22.3.4.1 COUNTER_32K Timer Register Mapping Summary
        2. 22.3.4.2 COUNTER_32K Timer Register Description
    4. 22.4 Watchdog Timer
      1. 22.4.1 Watchdog Timer Overview
        1. 22.4.1.1 Watchdog Timer Features
      2. 22.4.2 Watchdog Timer Integration
      3. 22.4.3 Watchdog Timer Functional Description
        1. 22.4.3.1  Power Management
          1. 22.4.3.1.1 Wake-Up Capability
        2. 22.4.3.2  Interrupts
        3. 22.4.3.3  General Watchdog Timer Operation
        4. 22.4.3.4  Reset Context
        5. 22.4.3.5  Overflow/Reset Generation
        6. 22.4.3.6  Prescaler Value/Timer Reset Frequency
        7. 22.4.3.7  Triggering a Timer Reload
        8. 22.4.3.8  Start/Stop Sequence for Watchdog Timer (Using the WSPR Register)
        9. 22.4.3.9  Modifying Timer Count/Load Values and Prescaler Setting
        10. 22.4.3.10 Watchdog Counter Register Access Restriction (WCRR)
        11. 22.4.3.11 Watchdog Timer Interrupt Generation
        12. 22.4.3.12 Watchdog Timer Under Emulation
        13. 22.4.3.13 Accessing Watchdog Timer Registers
      4. 22.4.4 Watchdog Timer Low-Level Programming Model
        1. 22.4.4.1 Global Initialization
          1. 22.4.4.1.1 Surrounding Modules Global Initialization
          2. 22.4.4.1.2 Watchdog Timer Module Global Initialization
            1. 22.4.4.1.2.1 Main Sequence – Watchdog Timer Module Global Initialization
        2. 22.4.4.2 Operational Mode Configuration
          1. 22.4.4.2.1 Watchdog Timer Basic Configuration
            1. 22.4.4.2.1.1 Main Sequence – Watchdog Timer Basic Configuration
            2. 22.4.4.2.1.2 Subsequence – Disable the Watchdog Timer
            3. 22.4.4.2.1.3 Subsequence – Enable the Watchdog Timer
      5. 22.4.5 Watchdog Timer Register Manual
        1. 22.4.5.1 Watchdog Timer Instance Summary
        2. 22.4.5.2 Watchdog Timer Registers
          1. 22.4.5.2.1 Watchdog Timer Register Summary
          2. 22.4.5.2.2 3131
          3. 22.4.5.2.3 Watchdog Timer Register Description
  25. 23Real-Time Clock (RTC)
    1. 23.1 RTC Overview
      1. 23.1.1 RTC Features
    2. 23.2 RTC Environment
      1. 23.2.1 RTC External Interface
    3. 23.3 RTC Integration
    4. 23.4 RTC Functional Description
      1. 23.4.1 Clock Source
      2. 23.4.2 Interrupt Support
        1. 23.4.2.1 CPU Interrupts
        2. 23.4.2.2 Interrupt Description
          1. 23.4.2.2.1 Timer Interrupt (timer_intr)
          2. 23.4.2.2.2 Alarm Interrupt (alarm_intr)
      3. 23.4.3 RTC Programming/Usage Guide
        1. 23.4.3.1 Time/Calendar Data Format
        2. 23.4.3.2 Register Access
        3. 23.4.3.3 Register Spurious Write Protection
        4. 23.4.3.4 Reading the Timer/Calendar (TC) Registers
          1. 23.4.3.4.1 Rounding Seconds
        5. 23.4.3.5 Modifying the TC Registers
          1. 23.4.3.5.1 General Registers
        6. 23.4.3.6 Crystal Compensation
      4. 23.4.4 Scratch Registers
      5. 23.4.5 Debouncing
      6. 23.4.6 Power Management
        1. 23.4.6.1 Device-Level Power Management
        2. 23.4.6.2 Subsystem-Level Power Management — PMIC Mode
    5. 23.5 RTC Low-Level Programming Guide
      1. 23.5.1 Global Initialization
        1. 23.5.1.1 Surrounding Modules Global Initialization
        2. 23.5.1.2 RTC Module Global Initialization
          1. 23.5.1.2.1 Main Sequence – RTC Module Global Initialization
    6. 23.6 RTC Register Manual
      1. 23.6.1 RTC Instance Summary
      2. 23.6.2 RTC_SS Registers
        1. 23.6.2.1 RTC_SS Register Summary
        2. 23.6.2.2 RTC_SS Register Description
  26. 24Serial Communication Interfaces
    1. 24.1  Multimaster High-Speed I2C Controller
      1. 24.1.1 HS I2C Overview
      2. 24.1.2 HS I2C Environment
        1. 24.1.2.1 HS I2C Typical Application
          1. 24.1.2.1.1 HS I2C Pins for Typical Connections in I2C Mode
          2. 24.1.2.1.2 HS I2C Interface Typical Connections
        2. 24.1.2.2 HS I2C Typical Connection Protocol and Data Format
          1. 24.1.2.2.1  HS I2C Serial Data Format
          2. 24.1.2.2.2  HS I2C Data Validity
          3. 24.1.2.2.3  HS I2C Start and Stop Conditions
          4. 24.1.2.2.4  HS I2C Addressing
            1. 24.1.2.2.4.1 Data Transfer Formats in F/S Mode
            2. 24.1.2.2.4.2 Data Transfer Format in HS Mode
          5. 24.1.2.2.5  HS I2C Master Transmitter
          6. 24.1.2.2.6  HS I2C Master Receiver
          7. 24.1.2.2.7  HS I2C Slave Transmitter
          8. 24.1.2.2.8  HS I2C Slave Receiver
          9. 24.1.2.2.9  HS I2C Bus Arbitration
          10. 24.1.2.2.10 HS I2C Clock Generation and Synchronization
      3. 24.1.3 HS I2C Integration
      4. 24.1.4 HS I2C Functional Description
        1. 24.1.4.1  HS I2C Block Diagram
        2. 24.1.4.2  HS I2C Clocks
          1. 24.1.4.2.1 HS I2C Clocking
          2. 24.1.4.2.2 HS I2C Automatic Blocking of the I2C Clock Feature
        3. 24.1.4.3  HS I2C Software Reset
        4. 24.1.4.4  HS I2C Power Management
        5. 24.1.4.5  HS I2C Interrupt Requests
        6. 24.1.4.6  HS I2C DMA Requests
        7. 24.1.4.7  HS I2C Programmable Multislave Channel Feature
        8. 24.1.4.8  HS I2C FIFO Management
          1. 24.1.4.8.1 HS I2C FIFO Interrupt Mode
          2. 24.1.4.8.2 HS I2C FIFO Polling Mode
          3. 24.1.4.8.3 HS I2C FIFO DMA Mode
          4. 24.1.4.8.4 HS I2C Draining Feature
        9. 24.1.4.9  HS I2C Noise Filter
        10. 24.1.4.10 HS I2C System Test Mode
      5. 24.1.5 HS I2C Programming Guide
        1. 24.1.5.1 HS I2C Low-Level Programming Models
          1. 24.1.5.1.1 HS I2C Programming Model
            1. 24.1.5.1.1.1 Main Program
              1. 24.1.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
              2. 24.1.5.1.1.1.2 Initialize the I2C Controller
              3. 24.1.5.1.1.1.3 Configure Slave Address and the Data Control Register
              4. 24.1.5.1.1.1.4 Initiate a Transfer
              5. 24.1.5.1.1.1.5 Receive Data
              6. 24.1.5.1.1.1.6 Transmit Data
            2. 24.1.5.1.1.2 Interrupt Subroutine Sequence
            3. 24.1.5.1.1.3 Programming Flow-Diagrams
      6. 24.1.6 HS I2C Register Manual
        1. 24.1.6.1 HS I2C Instance Summary
        2. 24.1.6.2 HS I2C Registers
          1. 24.1.6.2.1 HS I2C Register Summary
          2. 24.1.6.2.2 HS I2C Register Description
    2. 24.2  HDQ/1-Wire
      1. 24.2.1 HDQ1W Overview
      2. 24.2.2 HDQ1W Environment
        1. 24.2.2.1 HDQ1W Functional Modes
        2. 24.2.2.2 HDQ and 1-Wire (SDQ) Protocols
          1. 24.2.2.2.1 HDQ Protocol Initialization (Default)
          2. 24.2.2.2.2 1-Wire (SDQ) Protocol Initialization
          3. 24.2.2.2.3 Communication Sequence (HDQ and 1-Wire Protocols)
      3. 24.2.3 HDQ1W Integration
      4. 24.2.4 HDQ1W Functional Description
        1. 24.2.4.1 HDQ1W Block Diagram
        2. 24.2.4.2 HDQ1W Clocking Configuration
          1. 24.2.4.2.1 HDQ1W Clocks
        3. 24.2.4.3 HDQ1W Hardware and Software Reset
        4. 24.2.4.4 HDQ1W Power Management
          1. 24.2.4.4.1 Auto-Idle Mode
          2. 24.2.4.4.2 Power-Down Mode
          3. 24.2.4.4.3 3242
        5. 24.2.4.5 HDQ Interrupt Requests
        6. 24.2.4.6 HDQ Mode (Default)
          1. 24.2.4.6.1 HDQ Mode Features
          2. 24.2.4.6.2 Description
          3. 24.2.4.6.3 Single-Bit Mode
          4. 24.2.4.6.4 Interrupt Conditions
        7. 24.2.4.7 1-Wire Mode
          1. 24.2.4.7.1 1-Wire Mode Features
          2. 24.2.4.7.2 Description
          3. 24.2.4.7.3 1-Wire Single-Bit Mode Operation
          4. 24.2.4.7.4 Interrupt Conditions
          5. 24.2.4.7.5 Status Flags
        8. 24.2.4.8 BITFSM Delay
      5. 24.2.5 HDQ1W Low-Level Programming Model
        1. 24.2.5.1 Global Initialization
          1. 24.2.5.1.1 Surrounding Modules Global Initialization
          2. 24.2.5.1.2 HDQ1W Module Global Initialization
        2. 24.2.5.2 HDQ Operational Modes Configuration
          1. 24.2.5.2.1 Main Sequence - HDQ Write Operation Mode
          2. 24.2.5.2.2 Main Sequence - HDQ Read Operation Mode
            1. 24.2.5.2.2.1 Sub-sequence - Initialize HDQ Slave
        3. 24.2.5.3 1-Wire Operational Modes Configuration
          1. 24.2.5.3.1 Main Sequence - 1-Wire Write Operation Mode
          2. 24.2.5.3.2 Main Sequence - 1-Wire Read Operation Mode
          3. 24.2.5.3.3 Sub-sequence - Initialize 1-Wire Slave
      6. 24.2.6 HDQ1W Register Manual
        1. 24.2.6.1 HDQ1W Instance Summary
        2. 24.2.6.2 HDQ1W Registers
          1. 24.2.6.2.1 HDQ1W Register Summary
          2. 24.2.6.2.2 HDQ1W Register Description
    3. 24.3  UART/IrDA/CIR
      1. 24.3.1 UART/IrDA/CIR Overview
        1. 24.3.1.1 UART Features
        2. 24.3.1.2 IrDA Features
        3. 24.3.1.3 CIR Features
      2. 24.3.2 UART/IrDA/CIR Environment
        1. 24.3.2.1 UART Interface
          1. 24.3.2.1.1 System Using UART Communication With Hardware Handshake
          2. 24.3.2.1.2 UART Interface Description
          3. 24.3.2.1.3 UART Protocol and Data Format
        2. 24.3.2.2 IrDA Functional Interfaces
          1. 24.3.2.2.1 System Using IrDA Communication Protocol
          2. 24.3.2.2.2 IrDA Interface Description
          3. 24.3.2.2.3 IrDA Protocol and Data Format
            1. 24.3.2.2.3.1 SIR Mode
              1. 24.3.2.2.3.1.1 Frame Format
              2. 24.3.2.2.3.1.2 Asynchronous Transparency
              3. 24.3.2.2.3.1.3 Abort Sequence
              4. 24.3.2.2.3.1.4 Pulse Shaping
              5. 24.3.2.2.3.1.5 Encoder
              6. 24.3.2.2.3.1.6 Decoder
              7. 24.3.2.2.3.1.7 IR Address Checking
            2. 24.3.2.2.3.2 SIR Free-Format Mode
            3. 24.3.2.2.3.3 MIR Mode
              1. 24.3.2.2.3.3.1 MIR Encoder/Decoder
              2. 24.3.2.2.3.3.2 SIP Generation
            4. 24.3.2.2.3.4 FIR Mode
        3. 24.3.2.3 CIR Functional Interfaces
          1. 24.3.2.3.1 System Using CIR Communication Protocol With Remote Control
          2. 24.3.2.3.2 CIR Interface Description
          3. 24.3.2.3.3 CIR Protocol and Data Format
            1. 24.3.2.3.3.1 Carrier Modulation
            2. 24.3.2.3.3.2 Pulse Duty Cycle
            3. 24.3.2.3.3.3 Consumer IR Encoding/Decoding
      3. 24.3.3 UART/IrDA/CIR Integration
        1. 24.3.3.1 3308
      4. 24.3.4 UART/IrDA/CIR Functional Description
        1. 24.3.4.1 Block Diagram
        2. 24.3.4.2 Clock Configuration
        3. 24.3.4.3 Software Reset
        4. 24.3.4.4 Power Management
          1. 24.3.4.4.1 UART Mode Power Management
            1. 24.3.4.4.1.1 Module Power Saving
            2. 24.3.4.4.1.2 System Power Saving
          2. 24.3.4.4.2 IrDA Mode Power Management (UART3 Only)
            1. 24.3.4.4.2.1 Module Power Saving
            2. 24.3.4.4.2.2 System Power Saving
          3. 24.3.4.4.3 CIR Mode Power Management (UART3 Only)
            1. 24.3.4.4.3.1 Module Power Saving
            2. 24.3.4.4.3.2 System Power Saving
          4. 24.3.4.4.4 Local Power Management
        5. 24.3.4.5 Interrupt Requests
          1. 24.3.4.5.1 UART Mode Interrupt Management
            1. 24.3.4.5.1.1 UART Interrupts
            2. 24.3.4.5.1.2 Wake-Up Interrupt
          2. 24.3.4.5.2 IrDA Mode Interrupt Management
            1. 24.3.4.5.2.1 IrDA Interrupts
            2. 24.3.4.5.2.2 Wake-Up Interrupts
          3. 24.3.4.5.3 CIR Mode Interrupt Management
            1. 24.3.4.5.3.1 CIR Interrupts
            2. 24.3.4.5.3.2 Wake-Up Interrupts
        6. 24.3.4.6 FIFO Management
          1. 24.3.4.6.1 FIFO Trigger
            1. 24.3.4.6.1.1 Transmit FIFO Trigger
            2. 24.3.4.6.1.2 Receive FIFO Trigger
          2. 24.3.4.6.2 FIFO Interrupt Mode
          3. 24.3.4.6.3 FIFO Polled Mode Operation
          4. 24.3.4.6.4 FIFO DMA Mode Operation
            1. 24.3.4.6.4.1 DMA sequence to disable TX DMA
            2. 24.3.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
            3. 24.3.4.6.4.3 DMA Transmission
            4. 24.3.4.6.4.4 DMA Reception
        7. 24.3.4.7 Mode Selection
          1. 24.3.4.7.1 Register Access Modes
            1. 24.3.4.7.1.1 Operational Mode and Configuration Modes
            2. 24.3.4.7.1.2 Register Access Submode
            3. 24.3.4.7.1.3 Registers Available for the Register Access Modes
          2. 24.3.4.7.2 UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
            1. 24.3.4.7.2.1 Registers Available for the UART Function
            2. 24.3.4.7.2.2 Registers Available for the IrDA Function (UART3 Only)
            3. 24.3.4.7.2.3 Registers Available for the CIR Function (UART3 Only)
        8. 24.3.4.8 Protocol Formatting
          1. 24.3.4.8.1 UART Mode
            1. 24.3.4.8.1.1 UART Clock Generation: Baud Rate Generation
            2. 24.3.4.8.1.2 Choosing the Appropriate Divisor Value
            3. 24.3.4.8.1.3 UART Data Formatting
              1. 24.3.4.8.1.3.1 Frame Formatting
              2. 24.3.4.8.1.3.2 Hardware Flow Control
              3. 24.3.4.8.1.3.3 Software Flow Control
                1. 24.3.4.8.1.3.3.1 Receive (RX)
                2. 24.3.4.8.1.3.3.2 Transmit (TX)
              4. 24.3.4.8.1.3.4 Autobauding Modes
              5. 24.3.4.8.1.3.5 Error Detection
              6. 24.3.4.8.1.3.6 Overrun During Receive
              7. 24.3.4.8.1.3.7 Time-Out and Break Conditions
                1. 24.3.4.8.1.3.7.1 Time-Out Counter
                2. 24.3.4.8.1.3.7.2 Break Condition
          2. 24.3.4.8.2 IrDA Mode (UART3 Only)
            1. 24.3.4.8.2.1 IrDA Clock Generation: Baud Generator
            2. 24.3.4.8.2.2 Choosing the Appropriate Divisor Value
            3. 24.3.4.8.2.3 IrDA Data Formatting
              1. 24.3.4.8.2.3.1 IR RX Polarity Control
              2. 24.3.4.8.2.3.2 IrDA Reception Control
              3. 24.3.4.8.2.3.3 IR Address Checking
              4. 24.3.4.8.2.3.4 Frame Closing
              5. 24.3.4.8.2.3.5 Store and Controlled Transmission
              6. 24.3.4.8.2.3.6 Error Detection
              7. 24.3.4.8.2.3.7 Underrun During Transmission
              8. 24.3.4.8.2.3.8 Overrun During Receive
              9. 24.3.4.8.2.3.9 Status FIFO
            4. 24.3.4.8.2.4 SIR Mode Data Formatting
              1. 24.3.4.8.2.4.1 Abort Sequence
              2. 24.3.4.8.2.4.2 Pulse Shaping
              3. 24.3.4.8.2.4.3 SIR Free Format Programming
            5. 24.3.4.8.2.5 MIR and FIR Mode Data Formatting
          3. 24.3.4.8.3 CIR Mode (UART3 Only)
            1. 24.3.4.8.3.1 CIR Mode Clock Generation
            2. 24.3.4.8.3.2 CIR Data Formatting
              1. 24.3.4.8.3.2.1 IR RX Polarity Control
              2. 24.3.4.8.3.2.2 CIR Transmission
      5. 24.3.5 UART/IrDA/CIR Basic Programming Model
        1. 24.3.5.1 Global Initialization
          1. 24.3.5.1.1 Surrounding Modules Global Initialization
          2. 24.3.5.1.2 UART/IrDA/CIR Module Global Initialization
        2. 24.3.5.2 Mode selection
        3. 24.3.5.3 Submode selection
        4. 24.3.5.4 Load FIFO trigger and DMA mode settings
          1. 24.3.5.4.1 DMA mode Settings
          2. 24.3.5.4.2 FIFO Trigger Settings
        5. 24.3.5.5 Protocol, Baud rate and interrupt settings
          1. 24.3.5.5.1 Baud rate settings
          2. 24.3.5.5.2 Interrupt settings
          3. 24.3.5.5.3 Protocol settings
          4. 24.3.5.5.4 UART/IrDA(SIR/MIR/FIR)/CIR
        6. 24.3.5.6 Hardware and Software Flow Control Configuration
          1. 24.3.5.6.1 Hardware Flow Control Configuration
          2. 24.3.5.6.2 Software Flow Control Configuration
        7. 24.3.5.7 IrDA Programming Model (UART3 Only)
          1. 24.3.5.7.1 SIR mode
            1. 24.3.5.7.1.1 Receive
            2. 24.3.5.7.1.2 Transmit
          2. 24.3.5.7.2 MIR mode
            1. 24.3.5.7.2.1 Receive
            2. 24.3.5.7.2.2 Transmit
          3. 24.3.5.7.3 FIR mode
            1. 24.3.5.7.3.1 Receive
            2. 24.3.5.7.3.2 Transmit
      6. 24.3.6 UART/IrDA/CIR Register Manual
        1. 24.3.6.1 UART/IrDA/CIR Instance Summary
        2. 24.3.6.2 UART/IrDA/CIR Registers
          1. 24.3.6.2.1 UART/IrDA/CIR Register Summary
          2. 24.3.6.2.2 UART/IrDA/CIR Register Description
    4. 24.4  Multichannel Serial Peripheral Interface
      1. 24.4.1 McSPI Overview
      2. 24.4.2 McSPI Environment
        1. 24.4.2.1 Basic McSPI Pins for Master Mode
        2. 24.4.2.2 Basic McSPI Pins for Slave Mode
        3. 24.4.2.3 Multichannel SPI Protocol and Data Format
          1. 24.4.2.3.1 Transfer Format
        4. 24.4.2.4 SPI in Master Mode
        5. 24.4.2.5 SPI in Slave Mode
      3. 24.4.3 McSPI Integration
      4. 24.4.4 McSPI Functional Description
        1. 24.4.4.1 McSPI Block Diagram
        2. 24.4.4.2 Reset
        3. 24.4.4.3 Master Mode
          1. 24.4.4.3.1 Master Mode Features
          2. 24.4.4.3.2 Master Transmit-and-Receive Mode (Full Duplex)
          3. 24.4.4.3.3 Master Transmit-Only Mode (Half Duplex)
          4. 24.4.4.3.4 Master Receive-Only Mode (Half Duplex)
          5. 24.4.4.3.5 Single-Channel Master Mode
            1. 24.4.4.3.5.1 Programming Tips When Switching to Another Channel
            2. 24.4.4.3.5.2 Force SPIEN[x] Mode
            3. 24.4.4.3.5.3 Turbo Mode
          6. 24.4.4.3.6 Start-Bit Mode
          7. 24.4.4.3.7 Chip-Select Timing Control
          8. 24.4.4.3.8 Programmable SPI Clock
            1. 24.4.4.3.8.1 Clock Ratio Granularity
        4. 24.4.4.4 Slave Mode
          1. 24.4.4.4.1 Dedicated Resources
          2. 24.4.4.4.2 Slave Transmit-and-Receive Mode
          3. 24.4.4.4.3 Slave Transmit-Only Mode
          4. 24.4.4.4.4 Slave Receive-Only Mode
        5. 24.4.4.5 3-Pin or 4-Pin Mode
        6. 24.4.4.6 FIFO Buffer Management
          1. 24.4.4.6.1 Buffer Almost Full
          2. 24.4.4.6.2 Buffer Almost Empty
          3. 24.4.4.6.3 End of Transfer Management
        7. 24.4.4.7 Interrupts
          1. 24.4.4.7.1 Interrupt Events in Master Mode
            1. 24.4.4.7.1.1 TXx_EMPTY
            2. 24.4.4.7.1.2 TXx_UNDERFLOW
            3. 24.4.4.7.1.3 RXx_ FULL
            4. 24.4.4.7.1.4 End Of Word Count
          2. 24.4.4.7.2 Interrupt Events in Slave Mode
            1. 24.4.4.7.2.1 TXx_EMPTY
            2. 24.4.4.7.2.2 TXx_UNDERFLOW
            3. 24.4.4.7.2.3 RXx_FULL
            4. 24.4.4.7.2.4 RX0_OVERFLOW
            5. 24.4.4.7.2.5 End Of Word Count
          3. 24.4.4.7.3 Interrupt-Driven Operation
          4. 24.4.4.7.4 Polling
        8. 24.4.4.8 DMA Requests
        9. 24.4.4.9 Power Saving Management
          1. 24.4.4.9.1 Normal Mode
          2. 24.4.4.9.2 Idle Mode
            1. 24.4.4.9.2.1 Wake-Up Event in Smart-Idle Mode
            2. 24.4.4.9.2.2 Transitions From Smart-Idle Mode to Normal Mode
            3. 24.4.4.9.2.3 Force-Idle Mode
      5. 24.4.5 McSPI Programming Guide
        1. 24.4.5.1 Global Initialization
          1. 24.4.5.1.1 Surrounding Modules Global Initialization
          2. 24.4.5.1.2 McSPI Global Initialization
            1. 24.4.5.1.2.1 Main Sequence – McSPI Global Initialization
        2. 24.4.5.2 Operational Mode Configuration
          1. 24.4.5.2.1 McSPI Operational Modes
            1. 24.4.5.2.1.1 Common Transfer Sequence
            2. 24.4.5.2.1.2 End of Transfer Sequences
            3. 24.4.5.2.1.3 Transmit-and-Receive (Master and Slave)
            4. 24.4.5.2.1.4 Transmit-Only (Master and Slave)
              1. 24.4.5.2.1.4.1 Based on Interrupt Requests
              2. 24.4.5.2.1.4.2 Based on DMA Write Requests
            5. 24.4.5.2.1.5 Master Normal Receive-Only
              1. 24.4.5.2.1.5.1 Based on Interrupt Requests
              2. 24.4.5.2.1.5.2 Based on DMA Read Requests
            6. 24.4.5.2.1.6 Master Turbo Receive-Only
              1. 24.4.5.2.1.6.1 Based on Interrupt Requests
              2. 24.4.5.2.1.6.2 Based on DMA Read Requests
            7. 24.4.5.2.1.7 Slave Receive-Only
            8. 24.4.5.2.1.8 Transfer Procedures With FIFO
              1. 24.4.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
              2. 24.4.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
              3. 24.4.5.2.1.8.3 Transmit-and-Receive With Word Count
              4. 24.4.5.2.1.8.4 Transmit-and-Receive Without Word Count
              5. 24.4.5.2.1.8.5 Transmit-Only
              6. 24.4.5.2.1.8.6 Receive-Only With Word Count
              7. 24.4.5.2.1.8.7 Receive-Only Without Word Count
        3. 24.4.5.3 Common Transfer Procedures Without FIFO – Polling Method
          1. 24.4.5.3.1 Receive-Only Procedure – Polling Method
          2. 24.4.5.3.2 Receive-Only Procedure – Interrupt Method
          3. 24.4.5.3.3 Transmit-Only Procedure – Polling Method
          4. 24.4.5.3.4 Transmit-and-Receive Procedure – Polling Method
      6. 24.4.6 McSPI Register Manual
        1. 24.4.6.1 McSPI Instance Summary
        2. 24.4.6.2 McSPI Registers
          1. 24.4.6.2.1 McSPI Register Summary
          2. 24.4.6.2.2 McSPI Register Description
    5. 24.5  Quad Serial Peripheral Interface
      1. 24.5.1 Quad Serial Peripheral Interface Overview
      2. 24.5.2 QSPI Environment
      3. 24.5.3 QSPI Integration
      4. 24.5.4 QSPI Functional Description
        1. 24.5.4.1 QSPI Block Diagram
          1. 24.5.4.1.1 SFI Register Control
          2. 24.5.4.1.2 SFI Translator
          3. 24.5.4.1.3 SPI Control Interface
          4. 24.5.4.1.4 SPI Clock Generator
          5. 24.5.4.1.5 SPI Control State-Machine
          6. 24.5.4.1.6 SPI Data Shifter
        2. 24.5.4.2 QSPI Clock Configuration
        3. 24.5.4.3 QSPI Interrupt Requests
        4. 24.5.4.4 QSPI Memory Regions
      5. 24.5.5 QSPI Register Manual
        1. 24.5.5.1 QSPI Instance Summary
        2. 24.5.5.2 QSPI registers
          1. 24.5.5.2.1 QSPI Register Summary
          2. 24.5.5.2.2 QSPI Register Description
    6. 24.6  Multichannel Audio Serial Port
      1. 24.6.1 McASP Overview
      2. 24.6.2 McASP Environment
        1. 24.6.2.1 McASP Signals
        2. 24.6.2.2 Protocols and Data Formats
          1. 24.6.2.2.1 Protocols Supported
          2. 24.6.2.2.2 Definition of Terms
          3. 24.6.2.2.3 TDM Format
          4. 24.6.2.2.4 I2S Format
          5. 24.6.2.2.5 S/PDIF Coding Format
            1. 24.6.2.2.5.1 Biphase-Mark Code
            2. 24.6.2.2.5.2 S/PDIF Subframe Format
            3. 24.6.2.2.5.3 Frame Format
      3. 24.6.3 McASP Integration
      4. 24.6.4 McASP Functional Description
        1. 24.6.4.1  McASP Block Diagram
        2. 24.6.4.2  McASP Clock and Frame-Sync Configurations
          1. 24.6.4.2.1 McASP Transmit Clock
          2. 24.6.4.2.2 McASP Receive Clock
          3. 24.6.4.2.3 Frame-Sync Generator
          4. 24.6.4.2.4 Synchronous and Asynchronous Transmit and Receive Operations
        3. 24.6.4.3  Serializers
        4. 24.6.4.4  Format Units
          1. 24.6.4.4.1 Transmit Format Unit
            1. 24.6.4.4.1.1 TDM Mode Transmission Data Alignment Settings
            2. 24.6.4.4.1.2 DIT Mode Transmission Data Alignment Settings
          2. 24.6.4.4.2 Receive Format Unit
            1. 24.6.4.4.2.1 TDM Mode Reception Data Alignment Settings
        5. 24.6.4.5  State-Machines
        6. 24.6.4.6  TDM Sequencers
        7. 24.6.4.7  McASP Software Reset
        8. 24.6.4.8  McASP Power Management
        9. 24.6.4.9  Transfer Modes
          1. 24.6.4.9.1 Burst Transfer Mode
          2. 24.6.4.9.2 Time-Division Multiplexed (TDM) Transfer Mode
            1. 24.6.4.9.2.1 TDM Time Slots Generation and Processing
            2. 24.6.4.9.2.2 Special 384-Slot TDM Mode for Connection to External DIR
          3. 24.6.4.9.3 DIT Transfer Mode
            1. 24.6.4.9.3.1 Transmit DIT Encoding
            2. 24.6.4.9.3.2 Transmit DIT Clock and Frame-Sync Generation
            3. 24.6.4.9.3.3 DIT Channel Status and User Data Register Files
        10. 24.6.4.10 Data Transmission and Reception
          1. 24.6.4.10.1 Data Ready Status and Event/Interrupt Generation
            1. 24.6.4.10.1.1 Transmit Data Ready
            2. 24.6.4.10.1.2 Receive Data Ready
            3. 24.6.4.10.1.3 Transfers Through the Data Port (DATA)
            4. 24.6.4.10.1.4 Transfers Through the Configuration Bus (CFG)
            5. 24.6.4.10.1.5 Using a Device CPU for McASP Servicing
            6. 24.6.4.10.1.6 Using the DMA for McASP Servicing
        11. 24.6.4.11 McASP Audio FIFO (AFIFO)
          1. 24.6.4.11.1 AFIFO Data Transmission
            1. 24.6.4.11.1.1 Transmit DMA Event Pacer
          2. 24.6.4.11.2 AFIFO Data Reception
            1. 24.6.4.11.2.1 Receive DMA Event Pacer
          3. 24.6.4.11.3 Arbitration Between Transmit and Receive DMA Requests
        12. 24.6.4.12 McASP Events and Interrupt Requests
          1. 24.6.4.12.1 Transmit Data Ready Event and Interrupt
          2. 24.6.4.12.2 Receive Data Ready Event and Interrupt
          3. 24.6.4.12.3 Error Interrupt
          4. 24.6.4.12.4 Multiple Interrupts
        13. 24.6.4.13 DMA Requests
        14. 24.6.4.14 Loopback Modes
          1. 24.6.4.14.1 Loopback Mode Configurations
        15. 24.6.4.15 Error Reporting
          1. 24.6.4.15.1 Buffer Underrun Error -Transmitter
          2. 24.6.4.15.2 Buffer Overrun Error-Receiver
          3. 24.6.4.15.3 DATA Port Error - Transmitter
          4. 24.6.4.15.4 DATA Port Error - Receiver
          5. 24.6.4.15.5 Unexpected Frame Sync Error
          6. 24.6.4.15.6 Clock Failure Detection
            1. 24.6.4.15.6.1 Clock Failure Check Startup
            2. 24.6.4.15.6.2 Transmit Clock Failure Check and Recovery
            3. 24.6.4.15.6.3 Receive Clock Failure Check and Recovery
      5. 24.6.5 McASP Low-Level Programming Model
        1. 24.6.5.1 Global Initialization
          1. 24.6.5.1.1 Surrounding Modules Global Initialization
          2. 24.6.5.1.2 McASP Global Initialization
            1. 24.6.5.1.2.1 Main Sequence – McASP Global Initialization for DIT-Transmission
              1. 24.6.5.1.2.1.1 Subsequence – Transmit Format Unit Configuration for DIT-Transmission
              2. 24.6.5.1.2.1.2 Subsequence – Transmit Frame Synchronization Generator Configuration for DIT-Transmission
              3. 24.6.5.1.2.1.3 Subsequence – Transmit Clock Generator Configuration for DIT-Transmission
              4. 24.6.5.1.2.1.4 Subsequence - McASP Pins Functional Configuration
              5. 24.6.5.1.2.1.5 Subsequence – DIT-specific Subframe Fields Configuration
            2. 24.6.5.1.2.2 Main Sequence – McASP Global Initialization for TDM-Reception
              1. 24.6.5.1.2.2.1 Subsequence – Receive Format Unit Configuration in TDM Mode
              2. 24.6.5.1.2.2.2 Subsequence – Receive Frame Synchronization Generator Configuration in TDM Mode
              3. 24.6.5.1.2.2.3 Subsequence – Receive Clock Generator Configuration
              4. 24.6.5.1.2.2.4 Subsequence—McASP Receiver Pins Functional Configuration
            3. 24.6.5.1.2.3 Main Sequence – McASP Global Initialization for TDM -Transmission
              1. 24.6.5.1.2.3.1 Subsequence – Transmit Format Unit Configuration in TDM Mode
              2. 24.6.5.1.2.3.2 Subsequence – Transmit Frame Synchronization Generator Configuration in TDM Mode
              3. 24.6.5.1.2.3.3 Subsequence – Transmit Clock Generator Configuration for TDM Cases
              4. 24.6.5.1.2.3.4 Subsequence—McASP Transmit Pins Functional Configuration
        2. 24.6.5.2 Operational Modes Configuration
          1. 24.6.5.2.1 McASP Transmission Modes
            1. 24.6.5.2.1.1 Main Sequence – McASP DIT- /TDM- Polling Transmission Method
            2. 24.6.5.2.1.2 Main Sequence – McASP DIT- /TDM - Interrupt Transmission Method
            3. 24.6.5.2.1.3 Main Sequence –McASP DIT- /TDM - Mode DMA Transmission Method
          2. 24.6.5.2.2 McASP Reception Modes
            1. 24.6.5.2.2.1 Main Sequence – McASP Polling Reception Method
            2. 24.6.5.2.2.2 Main Sequence – McASP TDM - Interrupt Reception Method
            3. 24.6.5.2.2.3 Main Sequence – McASP TDM - Mode DMA Reception Method
          3. 24.6.5.2.3 McASP Event Servicing
            1. 24.6.5.2.3.1 McASP DIT-/TDM- Transmit Interrupt Events Servicing
            2. 24.6.5.2.3.2 McASP TDM- Receive Interrupt Events Servicing
            3. 24.6.5.2.3.3 3645
            4. 24.6.5.2.3.4 Subsequence – McASP DIT-/TDM -Modes Transmit Error Handling
            5. 24.6.5.2.3.5 Subsequence – McASP Receive Error Handling
      6. 24.6.6 McASP Register Manual
        1. 24.6.6.1 McASP Instance Summary
        2. 24.6.6.2 McASP Registers
          1. 24.6.6.2.1 MCASP_CFG Register Summary
          2. 24.6.6.2.2 MCASP_CFG Register Description
          3. 24.6.6.2.3 MCASP_AFIFO Register Summary
          4. 24.6.6.2.4 MCASP_AFIFO Register Description
          5. 24.6.6.2.5 MCASP_DAT Register Summary
          6. 24.6.6.2.6 MCASP_DAT Register Description
    7. 24.7  SuperSpeed USB DRD
      1. 24.7.1 SuperSpeed USB DRD Subsystem Overview
        1. 24.7.1.1 Main Features
      2. 24.7.2 SuperSpeed USB DRD Subsystem Environment
        1. 24.7.2.1 SuperSpeed USB DRD Subsystem I/O Interfaces
        2. 24.7.2.2 SuperSpeed USB Subsystem Application
          1. 24.7.2.2.1 USB3.0 DRD Application
          2. 24.7.2.2.2 USB2.0 DRD Internal PHY
          3. 24.7.2.2.3 USB2.0 DRD External PHY
          4. 24.7.2.2.4 3666
          5. 24.7.2.2.5 Host Mode
          6. 24.7.2.2.6 Device Mode
      3. 24.7.3 SuperSpeed USB Subsystem Integration
    8. 24.8  SATA Controller
      1. 24.8.1 SATA Controller Overview
        1. 24.8.1.1 SATA Controller
          1. 24.8.1.1.1 AHCI Mode Overview
          2. 24.8.1.1.2 Native Command Queuing
          3. 24.8.1.1.3 SATA Transport Layer Functionalities
          4. 24.8.1.1.4 SATA Link Layer Functionalities
        2. 24.8.1.2 SATA Controller Features
      2. 24.8.2 SATA Controller Environment
      3. 24.8.3 SATA Controller Integration
      4. 24.8.4 SATA Controller Functional Description
        1. 24.8.4.1  SATA Controller Block Diagram
        2. 24.8.4.2  SATA Controller Link Layer Protocol and Data Format
          1. 24.8.4.2.1 SATA 8b/10b Parallel Encoding/Decoding
          2. 24.8.4.2.2 SATA Stream Dword Components
          3. 24.8.4.2.3 Scrambling/Descrambling Processing
        3. 24.8.4.3  Resets
          1. 24.8.4.3.1 Hardware Reset
          2. 24.8.4.3.2 Software Initiated Resets
            1. 24.8.4.3.2.1 Software Reset
            2. 24.8.4.3.2.2 Port Reset
            3. 24.8.4.3.2.3 HBA Reset
        4. 24.8.4.4  Power Management
          1. 24.8.4.4.1 SATA Specific Power Management
            1. 24.8.4.4.1.1 PARTIAL Power Mode
            2. 24.8.4.4.1.2 Slumber Power Mode
            3. 24.8.4.4.1.3 Software Control over Low Power States
            4. 24.8.4.4.1.4 Aggressive Power Management
          2. 24.8.4.4.2 Master Standby and Slave Idle Management Protocols
          3. 24.8.4.4.3 Clock Gating Synchronization
          4. 24.8.4.4.4 3700
        5. 24.8.4.5  Interrupt Requests
          1. 24.8.4.5.1 Interrupt Generation
          2. 24.8.4.5.2 Levels of Interrupt Control
          3. 24.8.4.5.3 Interrupt Events Description
            1. 24.8.4.5.3.1  Task File Error Status
            2. 24.8.4.5.3.2  Host Bus Fatal Error
            3. 24.8.4.5.3.3  Interface Fatal Error Status
            4. 24.8.4.5.3.4  Interface Non-Fatal Error Status
            5. 24.8.4.5.3.5  Overflow Status
            6. 24.8.4.5.3.6  Incorrect Port Multiplier Status
            7. 24.8.4.5.3.7  PHYReady Change Status
            8. 24.8.4.5.3.8  Port Connect Change Status
            9. 24.8.4.5.3.9  Descriptor Processed
            10. 24.8.4.5.3.10 Unknown FIS Interrupt
            11. 24.8.4.5.3.11 Set Device Bits Interrupt
            12. 24.8.4.5.3.12 DMA Setup FIS Interrupt
            13. 24.8.4.5.3.13 PIO Setup FIS Interrupt
            14. 24.8.4.5.3.14 Device to Host Register FIS Interrupt
          4. 24.8.4.5.4 Interrupt Condition Control
          5. 24.8.4.5.5 Command Completion Coalescing Interrupts
            1. 24.8.4.5.5.1 CCC Interrupt Based on Expired Timeout Value
            2. 24.8.4.5.5.2 CCC Interrupt Based on Completion Count
        6. 24.8.4.6  System Memory FIS Descriptors
          1. 24.8.4.6.1 Command List Structure Basics
          2. 24.8.4.6.2 Supported Types of Commands
          3. 24.8.4.6.3 Received FIS Structures
          4. 24.8.4.6.4 FIS Descriptors Summary
        7. 24.8.4.7  Transport Layer FIS-Based Interactions
          1. 24.8.4.7.1 Software Processing of the Port Command List
          2. 24.8.4.7.2 Handling the Received FIS Descriptors
        8. 24.8.4.8  DMA Port Configuration
        9. 24.8.4.9  Port Multiplier Operation
          1. 24.8.4.9.1 Command-Based Switching Mode
            1. 24.8.4.9.1.1 Port Multiplier NCQ and Non-NCQ Commands Generation
          2. 24.8.4.9.2 Port Multiplier Enumeration
        10. 24.8.4.10 Activity LED Generation Functionality
        11. 24.8.4.11 Supported Types of SATA Transfers
          1. 24.8.4.11.1 Supported Higher Level Protocols
        12. 24.8.4.12 SATA Controller AHCI Hardware Register Interface
      5. 24.8.5 SATA Controller Low Level Programming Model
        1. 24.8.5.1 Global Initialization
          1. 24.8.5.1.1 Surrounding Modules Global Initialization
          2. 24.8.5.1.2 SATA Controller Global Initialization
            1. 24.8.5.1.2.1 Main Sequence SATA Controller Global Initialization
            2. 24.8.5.1.2.2 SubSequence – Firmware Capability Writes
          3. 24.8.5.1.3 Issue Command - Main Sequence
          4. 24.8.5.1.4 Receive FIS—Main Sequence
      6. 24.8.6 SATA Controller Register Manual
        1. 24.8.6.1 SATA Controller Instance Summary
        2. 24.8.6.2 DWC_ahsata Registers
          1. 24.8.6.2.1 DWC_ahsata Register Summary
          2. 24.8.6.2.2 DWC_ahsata Register Description
        3. 24.8.6.3 SATAMAC_wrapper Registers
          1. 24.8.6.3.1 SATAMAC_wrapper Register Summary
          2. 24.8.6.3.2 SATAMAC_wrapper Register Description
    9. 24.9  PCIe Controller
      1. 24.9.1 PCIe Controller Subsystem Overview
        1. 24.9.1.1 PCIe Controllers Key Features
      2. 24.9.2 PCIe Controller Environment
      3. 24.9.3 PCIe Controllers Integration
      4. 24.9.4 PCIe SS Controller Functional Description
        1. 24.9.4.1 PCIe Controller Functional Block Diagram
        2. 24.9.4.2 PCIe Traffics
        3. 24.9.4.3 PCIe Controller Ports on L3_MAIN Interconnect
          1. 24.9.4.3.1 PCIe Controller Master Port
            1. 24.9.4.3.1.1 PCIe Controller Master Port to MMU Routing
          2. 24.9.4.3.2 PCIe Controller Slave Port
          3. 24.9.4.3.3 3768
        4. 24.9.4.4 PCIe Controller Reset Management
          1. 24.9.4.4.1 PCIe Reset Types and Stickiness
          2. 24.9.4.4.2 PCIe Reset Conditions
            1. 24.9.4.4.2.1 PCIe Main Reset
              1. 24.9.4.4.2.1.1 PCIe Subsystem Cold Main Reset Source
              2. 24.9.4.4.2.1.2 PCIe Subsystem Warm Main Reset Sources
            2. 24.9.4.4.2.2 PCIe Standard Specific Resets to the PCIe Core Logic
        5. 24.9.4.5 PCIe Controller Power Management
          1. 24.9.4.5.1 PCIe Protocol Power Management
            1. 24.9.4.5.1.1 PCIe Device/function power state (D-state)
            2. 24.9.4.5.1.2 PCIe Controller PIPE Powerstate (Powerdown Control)
          2. 24.9.4.5.2 PCIE Controller Clocks Management
            1. 24.9.4.5.2.1 PCIe Clock Domains
            2. 24.9.4.5.2.2 PCIe Controller Idle/Standby Clock Management Interfaces
              1. 24.9.4.5.2.2.1 PCIe Controller Master Standby Behavior
              2. 24.9.4.5.2.2.2 PCIe Controller Slave Idle/Disconnect Behavior
                1. 24.9.4.5.2.2.2.1 PCIe Controller Idle Sequence During D3cold/L3 State
        6. 24.9.4.6 PCIe Controller Interrupt Requests
          1. 24.9.4.6.1 PCIe Controller Main Hardware Management
            1. 24.9.4.6.1.1 PCIe Management Interrupt Events
            2. 24.9.4.6.1.2 PCIe Error Interrupt Events
            3. 24.9.4.6.1.3 Summary of PCIe Controller Main Hardware Interrupt Events
          2. 24.9.4.6.2 PCIe Controller Legacy and MSI Virtual Interrupts Management
            1. 24.9.4.6.2.1 Legacy PCI Interrupts (INTx)
              1. 24.9.4.6.2.1.1 Legacy PCI Interrupt Events Overview
              2. 24.9.4.6.2.1.2 Legacy PCI Interrupt Transmission (EP mode only)
              3. 24.9.4.6.2.1.3 Legacy PCI Interrupt Reception (RC mode only)
            2. 24.9.4.6.2.2 PCIe Controller Message Signaled Interrupts (MSI)
              1. 24.9.4.6.2.2.1 PCIe Specific MSI Interrupt Event Overview
              2. 24.9.4.6.2.2.2 PCIe Controller MSI Transmission Methods (EP mode)
                1. 24.9.4.6.2.2.2.1 PCIe Controller MSI transmission, hardware method
                2. 24.9.4.6.2.2.2.2 PCIe Controller MSI transmission, software method
              3. 24.9.4.6.2.2.3 PCIe Controller MSI Reception (RC mode)
          3. 24.9.4.6.3 PCIe Controller MSI Hardware Interrupt Events
        7. 24.9.4.7 PCIe Controller Address Spaces and Address Translation
        8. 24.9.4.8 PCIe Traffic Requesting and Responding
          1. 24.9.4.8.1 PCIe Memory-type (Mem) Traffic Management
            1. 24.9.4.8.1.1 PCIe Memory Requesting
            2. 24.9.4.8.1.2 PCIe Memory Responding
          2. 24.9.4.8.2 PCIe Configuration Type (Cfg) Traffic Management
            1. 24.9.4.8.2.1 RC Self-configuration (RC Only)
            2. 24.9.4.8.2.2 Configuration Requests over PCIe (RC Only)
            3. 24.9.4.8.2.3 Configuration Responding over PCIe (EP Only)
          3. 24.9.4.8.3 PCIe I/O-type (IO) traffic management
            1. 24.9.4.8.3.1 PCIe I/O requesting (RC only)
            2. 24.9.4.8.3.2 PCIe IO BAR initialization before enumeration (EP only)
            3. 24.9.4.8.3.3 PCIe I/O responding (PCI legacy EP only)
          4. 24.9.4.8.4 PCIe Message-type (Msg) traffic management
        9. 24.9.4.9 PCIe Programming Register Interface
          1. 24.9.4.9.1 PCIe Register Access
          2. 24.9.4.9.2 Double Mapping of the PCIe Local Control Registers
          3. 24.9.4.9.3 Base Address Registers (BAR) Initialization
      5. 24.9.5 PCIe Controller Low Level Programming Model
        1. 24.9.5.1 Surrounding Modules Global Initialization
        2. 24.9.5.2 Main Sequence of PCIe Controllers Initalization
      6. 24.9.6 PCIe Standard Registers vs PCIe Subsystem Hardware Registers Mapping
      7. 24.9.7 PCIe Controller Register Manual
        1. 24.9.7.1 PCIe Controller Instance Summary
        2. 24.9.7.2 PCIe_SS_EP_CFG_PCIe Registers
          1. 24.9.7.2.1 PCIe_SS_EP_CFG_PCIe Register Summary
          2. 24.9.7.2.2 PCIe_SS_EP_CFG_PCIe Register Description
          3. 24.9.7.2.3 3830
        3. 24.9.7.3 PCIe_SS_EP_CFG_DBICS Registers
          1. 24.9.7.3.1 PCIe_SS_EP_CFG_DBICS Register Summary
          2. 24.9.7.3.2 PCIe_SS_EP_CFG_DBICS Register Description
        4. 24.9.7.4 PCIe_SS_RC_CFG_DBICS Registers
          1. 24.9.7.4.1 PCIe_SS_RC_CFG_DBICS Register Summary
          2. 24.9.7.4.2 PCIe_SS_RC_CFG_DBICS Register Description
        5. 24.9.7.5 PCIe_SS_PL_CONF Registers
          1. 24.9.7.5.1 PCIe_SS_PL_CONF Register Summary
          2. 24.9.7.5.2 PCIe_SS_PL_CONF Register Description
        6. 24.9.7.6 PCIe_SS_EP_CFG_DBICS2 Registers
          1. 24.9.7.6.1 PCIe_SS_EP_CFG_DBICS2 Register Summary
          2. 24.9.7.6.2 PCIe_SS_EP_CFG_DBICS2 Register Description
        7. 24.9.7.7 PCIe_SS_RC_CFG_DBICS2 Registers
          1. 24.9.7.7.1 PCIe_SS_RC_CFG_DBICS2 Register Summary
          2. 24.9.7.7.2 PCIe_SS_RC_CFG_DBICS2 Register Description
        8. 24.9.7.8 PCIe_SS_TI_CONF Registers
          1. 24.9.7.8.1 PCIe_SS_TI_CONF Register Summary
          2. 24.9.7.8.2 PCIe_SS_TI_CONF Register Description
    10. 24.10 DCAN
      1. 24.10.1 DCAN Overview
        1. 24.10.1.1 Features
      2. 24.10.2 DCAN Environment
        1. 24.10.2.1 CAN Network Basics
      3. 24.10.3 DCAN Integration
      4. 24.10.4 DCAN Functional Description
        1. 24.10.4.1  Module Clocking Requirements
        2. 24.10.4.2  Interrupt Functionality
          1. 24.10.4.2.1 Message Object Interrupts
          2. 24.10.4.2.2 Status Change Interrupts
          3. 24.10.4.2.3 Error Interrupts
        3. 24.10.4.3  DMA Functionality
        4. 24.10.4.4  Local Power-Down Mode
          1. 24.10.4.4.1 Entering Local Power-Down Mode
          2. 24.10.4.4.2 Wakeup From Local Power Down
        5. 24.10.4.5  Parity Check Mechanism
          1. 24.10.4.5.1 Behavior on Parity Error
          2. 24.10.4.5.2 Parity Testing
        6. 24.10.4.6  Debug/Suspend Mode
        7. 24.10.4.7  Configuration of Message Objects Description
          1. 24.10.4.7.1 Configuration of a Transmit Object for Data Frames
          2. 24.10.4.7.2 Configuration of a Transmit Object for Remote Frames
          3. 24.10.4.7.3 Configuration of a Single Receive Object for Data Frames
          4. 24.10.4.7.4 Configuration of a Single Receive Object for Remote Frames
          5. 24.10.4.7.5 Configuration of a FIFO Buffer
        8. 24.10.4.8  Message Handling
          1. 24.10.4.8.1  Message Handler Overview
          2. 24.10.4.8.2  Receive/Transmit Priority
          3. 24.10.4.8.3  Transmission of Messages in Event Driven CAN Communication
          4. 24.10.4.8.4  Updating a Transmit Object
          5. 24.10.4.8.5  Changing a Transmit Object
          6. 24.10.4.8.6  Acceptance Filtering of Received Messages
          7. 24.10.4.8.7  Reception of Data Frames
          8. 24.10.4.8.8  Reception of Remote Frames
          9. 24.10.4.8.9  Reading Received Messages
          10. 24.10.4.8.10 Requesting New Data for a Receive Object
          11. 24.10.4.8.11 Storing Received Messages in FIFO Buffers
          12. 24.10.4.8.12 Reading From a FIFO Buffer
        9. 24.10.4.9  CAN Bit Timing
          1. 24.10.4.9.1 Bit Time and Bit Rate
            1. 24.10.4.9.1.1 Synchronization Segment
            2. 24.10.4.9.1.2 Propagation Time Segment
            3. 24.10.4.9.1.3 Phase Buffer Segments and Synchronization
            4. 24.10.4.9.1.4 Oscillator Tolerance Range
          2. 24.10.4.9.2 DCAN Bit Timing Registers
            1. 24.10.4.9.2.1 Calculation of the Bit Timing Parameters
            2. 24.10.4.9.2.2 Example for Bit Timing Calculation
        10. 24.10.4.10 Message Interface Register Sets
          1. 24.10.4.10.1 Message Interface Register Sets 1 and 2
          2. 24.10.4.10.2 IF3 Register Set
        11. 24.10.4.11 Message RAM
          1. 24.10.4.11.1 Structure of Message Objects
          2. 24.10.4.11.2 Addressing Message Objects in RAM
          3. 24.10.4.11.3 Message RAM Representation in Debug/Suspend Mode
          4. 24.10.4.11.4 Message RAM Representation in Direct Access Mode
        12. 24.10.4.12 CAN Operation
          1. 24.10.4.12.1 CAN Module Initialization
            1. 24.10.4.12.1.1 Configuration of CAN Bit Timing
            2. 24.10.4.12.1.2 Configuration of Message Objects
            3. 24.10.4.12.1.3 DCAN RAM Hardware Initialization
          2. 24.10.4.12.2 CAN Message Transfer (Normal Operation)
            1. 24.10.4.12.2.1 Automatic Retransmission
            2. 24.10.4.12.2.2 Auto-Bus-On
          3. 24.10.4.12.3 Test Modes
            1. 24.10.4.12.3.1 Silent Mode
            2. 24.10.4.12.3.2 Loopback Mode
            3. 24.10.4.12.3.3 External Loopback Mode
            4. 24.10.4.12.3.4 Loopback Mode Combined With Silent Mode
            5. 24.10.4.12.3.5 Software Control of CAN_TX Pin
        13. 24.10.4.13 GPIO Support
      5. 24.10.5 DCAN Register Manual
        1. 24.10.5.1 DCAN Instance Summary
        2. 24.10.5.2 DCAN Registers
          1. 24.10.5.2.1 DCAN Register Summary
          2. 24.10.5.2.2 DCAN Register Description
    11. 24.11 Gigabit Ethernet Switch (GMAC_SW)
      1. 24.11.1 GMAC_SW Overview
        1. 24.11.1.1 Features
        2. 24.11.1.2 3928
      2. 24.11.2 GMAC_SW Environment
        1. 24.11.2.1 G/MII Interface
        2. 24.11.2.2 RMII Interface
        3. 24.11.2.3 RGMII Interface
      3. 24.11.3 GMAC_SW Integration
      4. 24.11.4 GMAC_SW Functional Description
        1. 24.11.4.1  Functional Block Diagram
        2. 24.11.4.2  GMAC_SW Ports
          1. 24.11.4.2.1 Interface Mode Selection
        3. 24.11.4.3  Clocking
          1. 24.11.4.3.1 Subsystem Clocking
          2. 24.11.4.3.2 Interface Clocking
            1. 24.11.4.3.2.1 G/MII Interface Clocking
            2. 24.11.4.3.2.2 RGMII Interface Clocking
            3. 24.11.4.3.2.3 RMII Interface Clocking
            4. 24.11.4.3.2.4 MDIO Clocking
        4. 24.11.4.4  Software IDLE
        5. 24.11.4.5  Interrupt Functionality
          1. 24.11.4.5.1 Receive Packet Completion Pulse Interrupt (RX_PULSE)
          2. 24.11.4.5.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE)
          3. 24.11.4.5.3 Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)
          4. 24.11.4.5.4 Miscellaneous Pulse Interrupt (MISC_PULSE)
            1. 24.11.4.5.4.1 EVNT_PEND( CPTS_PEND) Interrupt
            2. 24.11.4.5.4.2 Statistics Interrupt
            3. 24.11.4.5.4.3 Host Error interrupt
            4. 24.11.4.5.4.4 MDIO Interrupts
          5. 24.11.4.5.5 Interrupt Pacing
        6. 24.11.4.6  Reset Isolation
          1. 24.11.4.6.1 Reset Isolation Functional Description
        7. 24.11.4.7  Software Reset
        8. 24.11.4.8  CPSW_3G
          1. 24.11.4.8.1  CPDMA RX and TX Interfaces
            1. 24.11.4.8.1.1 Functional Operation
            2. 24.11.4.8.1.2 Receive DMA Interface
              1. 24.11.4.8.1.2.1 Receive DMA Host Configuration
              2. 24.11.4.8.1.2.2 Receive Channel Teardown
            3. 24.11.4.8.1.3 Transmit DMA Interface
              1. 24.11.4.8.1.3.1 Transmit DMA Host Configuration
              2. 24.11.4.8.1.3.2 Transmit Channel Teardown
            4. 24.11.4.8.1.4 Transmit Rate Limiting
            5. 24.11.4.8.1.5 Command IDLE
          2. 24.11.4.8.2  Address Lookup Engine (ALE)
            1. 24.11.4.8.2.1 Address Table Entry
              1. 24.11.4.8.2.1.1 Free Table Entry
              2. 24.11.4.8.2.1.2 Multicast Address Table Entry
              3. 24.11.4.8.2.1.3 VLAN/Multicast Address Table Entry
              4. 24.11.4.8.2.1.4 Unicast Address Table Entry
              5. 24.11.4.8.2.1.5 OUI Unicast Address Table Entry
              6. 24.11.4.8.2.1.6 VLAN/Unicast Address Table Entry
              7. 24.11.4.8.2.1.7 VLAN Table Entry
            2. 24.11.4.8.2.2 Packet Forwarding Processes
            3. 24.11.4.8.2.3 Learning Process
            4. 24.11.4.8.2.4 VLAN Aware Mode
            5. 24.11.4.8.2.5 VLAN Unaware Mode
          3. 24.11.4.8.3  Packet Priority Handling
          4. 24.11.4.8.4  FIFO Memory Control
          5. 24.11.4.8.5  FIFO Transmit Queue Control
            1. 24.11.4.8.5.1 Normal Priority Mode
            2. 24.11.4.8.5.2 Dual MAC Mode
            3. 24.11.4.8.5.3 Rate Limit Mode
          6. 24.11.4.8.6  Audio Video Bridging
            1. 24.11.4.8.6.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
              1. 24.11.4.8.6.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
              2. 24.11.4.8.6.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
            2. 24.11.4.8.6.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
              1. 24.11.4.8.6.2.1 Configuring the Device for 802.1Qav Operation:
          7. 24.11.4.8.7  Ethernet MAC Sliver (CPGMAC_SL)
            1. 24.11.4.8.7.1 G/MII Media Independent Interface
              1. 24.11.4.8.7.1.1 Data Reception
                1. 24.11.4.8.7.1.1.1 Receive Control
                2. 24.11.4.8.7.1.1.2 Receive Inter-Frame Interval
              2. 24.11.4.8.7.1.2 Data Transmission
                1. 24.11.4.8.7.1.2.1 Transmit Control
                2. 24.11.4.8.7.1.2.2 CRC Insertion
                3. 24.11.4.8.7.1.2.3 MTXER
                4. 24.11.4.8.7.1.2.4 Adaptive Performance Optimization (APO)
                5. 24.11.4.8.7.1.2.5 Inter-Packet-Gap Enforcement
                6. 24.11.4.8.7.1.2.6 Back Off
                7. 24.11.4.8.7.1.2.7 Programmable Transmit Inter-Packet Gap
                8. 24.11.4.8.7.1.2.8 Speed, Duplex and Pause Frame Support Negotiation
            2. 24.11.4.8.7.2 RMII Interface
              1. 24.11.4.8.7.2.1 Features
              2. 24.11.4.8.7.2.2 RMII Receive (RX)
              3. 24.11.4.8.7.2.3 RMII Transmit (TX)
            3. 24.11.4.8.7.3 RGMII Interface
              1. 24.11.4.8.7.3.1 RGMII Features
              2. 24.11.4.8.7.3.2 RGMII Receive (RX)
              3. 24.11.4.8.7.3.3 In-Band Mode of Operation
              4. 24.11.4.8.7.3.4 Forced Mode of Operation
              5. 24.11.4.8.7.3.5 RGMII Transmit (TX)
            4. 24.11.4.8.7.4 Frame Classification
          8. 24.11.4.8.8  Embedded Memories
          9. 24.11.4.8.9  Flow Control
            1. 24.11.4.8.9.1 CPPI Port Flow Control
            2. 24.11.4.8.9.2 Ethernet Port Flow Control
              1. 24.11.4.8.9.2.1 Receive Flow Control
                1. 24.11.4.8.9.2.1.1 Collision Based Receive Buffer Flow Control
                2. 24.11.4.8.9.2.1.2 IEEE 802.3X Based Receive Flow Control
              2. 24.11.4.8.9.2.2 Transmit Flow Control
          10. 24.11.4.8.10 Short Gap
          11. 24.11.4.8.11 Switch Latency
          12. 24.11.4.8.12 Emulation Control
          13. 24.11.4.8.13 FIFO Loopback
          14. 24.11.4.8.14 Device Level Ring (DLR) Support
          15. 24.11.4.8.15 Energy Efficient Ethernet Support (802.3az)
          16. 24.11.4.8.16 CPSW_3G Network Statistics
            1. 24.11.4.8.16.1 4035
        9. 24.11.4.9  Static Packet Filter (SPF)
          1. 24.11.4.9.1 SPF Overview
          2. 24.11.4.9.2 SPF Functional Description
            1. 24.11.4.9.2.1 SPF Block Diagram
            2. 24.11.4.9.2.2 Interrupts
            3. 24.11.4.9.2.3 Protocol Header Extractor
            4. 24.11.4.9.2.4 Programmable Rule Engine
              1. 24.11.4.9.2.4.1 Internal Registers
              2. 24.11.4.9.2.4.2 Packet Buffer
            5. 24.11.4.9.2.5 Intrusion Event Logger
            6. 24.11.4.9.2.6 Rate Limiter
            7. 24.11.4.9.2.7 Rule Engine Instruction Set Architecture
              1. 24.11.4.9.2.7.1 Instruction Format
              2. 24.11.4.9.2.7.2 Operand Field
              3. 24.11.4.9.2.7.3 Arithmetic/Logical Function Field
              4. 24.11.4.9.2.7.4 Operation Field
          3. 24.11.4.9.3 Programming Guide
            1. 24.11.4.9.3.1 Initialization Routine
            2. 24.11.4.9.3.2 Interrupt Service Routine
            3. 24.11.4.9.3.3 Rule Engine Example Program
        10. 24.11.4.10 Common Platform Time Sync (CPTS)
          1. 24.11.4.10.1 CPTS Architecture
          2. 24.11.4.10.2 CPTS Initialization
          3. 24.11.4.10.3 Time Stamp Value
          4. 24.11.4.10.4 Event FIFO
          5. 24.11.4.10.5 Time Sync Events
            1. 24.11.4.10.5.1 Time Stamp Push Event
            2. 24.11.4.10.5.2 Time Stamp Counter Rollover Event
            3. 24.11.4.10.5.3 Time Stamp Counter Half-rollover Event
            4. 24.11.4.10.5.4 Hardware Time Stamp Push Event
            5. 24.11.4.10.5.5 Ethernet Port Events
          6. 24.11.4.10.6 CPTS Interrupt Handling
        11. 24.11.4.11 CPPI Buffer Descriptors
          1. 24.11.4.11.1 TX Buffer Descriptors
            1. 24.11.4.11.1.1 CPPI TX Data Word 0
            2. 24.11.4.11.1.2 CPPI TX Data Word 1
            3. 24.11.4.11.1.3 CPPI TX Data Word 2
            4. 24.11.4.11.1.4 CPPI TX Data Word 3
          2. 24.11.4.11.2 RX Buffer Descriptors
            1. 24.11.4.11.2.1 CPPI RX Data Word 0
            2. 24.11.4.11.2.2 CPPI RX Data Word 1
            3. 24.11.4.11.2.3 CPPI RX Data Word 2
            4. 24.11.4.11.2.4 CPPI RX Data Word 3
        12. 24.11.4.12 MDIO
          1. 24.11.4.12.1 MDIO Frame Formats
          2. 24.11.4.12.2 MDIO Functional Description
      5. 24.11.5 GMAC_SW Programming Guide
        1. 24.11.5.1 Transmit Operation
        2. 24.11.5.2 Receive Operation
        3. 24.11.5.3 MDIO Software Interface
          1. 24.11.5.3.1 Initializing the MDIO Module
          2. 24.11.5.3.2 Writing Data To a PHY Register
          3. 24.11.5.3.3 Reading Data From a PHY Register
        4. 24.11.5.4 Initialization and Configuration of CPSW
      6. 24.11.6 GMAC_SW Register Manual
        1. 24.11.6.1  GMAC_SW Instance Summary
        2. 24.11.6.2  SS Registers
          1. 24.11.6.2.1 SS Register Summary
          2. 24.11.6.2.2 SS Register Description
        3. 24.11.6.3  PORT Registers
          1. 24.11.6.3.1 PORT Register Summary
          2. 24.11.6.3.2 PORT Register Description
        4. 24.11.6.4  CPDMA registers
          1. 24.11.6.4.1 CPDMA Register Summary
          2. 24.11.6.4.2 CPDMA Register Description
        5. 24.11.6.5  STATS Registers
          1. 24.11.6.5.1 STATS Register Summary
          2. 24.11.6.5.2 STATS Register Description
        6. 24.11.6.6  STATERAM Registers
          1. 24.11.6.6.1 STATERAM Register Summary
          2. 24.11.6.6.2 STATERAM Register Description
        7. 24.11.6.7  CPTS registers
          1. 24.11.6.7.1 CPTS Register Summary
          2. 24.11.6.7.2 CPTS Register Description
        8. 24.11.6.8  ALE registers
          1. 24.11.6.8.1 ALE Register Summary
          2. 24.11.6.8.2 ALE Register Description
        9. 24.11.6.9  SL registers
          1. 24.11.6.9.1 SL Register Summary
          2. 24.11.6.9.2 SL Register Description
        10. 24.11.6.10 MDIO registers
          1. 24.11.6.10.1 MDIO Register Summary
          2. 24.11.6.10.2 MDIO Register Description
        11. 24.11.6.11 WR registers
          1. 24.11.6.11.1 WR Register Summary
          2. 24.11.6.11.2 WR Register Description
        12. 24.11.6.12 SPF Registers
          1. 24.11.6.12.1 SPF Register Summary
          2. 24.11.6.12.2 SPF Register Description
    12. 24.12 Media Local Bus (MLB)
      1. 24.12.1 MLB Overview
      2. 24.12.2 MLB Environment
        1. 24.12.2.1 MLB IO Cell Controls
      3. 24.12.3 MLB Integration
      4. 24.12.4 MLB Functional Description
        1. 24.12.4.1 Block Diagram
          1. 24.12.4.1.1 MediaLB Core Block
          2. 24.12.4.1.2 Routing Fabric Block
          3. 24.12.4.1.3 Data Buffer RAM
          4. 24.12.4.1.4 Channel Table RAM
            1. 24.12.4.1.4.1 Channel Allocation Table
            2. 24.12.4.1.4.2 Channel Descriptor Table
          5. 24.12.4.1.5 DMA Block
            1. 24.12.4.1.5.1 Synchronous Channel Descriptor
            2. 24.12.4.1.5.2 Isochronous Channel Descriptors
            3. 24.12.4.1.5.3 Asynchronous and Control Channel Descriptors
              1. 24.12.4.1.5.3.1 Single-Packet Mode
              2. 24.12.4.1.5.3.2 Multiple-Packet Mode
        2. 24.12.4.2 Software and Data Flow for MLBSS
          1. 24.12.4.2.1 Data Flow For Receive Channels
          2. 24.12.4.2.2 Data Flow for Transmit Channels
        3. 24.12.4.3 MLB Priority On The L3_MAIN Interconnect
      5. 24.12.5 MLB Programming Guide
        1. 24.12.5.1 Global Initialization
          1. 24.12.5.1.1 Surrounding Modules Global Initialization
          2. 24.12.5.1.2 MLBSS Global Initialization
            1. 24.12.5.1.2.1 Channel Initialization
        2. 24.12.5.2 MLBSS Operational Modes Configuration
          1. 24.12.5.2.1 Channel Servicing
          2. 24.12.5.2.2 Channel Table RAM Access
      6. 24.12.6 MLB Register Manual
        1. 24.12.6.1 MLB Instance Summary
        2. 24.12.6.2 MLB registers
          1. 24.12.6.2.1 MLB Register Summary
          2. 24.12.6.2.2 MLB Register Description
  27. 25eMMC/SD/SDIO
    1. 25.1 eMMC/SD/SDIO Overview
      1. 25.1.1 eMMC/SD/SDIO Features
    2. 25.2 eMMC/SD/SDIO Environment
      1. 25.2.1 eMMC/SD/SDIO Functional Modes
        1. 25.2.1.1 eMMC/SD/SDIO Connected to an eMMC, SD, or SDIO Card
      2. 25.2.2 Protocol and Data Format
        1. 25.2.2.1 Protocol
        2. 25.2.2.2 Data Format
    3. 25.3 eMMC/SD/SDIO Integration
    4. 25.4 eMMC/SD/SDIO Functional Description
      1. 25.4.1  Block Diagram
      2. 25.4.2  Resets
        1. 25.4.2.1 Hardware Reset
        2. 25.4.2.2 Software Reset
      3. 25.4.3  Power Management
      4. 25.4.4  Interrupt Requests
        1. 25.4.4.1 Interrupt-Driven Operation
        2. 25.4.4.2 Polling
        3. 25.4.4.3 Asynchronous Interrupt
      5. 25.4.5  DMA Modes
        1. 25.4.5.1 Master DMA Operations
          1. 25.4.5.1.1 Descriptor Table Description
          2. 25.4.5.1.2 Requirements for Descriptors
            1. 25.4.5.1.2.1 Data Length
            2. 25.4.5.1.2.2 Supported Features
            3. 25.4.5.1.2.3 Error Generation
          3. 25.4.5.1.3 Advanced DMA Description
        2. 25.4.5.2 Slave DMA Operations
          1. 25.4.5.2.1 DMA Receive Mode
          2. 25.4.5.2.2 DMA Transmit Mode
      6. 25.4.6  Mode Selection
      7. 25.4.7  Buffer Management
        1. 25.4.7.1 Data Buffer
          1. 25.4.7.1.1 Memory Size, Block Length, and Buffer-Management Relationship
          2. 25.4.7.1.2 Data Buffer Status
      8. 25.4.8  Transfer Process
        1. 25.4.8.1 Different Types of Commands
        2. 25.4.8.2 Different Types of Responses
      9. 25.4.9  Transfer or Command Status and Errors Reporting
        1. 25.4.9.1 Busy Time-Out for R1b, R5b Response Type
        2. 25.4.9.2 Busy Time-Out After Write CRC Status
        3. 25.4.9.3 Write CRC Status Time-Out
        4. 25.4.9.4 Read Data Time-Out
        5. 25.4.9.5 Boot Acknowledge Time-Out
      10. 25.4.10 Auto Command 12 Timings
        1. 25.4.10.1 Auto CMD12 Timings During Write Transfer
        2. 25.4.10.2 Auto CMD12 Timings During Read Transfer
      11. 25.4.11 Transfer Stop
      12. 25.4.12 Output Signals Generation
        1. 25.4.12.1 Generation on Falling Edge of MMC Clock
        2. 25.4.12.2 Generation on Rising Edge of MMC Clock
      13. 25.4.13 Sampling Clock Tuning
      14. 25.4.14 Card Boot Mode Management
        1. 25.4.14.1 Boot Mode Using CMD0
        2. 25.4.14.2 Boot Mode With CMD Line Tied to 0
      15. 25.4.15 MMC CE-ATA Command Completion Disable Management
      16. 25.4.16 Test Registers
      17. 25.4.17 eMMC/SD/SDIO Hardware Status Features
    5. 25.5 eMMC/SD/SDIO Programming Guide
      1. 25.5.1 Low-Level Programming Models
        1. 25.5.1.1 Global Initialization
          1. 25.5.1.1.1 Surrounding Modules Global Initialization
          2. 25.5.1.1.2 eMMC/SD/SDIO Host Controller Initialization Flow
            1. 25.5.1.1.2.1 Enable Interface and Functional Clock for MMC Controller
            2. 25.5.1.1.2.2 MMCHS Soft Reset Flow
            3. 25.5.1.1.2.3 Set MMCHS Default Capabilities
            4. 25.5.1.1.2.4 Wake-Up Configuration
            5. 25.5.1.1.2.5 MMC Host and Bus Configuration
        2. 25.5.1.2 Operational Modes Configuration
          1. 25.5.1.2.1 Basic Operations for eMMC/SD/SDIO Host Controller
            1. 25.5.1.2.1.1 Card Detection, Identification, and Selection
              1. 25.5.1.2.1.1.1 CMD Line Reset Procedure
            2. 25.5.1.2.1.2 Read/Write Transfer Flow in DMA Mode With Interrupt
              1. 25.5.1.2.1.2.1 DATA Lines Reset Procedure
            3. 25.5.1.2.1.3 Read/Write Transfer Flow in DMA Mode With Polling
            4. 25.5.1.2.1.4 Read/Write Transfer Flow Without DMA With Polling
            5. 25.5.1.2.1.5 Read/Write Transfer Flow in CE-ATA Mode
            6. 25.5.1.2.1.6 Suspend-Resume Flow
              1. 25.5.1.2.1.6.1 Suspend Flow
              2. 25.5.1.2.1.6.2 Resume Flow
            7. 25.5.1.2.1.7 Basic Operations – Steps Detailed
              1. 25.5.1.2.1.7.1 Command Transfer Flow
              2. 25.5.1.2.1.7.2 MMCHS Clock Frequency Change
              3. 25.5.1.2.1.7.3 Bus Width Selection
          2. 25.5.1.2.2 Bus Voltage Selection
          3. 25.5.1.2.3 Boot Mode Configuration
            1. 25.5.1.2.3.1 Boot Using CMD0
            2. 25.5.1.2.3.2 Boot With CMD Line Tied to 0
          4. 25.5.1.2.4 SDR104/HS200 DLL Tuning Procedure
    6. 25.6 eMMC/SD/SDIO Register Manual
      1. 25.6.1 eMMC/SD/SDIO Instance Summary
      2. 25.6.2 eMMC/SD/SDIO Registers
        1. 25.6.2.1 eMMC/SD/SDIO Register Summary
        2. 25.6.2.2 eMMC/SD/SDIO Register Description
  28. 26Shared PHY Component Subsystem
    1. 26.1 SATA PHY Subsystem
      1. 26.1.1 SATA PHY Subsystem Overview
      2. 26.1.2 SATA PHY Subsystem Environment
        1. 26.1.2.1 SATA PHY I/O Signals
      3. 26.1.3 SATA PHY Subsystem Integration
      4. 26.1.4 SATA PHY Subsystem Functional Description
        1. 26.1.4.1 SATA PLL Controller L4 Interface Adapter Functional Description
        2. 26.1.4.2 SATA PHY Serializer and Deserializer Functional Descriptions
          1. 26.1.4.2.1 SATA PHY Reset
          2. 26.1.4.2.2 SATA_PHY Clocking
            1. 26.1.4.2.2.1 SATA_PHY Input Clocks
            2. 26.1.4.2.2.2 SATA_PHY Output Clocks
          3. 26.1.4.2.3 SATA_PHY Power Management
            1. 26.1.4.2.3.1 SATA_PHY Power-Up/-Down Sequences
            2. 26.1.4.2.3.2 SATA_PHY Low-Power Modes
          4. 26.1.4.2.4 SATA_PHY Hardware Requests
        3. 26.1.4.3 SATA Clock Generator Subsystem Functional Description
          1. 26.1.4.3.1 SATA DPLL Clock Generator Overview
          2. 26.1.4.3.2 SATA DPLL Clock Generator Reset
          3. 26.1.4.3.3 SATA DPLL Low-Power Modes
          4. 26.1.4.3.4 SATA DPLL Clocks Configuration
            1. 26.1.4.3.4.1 SATA DPLL Input Clock Control
            2. 26.1.4.3.4.2 SATA DPLL Output Clock Configuration
              1. 26.1.4.3.4.2.1 SATA DPLL Output Clock Gating
          5. 26.1.4.3.5 SATA DPLL Subsystem Architecture
          6. 26.1.4.3.6 SATA DPLL Clock Generator Modes and State Transitions
            1. 26.1.4.3.6.1 SATA Clock Generator Power Up
            2. 26.1.4.3.6.2 SATA DPLL Sequences
            3. 26.1.4.3.6.3 SATA DPLL Locked Mode
            4. 26.1.4.3.6.4 SATA DPLL Idle-Bypass Mode
            5. 26.1.4.3.6.5 SATA DPLL MN-Bypass Mode
            6. 26.1.4.3.6.6 SATA DPLL Error Conditions
          7. 26.1.4.3.7 SATA PLL Controller Functions
            1. 26.1.4.3.7.1 SATA PLL Controller Register Access
            2. 26.1.4.3.7.2 SATA DPLL Clock Programming Sequence
            3. 26.1.4.3.7.3 SATA DPLL Recommended Values
      5. 26.1.5 SATA PHY Subsystem Low-Level Programming Model
    2. 26.2 USB3_PHY Subsystem
      1. 26.2.1 USB3_PHY Subsystem Overview
      2. 26.2.2 USB3_PHY Subsystem Environment
        1. 26.2.2.1 USB3_PHY I/O Signals
      3. 26.2.3 USB3_PHY Subsystem Integration
      4. 26.2.4 USB3_PHY Subsystem Functional Description
        1. 26.2.4.1 Super-Speed USB PLL Controller L4 Interface Adapter Functional Description
        2. 26.2.4.2 USB3_PHY Serializer and Deserializer Functional Descriptions
          1. 26.2.4.2.1 USB3_PHY Module Resets
            1. 26.2.4.2.1.1 Hardware Reset
            2. 26.2.4.2.1.2 Software Reset
          2. 26.2.4.2.2 USB3_PHY Subsystem Clocking
            1. 26.2.4.2.2.1 USB3_PHY Subsystem Input Clocks
            2. 26.2.4.2.2.2 USB3_PHY Subsystem Output Clocks
          3. 26.2.4.2.3 USB3_PHY Power Management
            1. 26.2.4.2.3.1 USB3_PHY Power-Up/-Down Sequences
            2. 26.2.4.2.3.2 USB3_PHY Low-Power Modes
            3. 26.2.4.2.3.3 Clock Gating
          4. 26.2.4.2.4 USB3_PHY Hardware Requests
        3. 26.2.4.3 USB3_PHY Clock Generator Subsystem Functional Description
          1. 26.2.4.3.1 USB3_PHY DPLL Clock Generator Overview
          2. 26.2.4.3.2 USB3_PHY DPLL Clock Generator Reset
          3. 26.2.4.3.3 USB3_PHY DPLL Low-Power Modes
          4. 26.2.4.3.4 USB3_PHY DPLL Clocks Configuration
            1. 26.2.4.3.4.1 USB3_PHY DPLL Input Clock Control
            2. 26.2.4.3.4.2 USB3_PHY DPLL Output Clock Configuration
              1. 26.2.4.3.4.2.1 USB3_PHY DPLL Output Clock Gating
          5. 26.2.4.3.5 USB3_PHY DPLL Subsystem Architecture
          6. 26.2.4.3.6 USB3_PHY DPLL Clock Generator Modes and State Transitions
            1. 26.2.4.3.6.1 USB3_PHY Clock Generator Power Up
            2. 26.2.4.3.6.2 USB3_PHY DPLL Sequences
            3. 26.2.4.3.6.3 USB3_PHY DPLL Locked Mode
            4. 26.2.4.3.6.4 USB3_PHY DPLL Idle-Bypass Mode
            5. 26.2.4.3.6.5 USB3_PHY DPLL MN-Bypass Mode
            6. 26.2.4.3.6.6 USB3_PHY DPLL Error Conditions
          7. 26.2.4.3.7 USB3_PHY PLL Controller Functions
            1. 26.2.4.3.7.1 USB3_PHY PLL Controller Register Access
            2. 26.2.4.3.7.2 4331
            3. 26.2.4.3.7.3 USB3_PHY DPLL Clock Programming Sequence
            4. 26.2.4.3.7.4 USB3_PHY DPLL Recommended Values
      5. 26.2.5 USB3_PHY Subsystem Low-Level Programming Model
    3. 26.3 USB3 PHY and SATA PHY Register Manual
      1. 26.3.1 USB3 PHY and SATA PHY Instance Summary
      2. 26.3.2 USB3_PHY_RX Registers
        1. 26.3.2.1 USB3_PHY_RX Register Summary
        2. 26.3.2.2 USB3_PHY_RX Register Description
      3. 26.3.3 USB3_PHY_TX Registers
        1. 26.3.3.1 USB3_PHY_TX Register Summary
        2. 26.3.3.2 USB3_PHY_TX Register Description
      4. 26.3.4 SATA_PHY_RX Registers
        1. 26.3.4.1 SATA_PHY_RX Register Summary
        2. 26.3.4.2 SATA_PHY_RX Register Description
      5. 26.3.5 SATA_PHY_TX Registers
        1. 26.3.5.1 SATA_PHY_TX Register Summary
        2. 26.3.5.2 SATA_PHY_TX Register Description
      6. 26.3.6 DPLLCTRL Registers
        1. 26.3.6.1 DPLLCTRL Register Summary
        2. 26.3.6.2 DPLLCTRL Register Description
    4. 26.4 PCIe PHY Subsystem
      1. 26.4.1 PCIe PHY Subsystem Overview
        1. 26.4.1.1 PCIe PHY Subsystem Key Features
      2. 26.4.2 PCIe PHY Subsystem Environment
        1. 26.4.2.1 PCIe PHY I/O Signals
      3. 26.4.3 PCIe Shared PHY Subsystem Integration
      4. 26.4.4 PCIe PHY Subsystem Functional Description
        1. 26.4.4.1 PCIe PHY Subsystem Block Diagram
        2. 26.4.4.2 OCP2SCP Functional Description
          1. 26.4.4.2.1 OCP2SCP Reset
            1. 26.4.4.2.1.1 Hardware Reset
            2. 26.4.4.2.1.2 Software Reset
          2. 26.4.4.2.2 OCP2SCP Power Management
            1. 26.4.4.2.2.1 Idle Mode
            2. 26.4.4.2.2.2 Clock Gating
          3. 26.4.4.2.3 OCP2SCP Timing Registers
        3. 26.4.4.3 PCIe PHY Serializer and Deserializer Functional Descriptions
          1. 26.4.4.3.1 PCIe PHY Module Resets
            1. 26.4.4.3.1.1 Hardware Reset
            2. 26.4.4.3.1.2 Software Reset
          2. 26.4.4.3.2 PCIe PHY Subsystem Clocking
            1. 26.4.4.3.2.1 PCIe PHY Subsystem Input Clocks
            2. 26.4.4.3.2.2 PCIe PHY Subsystem Output Clocks
          3. 26.4.4.3.3 PCIe PHY Power Management
            1. 26.4.4.3.3.1 PCIe PHY Power-Up/-Down Sequences
            2. 26.4.4.3.3.2 PCIe PHY Low-Power Modes
            3. 26.4.4.3.3.3 Clock Gating
          4. 26.4.4.3.4 PCIe PHY Hardware Requests
        4. 26.4.4.4 PCIe PHY Clock Generator Subsystem Functional Description
          1. 26.4.4.4.1 PCIe PHY DPLL Clock Generator
            1. 26.4.4.4.1.1 PCIe PHY DPLL Clock Generator Overview
            2. 26.4.4.4.1.2 PCIe PHY DPLL Clock Generator Reset
            3. 26.4.4.4.1.3 PCIe PHY DPLL Low-Power Modes
            4. 26.4.4.4.1.4 PCIe PHY DPLL Clocks Configuration
              1. 26.4.4.4.1.4.1 PCIe PHY DPLL Input Clock Control
              2. 26.4.4.4.1.4.2 PCIe PHY DPLL Output Clock Configuration
                1. 26.4.4.4.1.4.2.1 PCIe PHY DPLL Output Clock Gating
            5. 26.4.4.4.1.5 PCIe PHY DPLL Subsystem Architecture
            6. 26.4.4.4.1.6 PCIe PHY DPLL Clock Generator Modes and State Transitions
              1. 26.4.4.4.1.6.1 PCIe PHY Clock Generator Power Up
              2. 26.4.4.4.1.6.2 PCIe PHY DPLL Sequences
              3. 26.4.4.4.1.6.3 PCIe PHY DPLL Locked Mode
              4. 26.4.4.4.1.6.4 PCIe PHY DPLL Idle-Bypass Mode
              5. 26.4.4.4.1.6.5 PCIe PHY DPLL Low Power Stop Mode
              6. 26.4.4.4.1.6.6 PCIe PHY DPLL Clock Programming Sequence
              7. 26.4.4.4.1.6.7 PCIe PHY DPLL Recommended Values
          2. 26.4.4.4.2 PCIe PHY APLL Clock Generator
            1. 26.4.4.4.2.1 PCIe PHY APLL Clock Generator Overview
            2. 26.4.4.4.2.2 PCIe PHY APLL Clock Generator Reset
            3. 26.4.4.4.2.3 PCIe PHY APLL Low-Power Mode
            4. 26.4.4.4.2.4 PCIe PHY APLL Clocks Configuration
              1. 26.4.4.4.2.4.1 PCIe PHY APLL Input Clock Control
              2. 26.4.4.4.2.4.2 PCIe PHY APLL Output Clock Configuration
                1. 26.4.4.4.2.4.2.1 PCIe PHY APLL Output Clock Gating
            5. 26.4.4.4.2.5 PCIe PHY APLL Subsystem Architecture
            6. 26.4.4.4.2.6 PCIe PHY APLL Clock Generator Modes and State Transitions
              1. 26.4.4.4.2.6.1 PCIe PHY APLL Clock Generator Power Up
              2. 26.4.4.4.2.6.2 PCIe PHY APLL Sequences
              3. 26.4.4.4.2.6.3 PCIe PHY APLL Locked Mode
          3. 26.4.4.4.3 ACSPCIE reference clock buffer
      5. 26.4.5 PCIePHY Subsystem Low-Level Programming Model
      6. 26.4.6 PCIe PHY Subsystem Register Manual
        1. 26.4.6.1 PCIe PHY Instance Summary
          1. 26.4.6.1.1 PCIe_PHY_RX Registers
            1. 26.4.6.1.1.1 PCIe_PHY_RX Register Summary
            2. 26.4.6.1.1.2 PCIe_PHY_RX Register Description
          2. 26.4.6.1.2 PCIe_PHY_TX Registers
            1. 26.4.6.1.2.1 PCIe_PHY_TX Register Summary
            2. 26.4.6.1.2.2 PCIe_PHY_TX Register Description
          3. 26.4.6.1.3 OCP2SCP Registers
            1. 26.4.6.1.3.1 OCP2SCP Register Summary
            2. 26.4.6.1.3.2 OCP2SCP Register Description
  29. 27General-Purpose Interface
    1. 27.1 General-Purpose Interface Overview
    2. 27.2 General-Purpose Interface Environment
      1. 27.2.1 General-Purpose Interface as a Keyboard Interface
      2. 27.2.2 General-Purpose Interface Signals
    3. 27.3 General-Purpose Interface Integration
    4. 27.4 General-Purpose Interface Functional Description
      1. 27.4.1 General-Purpose Interface Block Diagram
      2. 27.4.2 General-Purpose Interface Interrupt and Wake-Up Features
        1. 27.4.2.1 Synchronous Path: Interrupt Request Generation
        2. 27.4.2.2 Asynchronous Path: Wake-Up Request Generation
        3. 27.4.2.3 Wake-Up Event Conditions During Transition To/From IDLE State
        4. 27.4.2.4 Interrupt (or Wake-Up) Line Release
      3. 27.4.3 General-Purpose Interface Clock Configuration
        1. 27.4.3.1 Clocking
      4. 27.4.4 General-Purpose Interface Hardware and Software Reset
      5. 27.4.5 General-Purpose Interface Power Management
        1. 27.4.5.1 Power Domain
        2. 27.4.5.2 Power Management
          1. 27.4.5.2.1 Idle Scheme
          2. 27.4.5.2.2 Operating Modes
          3. 27.4.5.2.3 System Power Management and Wakeup
          4. 27.4.5.2.4 Module Power Saving
      6. 27.4.6 General-Purpose Interface Interrupt and Wake-Up Requests
        1. 27.4.6.1 Interrupt Requests Generation
        2. 27.4.6.2 Wake-Up Requests Generation
      7. 27.4.7 General-Purpose Interface Channels Description
      8. 27.4.8 General-Purpose Interface Data Input/Output Capabilities
      9. 27.4.9 General-Purpose Interface Set-and-Clear Protocol
        1. 27.4.9.1 Description
        2. 27.4.9.2 Clear Instruction
          1. 27.4.9.2.1 Clear Register Addresses
          2. 27.4.9.2.2 Clear Instruction Example
        3. 27.4.9.3 Set Instruction
          1. 27.4.9.3.1 Set Register Addresses
          2. 27.4.9.3.2 Set Instruction Example
    5. 27.5 General-Purpose Interface Programming Guide
      1. 27.5.1 General-Purpose Interface Low-Level Programming Models
        1. 27.5.1.1 Global Initialization
          1. 27.5.1.1.1 Surrounding Modules Global Initialization
          2. 27.5.1.1.2 General-Purpose Interface Module Global Initialization
        2. 27.5.1.2 General-Purpose Interface Operational Modes Configuration
          1. 27.5.1.2.1 General-Purpose Interface Read Input Register
          2. 27.5.1.2.2 General-Purpose Interface Set Bit Function
          3. 27.5.1.2.3 General-Purpose Interface Clear Bit Function
    6. 27.6 General-Purpose Interface Register Manual
      1. 27.6.1 General-Purpose Interface Instance Summary
      2. 27.6.2 General-Purpose Interface Registers
        1. 27.6.2.1 General-Purpose Interface Register Summary
        2. 27.6.2.2 General-Purpose Interface Register Description
  30. 28Keyboard Controller
    1. 28.1 Keyboard Controller Overview
    2. 28.2 Keyboard Controller Environment
      1. 28.2.1 Keyboard Controller Functions/Modes
      2. 28.2.2 Keyboard Controller Signals
      3. 28.2.3 Protocols and Data Formats
    3. 28.3 Keyboard Controller Integration
    4. 28.4 Keyboard Controller Functional Description
      1. 28.4.1 Keyboard Controller Block Diagram
      2. 28.4.2 Keyboard Controller Software Reset
      3. 28.4.3 Keyboard Controller Power Management
      4. 28.4.4 Keyboard Controller Interrupt Requests
      5. 28.4.5 Keyboard Controller Software Mode
      6. 28.4.6 Keyboard Controller Hardware Decoding Modes
        1. 28.4.6.1 Functional Modes
        2. 28.4.6.2 Keyboard Controller Timer
        3. 28.4.6.3 State-Machine Status
        4. 28.4.6.4 Keyboard Controller Interrupt Generation
          1. 28.4.6.4.1 Interrupt-Generation Scheme
          2. 28.4.6.4.2 Keyboard Buffer and Missed Events (Overrun Feature)
      7. 28.4.7 Keyboard Controller Key Coding Registers
      8. 28.4.8 Keyboard Controller Register Access
        1. 28.4.8.1 Write Registers Access
        2. 28.4.8.2 Read Registers Access
    5. 28.5 Keyboard Controller Programming Guide
      1. 28.5.1 Keyboard Controller Low-Level Programming Models
        1. 28.5.1.1 Global Initialization
          1. 28.5.1.1.1 Surrounding Modules Global Initialization
          2. 28.5.1.1.2 Keyboard Controller Global Initialization
            1. 28.5.1.1.2.1 Main Sequence – Keyboard Controller Global Initialization
        2. 28.5.1.2 Operational Modes Configuration
          1. 28.5.1.2.1 Keyboard Controller in Hardware Decoding Mode (Default Mode)
            1. 28.5.1.2.1.1 Main Sequence – Keyboard Controller Hardware Mode
          2. 28.5.1.2.2 Keyboard Controller Software Scanning Mode
            1. 28.5.1.2.2.1 Main Sequence – Keyboard Controller Software Mode
          3. 28.5.1.2.3 Using the Timer
          4. 28.5.1.2.4 State-Machine Status Register
        3. 28.5.1.3 Keyboard Controller Events Servicing
    6. 28.6 Keyboard Controller Register Manual
      1. 28.6.1 Keyboard Controller Instance Summary
      2. 28.6.2 Keyboard Controller Registers
        1. 28.6.2.1 Keyboard Controller Register Summary
        2. 28.6.2.2 Keyboard Controller Register Description
  31. 29Pulse-Width Modulation Subsystem
    1. 29.1 PWM Subsystem Resources
      1. 29.1.1 PWMSS Overview
        1. 29.1.1.1 PWMSS Key Features
        2. 29.1.1.2 PWMSS Unsupported Fetaures
      2. 29.1.2 PWMSS Environment
        1. 29.1.2.1 PWMSS I/O Interface
      3. 29.1.3 PWMSS Integration
        1. 29.1.3.1 PWMSS Module Interfaces Implementation
          1. 29.1.3.1.1 Device Specific PWMSS Features
          2. 29.1.3.1.2 Daisy-Chain Connectivity between PWMSS Modules
          3. 29.1.3.1.3 eHRPWM Modules Time Base Clock Gating
      4. 29.1.4 PWMSS Subsystem Power, Reset and Clock Configuration
        1. 29.1.4.1 PWMSS Local Clock Management
        2. 29.1.4.2 PWMSS Modules Local Clock Gating
        3. 29.1.4.3 PWMSS Software Reset
      5. 29.1.5 PWMSS_CFG Register Manual
        1. 29.1.5.1 PWMSS_CFG Instance Summary
        2. 29.1.5.2 PWMSS_CFG Registers
          1. 29.1.5.2.1 PWMSS_CFG Register Summary
          2. 29.1.5.2.2 PWMSS_CFG Register Description
    2. 29.2 Enhanced PWM (ePWM) Module
    3. 29.3 Enhanced Capture (eCAP) Module
    4. 29.4 Enhanced Quadrature Encoder Pulse (eQEP) Module
  32. 30Viterbi-Decoder Coprocessor
    1. 30.1 VCP Overview
      1. 30.1.1 VCP Features
    2. 30.2 VCP Integration
    3. 30.3 VCP Functional Description
      1. 30.3.1  VCP Block Diagram
      2. 30.3.2  VCP Internal Interfaces
        1. 30.3.2.1 VCP Power Management
          1. 30.3.2.1.1 Idle Mode
        2. 30.3.2.2 VCP Clocks
        3. 30.3.2.3 VCP Resets
        4. 30.3.2.4 Interrupt Requests
        5. 30.3.2.5 EDMA Requests
      3. 30.3.3  Functional Overview
        1. 30.3.3.1 Theoretical Basics of the Convolutional Code.
        2. 30.3.3.2 4556
      4. 30.3.4  VCP Architecture
        1. 30.3.4.1 Sliding Windows Processing
          1. 30.3.4.1.1 Tailed Traceback Mode
          2. 30.3.4.1.2 Mixed Traceback Mode
          3. 30.3.4.1.3 Convergent Traceback Mode
          4. 30.3.4.1.4 F, R, and C Limitations
          5. 30.3.4.1.5 Yamamoto Parameters
          6. 30.3.4.1.6 Input FIFO (Branch Metrics)
          7. 30.3.4.1.7 Output FIFO (Decisions)
      5. 30.3.5  VCP Input Data
        1. 30.3.5.1 Branch Metrics Calculations
      6. 30.3.6  Soft Input Dynamic Ranges
      7. 30.3.7  VCP Memory Sleep Mode
      8. 30.3.8  Decision Data
      9. 30.3.9  Endianness
        1. 30.3.9.1 Branch Metrics
          1. 30.3.9.1.1 Hard Decisions
          2. 30.3.9.1.2 Soft Decisions
      10. 30.3.10 VCP Output Parameters
      11. 30.3.11 Event Generation
        1. 30.3.11.1 VCPnXEVT Generation
        2. 30.3.11.2 VCPnREVT Generation
      12. 30.3.12 Operational Modes
        1. 30.3.12.1 Debugging Features
      13. 30.3.13 Errors and Status
    4. 30.4 VCP Modules Programming Guide
      1. 30.4.1 EDMA Resources
        1. 30.4.1.1 VCP1 and VCP2 Dedicated EDMA Resources
        2. 30.4.1.2 Special VCP EDMA Programming Considerations
          1. 30.4.1.2.1 Input Configuration Parameters Transfer
          2. 30.4.1.2.2 Branch Metrics Transfer
          3. 30.4.1.2.3 Decisions Transfer
          4. 30.4.1.2.4 Hard-Decisions Mode
          5. 30.4.1.2.5 Soft-Decisions Mode
          6. 30.4.1.2.6 Output Parameters Transfer
      2. 30.4.2 Input Configuration Words
    5. 30.5 VCP Register Manual
      1. 30.5.1 VCP1 and VCP2 Instance Summary
      2. 30.5.2 VCP Registers
        1. 30.5.2.1 VCP Register Summary
        2. 30.5.2.2 VCP1 and VCP2 Data Registers Description
        3. 30.5.2.3 VCP1 and VCP2 Configuration Registers Description
  33. 31Audio Tracking Logic
    1. 31.1 ATL Overview
    2. 31.2 ATL Environment
      1. 31.2.1 ATL Functions
      2. 31.2.2 ATL Signals Descriptions
    3. 31.3 ATL Integration
      1. 31.3.1 ATL Distribution on Interconnects
      2. 31.3.2 ATL Regions Allocations
    4. 31.4 ATL Functional Description
      1. 31.4.1 Block Diagram
      2. 31.4.2 Source Signal Control
      3. 31.4.3 ATL Clock and Reset Configuration
    5. 31.5 ATL Register Manual
      1. 31.5.1 ATL Instance Summary
      2. 31.5.2 ATL Register Summary
      3. 31.5.3 ATL Register Description
  34. 32Initialization
    1. 32.1 Initialization Overview
      1. 32.1.1 Terminology
      2. 32.1.2 Initialization Process
    2. 32.2 Preinitialization
      1. 32.2.1 Power Requirements
      2. 32.2.2 Interaction With the PMIC Companion
      3. 32.2.3 Clock, Reset, and Control
        1. 32.2.3.1 Overview
        2. 32.2.3.2 Clocking Scheme
        3. 32.2.3.3 Reset Configuration
          1. 32.2.3.3.1 ON/OFF Interconnect and Power-On-Reset
          2. 32.2.3.3.2 Warm Reset
          3. 32.2.3.3.3 Peripheral Reset by GPIO
          4. 32.2.3.3.4 Warm Reset Impact on GPIOs
        4. 32.2.3.4 PMIC Control
        5. 32.2.3.5 PMIC Request Signals
      4. 32.2.4 Sysboot Configuration
        1. 32.2.4.1 GPMC Configuration for XIP/NAND
        2. 32.2.4.2 System Clock Speed Selection
        3. 32.2.4.3 QSPI Redundant SBL Images Offset
        4. 32.2.4.4 Booting Device Order Selection
        5. 32.2.4.5 4637
        6. 32.2.4.6 Boot Peripheral Pin Multiplexing
    3. 32.3 Device Initialization by ROM Code
      1. 32.3.1 Booting Overview
        1. 32.3.1.1 Booting Types
        2. 32.3.1.2 ROM Code Architecture
      2. 32.3.2 Memory Maps
        1. 32.3.2.1 ROM Memory Map
        2. 32.3.2.2 RAM Memory Map
      3. 32.3.3 Overall Booting Sequence
      4. 32.3.4 Startup and Configuration
        1. 32.3.4.1 Startup
        2. 32.3.4.2 Control Module Configuration
        3. 32.3.4.3 PRCM Module Mode Configuration
        4. 32.3.4.4 Clocking Configuration
        5. 32.3.4.5 Booting Device List Setup
      5. 32.3.5 Peripheral Booting
        1. 32.3.5.1 Description
        2. 32.3.5.2 Initialization Phase for UART Boot
        3. 32.3.5.3 Initialization Phase for USB Boot
          1. 32.3.5.3.1 Initialization Procedure
          2. 32.3.5.3.2 SATA Peripheral Device Flashing over USB Interface
          3. 32.3.5.3.3 USB Driver Descriptors
          4. 32.3.5.3.4 4660
          5. 32.3.5.3.5 USB Customized Vendor and Product IDs
          6. 32.3.5.3.6 USB Driver Functionality
      6. 32.3.6 Fast External Booting
        1. 32.3.6.1 Overview
        2. 32.3.6.2 Fast External Booting Procedure
      7. 32.3.7 Memory Booting
        1. 32.3.7.1 Overview
        2. 32.3.7.2 Non-XIP Memory
        3. 32.3.7.3 XIP Memory
          1. 32.3.7.3.1 GPMC Initialization
        4. 32.3.7.4 NAND
          1. 32.3.7.4.1 Initialization and NAND Detection
          2. 32.3.7.4.2 NAND Read Sector Procedure
        5. 32.3.7.5 SPI/QSPI Flash Devices
        6. 32.3.7.6 eMMC Memories and SD Cards
          1. 32.3.7.6.1 eMMC Memories
            1. 32.3.7.6.1.1 System Conditions and Limitations
            2. 32.3.7.6.1.2 eMMC Memory Connection
          2. 32.3.7.6.2 SD Cards
            1. 32.3.7.6.2.1 System Conditions and Limitations
            2. 32.3.7.6.2.2 SD Card Connection
            3. 32.3.7.6.2.3 Booting Procedure
            4. 32.3.7.6.2.4 eMMC Partitions Handling in Alternative Boot Operation Mode
              1. 32.3.7.6.2.4.1 eMMC Devices Preflashing
              2. 32.3.7.6.2.4.2 eMMC Device State After ROM Code Execution
              3. 32.3.7.6.2.4.3 Consideration on device Global Warm Reset
              4. 32.3.7.6.2.4.4 Booting Image Size
              5. 32.3.7.6.2.4.5 Booting Image Layout
          3. 32.3.7.6.3 Initialization and Detection
          4. 32.3.7.6.4 Read Sector Procedure
          5. 32.3.7.6.5 File System Handling
            1. 32.3.7.6.5.1 MBR and FAT File System
        7. 32.3.7.7 SATA Device Boot Operation
          1. 32.3.7.7.1 SATA Booting Overview
          2. 32.3.7.7.2 SATA Power-Up Initialization Sequence
          3. 32.3.7.7.3 System Conditions and Limitations for SATA Boot
          4. 32.3.7.7.4 SATA Read Sector Procedure in FAT Mode
      8. 32.3.8 Image Format
        1. 32.3.8.1 Overview
        2. 32.3.8.2 Configuration Header
          1. 32.3.8.2.1 CHSETTINGS Item
          2. 32.3.8.2.2 CHFLASH Item
          3. 32.3.8.2.3 CHMMCSD Item
          4. 32.3.8.2.4 CHQSPI Item
        3. 32.3.8.3 GP Header
        4. 32.3.8.4 Image Execution
      9. 32.3.9 Tracing
    4. 32.4 Services for HLOS Support
      1. 32.4.1 Hypervisor
      2. 32.4.2 Caches Maintenance
      3. 32.4.3 CP15 Registers
      4. 32.4.4 Wakeup Generator
      5. 32.4.5 Arm Timer
  35. 33On-Chip Debug Support
    1. 33.1  Introduction
      1. 33.1.1 Key Features
    2. 33.2  Debug Interfaces
      1. 33.2.1 IEEE1149.1
      2. 33.2.2 Debug (Trace) Port
      3. 33.2.3 Trace Connector and Board Layout Considerations
    3. 33.3  Debugger Connection
      1. 33.3.1 ICEPick Module
      2. 33.3.2 ICEPick Boot Modes
        1. 33.3.2.1 Default Boot Mode
        2. 33.3.2.2 Wait-In-Reset
      3. 33.3.3 Dynamic TAP Insertion
        1. 33.3.3.1 ICEPick Secondary TAPs
    4. 33.4  Primary Debug Support
      1. 33.4.1 Processor Native Debug Support
        1. 33.4.1.1 Cortex-A15 Processor
        2. 33.4.1.2 Cortex-M4 Processor
        3. 33.4.1.3 DSP C66x
        4. 33.4.1.4 IVA Arm968
        5. 33.4.1.5 ARP32
        6. 33.4.1.6 4735
      2. 33.4.2 Cross-Triggering
        1. 33.4.2.1 SoC-Level Cross-Triggering
        2. 33.4.2.2 Cross-Triggering With External Device
      3. 33.4.3 Suspend
        1. 33.4.3.1 Debug Aware Peripherals and Host Processors
    5. 33.5  Real-Time Debug
      1. 33.5.1 Real-Time Debug Events
        1. 33.5.1.1 Emulation Interrupts
    6. 33.6  Power, Reset, and Clock Management Debug Support
      1. 33.6.1 Power and Clock Management
        1. 33.6.1.1 Power and Clock Control Override From Debugger
          1. 33.6.1.1.1 Debugger Directives
            1. 33.6.1.1.1.1 FORCEACTIVE Debugger Directive
            2. 33.6.1.1.1.2 INHIBITSLEEP Debugger Directive
          2. 33.6.1.1.2 Intrusive Debug Model
        2. 33.6.1.2 Debug Across Power Transition
          1. 33.6.1.2.1 Nonintrusive Debug Model
          2. 33.6.1.2.2 Debug Context Save and Restore
            1. 33.6.1.2.2.1 Debug Context Save
            2. 33.6.1.2.2.2 Debug Context Restore
      2. 33.6.2 Reset Management
        1. 33.6.2.1 Debugger Directives
          1. 33.6.2.1.1 Assert Reset
          2. 33.6.2.1.2 Block Reset
          3. 33.6.2.1.3 Wait-In-Reset
    7. 33.7  Performance Monitoring
      1. 33.7.1 MPU Subsystem Performance Monitoring
        1. 33.7.1.1 Performance Monitoring Unit
        2. 33.7.1.2 L2 Cache Controller
      2. 33.7.2 IPU Subsystem Performance Monitoring
        1. 33.7.2.1 Subsystem Counter Timer Module
        2. 33.7.2.2 Cache Events
      3. 33.7.3 DSP Subsystem Performance Monitoring
        1. 33.7.3.1 Advanced Event Triggering
      4. 33.7.4 EVE Subsystem Performance Monitoring
        1. 33.7.4.1 EVE Subsystem Counter Timer Module
        2. 33.7.4.2 EVE Subsystem SCTM Events
    8. 33.8  MPU Memory Adaptor (MPU_MA) Watchpoint
    9. 33.9  Processor Trace
      1. 33.9.1 Cortex-A15 Processor Trace
      2. 33.9.2 DSP Processor Trace
      3. 33.9.3 Trace Export
        1. 33.9.3.1 Trace Exported to External Trace Receiver
        2. 33.9.3.2 Trace Captured Into On-Chip Trace Buffer
        3. 33.9.3.3 Trace Exported Through USB
    10. 33.10 System Instrumentation
      1. 33.10.1  MIPI STM (CT_STM)
      2. 33.10.2  System Trace Export
        1. 33.10.2.1 CT_STM ATB Export
        2. 33.10.2.2 Trace Streams Interleaving
      3. 33.10.3  Software Instrumentation
        1. 33.10.3.1 MPU Software Instrumentation
        2. 33.10.3.2 SoC Software Instrumentation
      4. 33.10.4  OCP Watchpoint
        1. 33.10.4.1 OCP Target Traffic Monitoring
        2. 33.10.4.2 Messages Triggered from System Events
        3. 33.10.4.3 DMA Transfer Profiling
      5. 33.10.5  IVA Pipeline
      6. 33.10.6  EVE SMSET
      7. 33.10.7  L3 NOC Statistics Collector
        1. 33.10.7.1 L3 Target Load Monitoring
        2. 33.10.7.2 L3 Master Latency Monitoring
          1. 33.10.7.2.1  SC_LAT0 Configuration
          2. 33.10.7.2.2  SC_LAT1 Configuration
          3. 33.10.7.2.3  SC_LAT2 Configuration
          4. 33.10.7.2.4  SC_LAT3 Configuration
          5. 33.10.7.2.5  SC_LAT4 Configuration
          6. 33.10.7.2.6  SC_LAT5 Configuration
          7. 33.10.7.2.7  SC_LAT6 Configuration
          8. 33.10.7.2.8  SC_LAT7 Configuration
          9. 33.10.7.2.9  SC_LAT8 Configuration
          10. 33.10.7.2.10 Statistics Collector Alarm Mode
          11. 33.10.7.2.11 Statistics Collector Suspend Mode
      8. 33.10.8  PM Instrumentation
      9. 33.10.9  CM Instrumentation
      10. 33.10.10 Master-ID Encoding
        1. 33.10.10.1 Software Masters
        2. 33.10.10.2 Hardware Masters
    11. 33.11 Concurrent Debug Modes
    12. 33.12 DRM Register Manual
      1. 33.12.1 DRM Instance Summary
      2. 33.12.2 DRM Registers
        1. 33.12.2.1 DRM Register Summary
        2. 33.12.2.2 DRM Register Description
  36. 34Glossary
  37. 35Revision History

18.5 Control Module Register Manual

18.5.1 Control Module Instance Summary

Table 18-27 CONTROL MODULE Instance Summary
Module NameModule Base AddressSize
CTRL_MODULE_CORE0x4A00 20008 KiB
CTRL_MODULE_WKUP0x4AE0 C0004 KiB

18.5.2 CTRL_MODULE_CORE Registers

18.5.3 CTRL_MODULE_CORE Register Summary

Table 18-28 CTRL_MODULE_CORE Registers Mapping Summary
Register NameTypeRegister Width (Bits)Address OffsetCTRL_MODULE_CORE Base Address
RESERVED_k (k = 0 to 76)R320x0000 0000 + (k*4)0x4A00 2000 + (k*4)
CTRL_CORE_STATUSR320x0000 01340x4A00 2134
RESERVEDR320x0000 01380x4A00 2138
RESERVEDR320x0000 013C0x4A00 213C
RESERVEDR320x0000 01400x4A00 2140
RESERVEDR320x0000 01440x4A00 2144
CTRL_CORE_SEC_ERR_STATUS_FUNC_1RW320x0000 01480x4A00 2148
RESERVEDR320x0000 014C0x4A00 214C
CTRL_CORE_SEC_ERR_STATUS_DEBUG_1RW320x0000 01500x4A00 2150
RESERVEDR320x0000 01540x4A00 2154
RESERVEDR320x0000 01580x4A00 2158
CTRL_CORE_MPU_FORCEWRNPRW320x0000 015C0x4A00 215C
RESERVEDR320x0000 01600x4A00 2160
RESERVEDR320x0000 01640x4A00 2164
RESERVEDR320x0000 01680x4A00 2168
RESERVEDR320x0000 016C0x4A00 216C
RESERVEDR320x0000 01700x4A00 2170
RESERVEDR320x0000 01740x4A00 2174
RESERVEDR320x0000 01780x4A00 2178
RESERVEDR320x0000 017C0x4A00 217C
RESERVEDR320x0000 01800x4A00 2180
RESERVEDR320x0000 01840x4A00 2184
RESERVEDR320x0000 01880x4A00 2188
RESERVEDR320x0000 018C0x4A00 218C
RESERVEDR320x0000 01900x4A00 2190
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0R320x0000 01940x4A00 2194
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1R320x0000 01980x4A00 2198
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2R320x0000 019C0x4A00 219C
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3R320x0000 01A00x4A00 21A0
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4R320x0000 01A40x4A00 21A4
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5R320x0000 01A80x4A00 21A8
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0R320x0000 01AC0x4A00 21AC
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1R320x0000 01B00x4A00 21B0
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2R320x0000 01B40x4A00 21B4
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3R320x0000 01B80x4A00 21B8
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4R320x0000 01BC0x4A00 21BC
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5R320x0000 01C00x4A00 21C0
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6R320x0000 01C40x4A00 21C4
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7R320x0000 01C80x4A00 21C8
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0R320x0000 01CC0x4A00 21CC
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1R320x0000 01D00x4A00 21D0
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2R320x0000 01D40x4A00 21D4
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3R320x0000 01D80x4A00 21D8
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4R320x0000 01DC0x4A00 21DC
CTRL_CORE_STD_FUSE_OPP_BGAP_GPUR320x0000 01E00x4A00 21E0
CTRL_CORE_STD_FUSE_OPP_BGAP_MPUR320x0000 01E40x4A00 21E4
CTRL_CORE_STD_FUSE_OPP_BGAP_CORER320x0000 01E80x4A00 21E8
CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23R320x0000 01EC0x4A00 21EC
RESERVED_x (x = 0 to 11)R320x0000 01F00x4A00 21F0
CTRL_CORE_STD_FUSE_MPK_0R320x0000 02200x4A00 2220
CTRL_CORE_STD_FUSE_MPK_1R320x0000 02240x4A00 2224
CTRL_CORE_STD_FUSE_MPK_2R320x0000 02280x4A00 2228
CTRL_CORE_STD_FUSE_MPK_3R320x0000 022C0x4A00 222C
CTRL_CORE_STD_FUSE_MPK_4R320x0000 02300x4A00 2230
CTRL_CORE_STD_FUSE_MPK_5R320x0000 02340x4A00 2234
CTRL_CORE_STD_FUSE_MPK_6R320x0000 02380x4A00 2238
CTRL_CORE_STD_FUSE_MPK_7R320x0000 023C0x4A00 223C
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0R320x0000 02400x4A00 2240
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1R320x0000 02440x4A00 2244
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2R320x0000 02480x4A00 2248
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3R320x0000 024C0x4A00 224C
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4R320x0000 02500x4A00 2250
CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5R320x0000 02540x4A00 2254
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0R320x0000 02580x4A00 2258
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1R320x0000 025C0x4A00 225C
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2R320x0000 02600x4A00 2260
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3R320x0000 02640x4A00 2264
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4R320x0000 02680x4A00 2268
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5R320x0000 026C0x4A00 226C
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6R320x0000 02700x4A00 2270
CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7R320x0000 02740x4A00 2274
RESERVED_v (v = 0 to 16)R320x0000 0278 + (v*4)0x4A00 2278 + (v*4)
CTRL_CORE_CUST_FUSE_SWRV_0R320x0000 02BC0x4A00 22BC
CTRL_CORE_CUST_FUSE_SWRV_1R320x0000 02C00x4A00 22C0
CTRL_CORE_CUST_FUSE_SWRV_2R320x0000 02C40x4A00 22C4
CTRL_CORE_CUST_FUSE_SWRV_3R320x0000 02C80x4A00 22C8
CTRL_CORE_CUST_FUSE_SWRV_4R320x0000 02CC0x4A00 22CC
CTRL_CORE_CUST_FUSE_SWRV_5R320x0000 02D00x4A00 22D0
CTRL_CORE_CUST_FUSE_SWRV_6R320x0000 02D40x4A00 22D4
RESERVEDR320x0000 02D80x4A00 22D8
RESERVEDR320x0000 02DC0x4A00 22DC
RESERVEDR320x0000 02E00x4A00 22E0
RESERVEDR320x0000 02E40x4A00 22E4
RESERVEDR320x0000 02E80x4A00 22E8
RESERVEDR320x0000 02EC0x4A00 22EC
CTRL_CORE_DEV_CONFRW320x0000 03000x4A00 2300
RESERVEDR320x0000 03040x4A00 2304
CTRL_CORE_TEMP_SENSOR_MPUR320x0000 032C0x4A00 232C
CTRL_CORE_TEMP_SENSOR_GPUR320x0000 03300x4A00 2330
CTRL_CORE_TEMP_SENSOR_CORER320x0000 03340x4A00 2334
RESERVEDR320x0000 033C0x4A00 233C
RESERVEDR320x0000 03400x4A00 2340
RESERVEDR320x0000 03440x4A00 2344
CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTRRW320x0000 03580x4A00 2358
CTRL_CORE_CORTEX_M4_MMUADDRLOGICTRRW320x0000 035C0x4A00 235C
CTRL_CORE_HWOBS_CONTROLRW320x0000 03600x4A00 2360
RESERVED R320x0000 03640x4A00 2364
RESERVED R320x0000 03680x4A00 2368
RESERVEDR320x0000 036C0x4A00 236C
CTRL_CORE_PHY_POWER_USBRW320x0000 03700x4A00 2370
CTRL_CORE_PHY_POWER_SATARW320x0000 03740x4A00 2374
CTRL_CORE_BANDGAP_MASK_1RW320x0000 03800x4A00 2380
CTRL_CORE_BANDGAP_THRESHOLD_MPURW320x0000 03840x4A00 2384
CTRL_CORE_BANDGAP_THRESHOLD_GPURW320x0000 03880x4A00 2388
CTRL_CORE_BANDGAP_THRESHOLD_CORERW320x0000 038C0x4A00 238C
CTRL_CORE_BANDGAP_TSHUT_MPURW320x0000 03900x4A00 2390
CTRL_CORE_BANDGAP_TSHUT_GPURW320x0000 03940x4A00 2394
CTRL_CORE_BANDGAP_TSHUT_CORERW320x0000 03980x4A00 2398
RESERVEDR320x0000 039C0x4A00 239C
RESERVEDR320x0000 03A00x4A00 23A0
RESERVEDR320x0000 03A40x4A00 23A4
CTRL_CORE_BANDGAP_STATUS_1R320x0000 03A80x4A00 23A8
CTRL_CORE_SATA_EXT_MODERW320x0000 03AC0x4A00 23AC
RESERVEDR320x0000 03B00x4A00 23B0
RESERVEDR320x0000 03B40x4A00 23B4
RESERVEDR320x0000 03B80x4A00 23B8
RESERVEDR320x0000 03BC0x4A00 23BC
CTRL_CORE_DTEMP_MPU_0R320x0000 03C00x4A00 23C0
CTRL_CORE_DTEMP_MPU_1R320x0000 03C40x4A00 23C4
CTRL_CORE_DTEMP_MPU_2R320x0000 03C80x4A00 23C8
CTRL_CORE_DTEMP_MPU_3R320x0000 03CC0x4A00 23CC
CTRL_CORE_DTEMP_MPU_4R320x0000 03D00x4A00 23D0
CTRL_CORE_DTEMP_GPU_0R320x0000 03D40x4A00 23D4
CTRL_CORE_DTEMP_GPU_1R320x0000 03D80x4A00 23D8
CTRL_CORE_DTEMP_GPU_2R320x0000 03DC0x4A00 23DC
CTRL_CORE_DTEMP_GPU_3R320x0000 03E00x4A00 23E0
CTRL_CORE_DTEMP_GPU_4R320x0000 03E40x4A00 23E4
CTRL_CORE_DTEMP_CORE_0R320x0000 03E80x4A00 23E8
CTRL_CORE_DTEMP_CORE_1R320x0000 03EC0x4A00 23EC
CTRL_CORE_DTEMP_CORE_2R320x0000 03F00x4A00 23F0
CTRL_CORE_DTEMP_CORE_3R320x0000 03F40x4A00 23F4
CTRL_CORE_DTEMP_CORE_4R320x0000 03F80x4A00 23F8
CTRL_CORE_SMA_SW_0RW320x0000 03FC0x4A00 23FC
RESERVEDR320x0000 04000x4A00 2400
RESERVEDR320x0000 04040x4A00 2404
RESERVEDR320x0000 04080x4A00 2408
RESERVEDR320x0000 040C0x4A00 240C
CTRL_CORE_SEC_ERR_STATUS_FUNC_2RW320x0000 04140x4A00 2414
RESERVEDR320x0000 04180x4A00 2418
CTRL_CORE_SEC_ERR_STATUS_DEBUG_2RW320x0000 041C0x4A00 241C
CTRL_CORE_EMIF_INITIATOR_PRIORITY_1RW320x0000 04200x4A00 2420
CTRL_CORE_EMIF_INITIATOR_PRIORITY_2RW320x0000 04240x4A00 2424
CTRL_CORE_EMIF_INITIATOR_PRIORITY_3RW320x0000 04280x4A00 2428
CTRL_CORE_EMIF_INITIATOR_PRIORITY_4RW320x0000 042C0x4A00 242C
CTRL_CORE_EMIF_INITIATOR_PRIORITY_5RW320x0000 04300x4A00 2430
CTRL_CORE_EMIF_INITIATOR_PRIORITY_6RW320x0000 04340x4A00 2434
RESERVEDR320x0000 04380x4A00 2438
CTRL_CORE_L3_INITIATOR_PRESSURE_1RW320x0000 043C0x4A00 243C
CTRL_CORE_L3_INITIATOR_PRESSURE_2RW320x0000 04400x4A00 2440
RESERVEDR320x0000 04440x4A00 2444
CTRL_CORE_L3_INITIATOR_PRESSURE_4RW320x0000 04480x4A00 2448
CTRL_CORE_L3_INITIATOR_PRESSURE_5RW320x0000 044C0x4A00 244C
CTRL_CORE_L3_INITIATOR_PRESSURE_6RW320x0000 04500x4A00 2450
RESERVEDR320x0000 04540x4A00 2454
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0R320x0000 04580x4A00 2458
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1R320x0000 045C0x4A00 245C
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2R320x0000 04600x4A00 2460
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3R320x0000 04640x4A00 2464
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4R320x0000 04680x4A00 2468
CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRLRW320x0000 046C0x4A00 246C
CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRLRW320x0000 04700x4A00 2470
RESERVED_c (c = 0 to 28)R320x0000 0474 + (c*4)0x4A00 2474 + (c*4)
CTRL_CORE_CUST_FUSE_UID_0R320x0000 04E80x4A00 24E8
CTRL_CORE_CUST_FUSE_UID_1R320x0000 04EC0x4A00 24EC
CTRL_CORE_CUST_FUSE_UID_2R320x0000 04F00x4A00 24F0
CTRL_CORE_CUST_FUSE_UID_3R320x0000 04F40x4A00 24F4
CTRL_CORE_CUST_FUSE_UID_4R320x0000 04F80x4A00 24F8
CTRL_CORE_CUST_FUSE_UID_5R320x0000 04FC0x4A00 24FC
CTRL_CORE_CUST_FUSE_UID_6R320x0000 05000x4A00 2500
RESERVEDR320x0000 05040x4A00 2504
CTRL_CORE_CUST_FUSE_PCIE_ID_0R320x0000 05080x4A00 2508
RESERVEDR320x0000 050C0x4A00 250C
CTRL_CORE_CUST_FUSE_USB_ID_0R320x0000 05100x4A00 2510
CTRL_CORE_MAC_ID_SW_0R320x0000 05140x4A00 2514
CTRL_CORE_MAC_ID_SW_1R320x0000 05180x4A00 2518
CTRL_CORE_MAC_ID_SW_2R320x0000 051C0x4A00 251C
CTRL_CORE_MAC_ID_SW_3R320x0000 05200x4A00 2520
RESERVED_d (d = 0 to 3)R320x0000 0524 + (d*4)0x4A00 2524 + (d*4)
CTRL_CORE_SMA_SW_1RW320x0000 05340x4A00 2534
CTRL_CORE_DSS_PLL_CONTROLRW320x0000 05380x4A00 2538
RESERVEDR320x0000 053C0x4A00 253C
CTRL_CORE_MMR_LOCK_1RW320x0000 05400x4A00 2540
CTRL_CORE_MMR_LOCK_2RW320x0000 05440x4A00 2544
CTRL_CORE_MMR_LOCK_3RW320x0000 05480x4A00 2548
CTRL_CORE_MMR_LOCK_4RW320x0000 054C0x4A00 254C
CTRL_CORE_MMR_LOCK_5RW320x0000 05500x4A00 2550
CTRL_CORE_CONTROL_IO_1RW320x0000 05540x4A00 2554
CTRL_CORE_CONTROL_IO_2RW320x0000 05580x4A00 2558
CTRL_CORE_CONTROL_DSP1_RST_VECTRW320x0000 055C0x4A00 255C
CTRL_CORE_CONTROL_DSP2_RST_VECTRW320x0000 05600x4A00 2560
CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVER320x0000 05640x4A00 2564
CTRL_CORE_STD_FUSE_OPP_BGAP_IVAR320x0000 05680x4A00 2568
CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRLRW320x0000 056C0x4A00 256C
CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRLRW320x0000 05700x4A00 2570
CTRL_CORE_TEMP_SENSOR_DSPEVER320x0000 05740x4A00 2574
CTRL_CORE_TEMP_SENSOR_IVAR320x0000 05780x4A00 2578
CTRL_CORE_BANDGAP_MASK_2RW320x0000 057C0x4A00 257C
CTRL_CORE_BANDGAP_THRESHOLD_DSPEVERW320x0000 05800x4A00 2580
CTRL_CORE_BANDGAP_THRESHOLD_IVARW320x0000 05840x4A00 2584
CTRL_CORE_BANDGAP_TSHUT_DSPEVERW320x0000 05880x4A00 2588
CTRL_CORE_BANDGAP_TSHUT_IVARW320x0000 058C0x4A00 258C
RESERVEDR320x0000 05900x4A00 2590
RESERVEDR320x0000 05940x4A00 2594
CTRL_CORE_BANDGAP_STATUS_2R320x0000 05980x4A00 2598
CTRL_CORE_DTEMP_DSPEVE_0R320x0000 059C0x4A00 259C
CTRL_CORE_DTEMP_DSPEVE_1R320x0000 05A00x4A00 25A0
CTRL_CORE_DTEMP_DSPEVE_2R320x0000 05A40x4A00 25A4
CTRL_CORE_DTEMP_DSPEVE_3R320x0000 05A80x4A00 25A8
CTRL_CORE_DTEMP_DSPEVE_4R320x0000 05AC0x4A00 25AC
CTRL_CORE_DTEMP_IVA_0R320x0000 05B00x4A00 25B0
CTRL_CORE_DTEMP_IVA_1R320x0000 05B40x4A00 25B4
CTRL_CORE_DTEMP_IVA_2R320x0000 05B80x4A00 25B8
CTRL_CORE_DTEMP_IVA_3R320x0000 05BC0x4A00 25BC
CTRL_CORE_DTEMP_IVA_4R320x0000 05C00x4A00 25C0
CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_5R320x0000 05C40x4A00 25C4
RESERVEDR320x0000 05C80x4A00 25C8
CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2R320x0000 05CC0x4A00 25CC
CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3R320x0000 05D00x4A00 25D0
CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4R320x0000 05D40x4A00 25D4
CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_5R320x0000 05D80x4A00 25D8
RESERVEDR320x0000 05DC0x4A00 25DC
CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2R320x0000 05E00x4A00 25E0
CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3R320x0000 05E40x4A00 25E4
CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4R320x0000 05E80x4A00 25E8
RESERVEDR320x0000 05EC0x4A00 25EC
RESERVEDR320x0000 05F00x4A00 25F0
CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2R320x0000 05F40x4A00 25F4
RESERVEDR320x0000 05F80x4A00 25F8
RESERVEDR320x0000 05FC0x4A00 25FC
RESERVED_m (m = 0 to 31)R320x0000 0600 + (m*4)0x4A00 2600 + (m*4)
CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRLRW320x0000 06800x4A00 2680
CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRLRW320x0000 06840x4A00 2684
RESERVEDR320x0000 06880x4A00 2688
CTRL_CORE_NMI_DESTINATION_1RW320x0000 068C0x4A00 268C
CTRL_CORE_NMI_DESTINATION_2RW320x0000 06900x4A00 2690
RESERVEDR320x0000 06940x4A00 2694
CTRL_CORE_IP_PRESSURERW320x0000 06980x4A00 2698
RESERVEDR320x0000 069C0x4A00 269C
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0R320x0000 06A00x4A00 26A0
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1R320x0000 06A40x4A00 26A4
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2R320x0000 06A80x4A00 26A8
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3R320x0000 06AC0x4A00 26AC
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4R320x0000 06B00x4A00 26B0
CTRL_CORE_CUST_FUSE_SWRV_7R320x0000 06B40x4A00 26B4
CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0R320x0000 06B80x4A00 26B8
CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1R320x0000 06BC0x4A00 26BC
CTRL_CORE_PCIE_POWER_STATERW320x0000 06C00x4A00 26C0
CTRL_CORE_BOOTSTRAPR320x0000 06C40x4A00 26C4
CTRL_CORE_MLB_SIG_IO_CTRLRW320x0000 06C80x4A00 26C8
CTRL_CORE_MLB_DAT_IO_CTRLRW320x0000 06CC0x4A00 26CC
CTRL_CORE_MLB_CLK_BG_CTRLRW320x0000 06D00x4A00 26D0
RESERVED_n (n = 0 to 48)R320x0000 06DC + (n*4)0x4A00 26DC + (n*4)
CTRL_CORE_EVE1_IRQ_0_1RW320x0000 07A00x4A00 27A0
CTRL_CORE_EVE1_IRQ_2_3RW320x0000 07A40x4A00 27A4
CTRL_CORE_EVE1_IRQ_4_5RW320x0000 07A80x4A00 27A8
CTRL_CORE_EVE1_IRQ_6_7RW320x0000 07AC0x4A00 27AC
CTRL_CORE_EVE2_IRQ_0_1RW320x0000 07B00x4A00 27B0
CTRL_CORE_EVE2_IRQ_2_3RW320x0000 07B40x4A00 27B4
CTRL_CORE_EVE2_IRQ_4_5RW320x0000 07B80x4A00 27B8
CTRL_CORE_EVE2_IRQ_6_7RW320x0000 07BC0x4A00 27BC
RESERVEDR320x0000 07C00x4A00 27C0
RESERVEDR320x0000 07C40x4A00 27C4
RESERVEDR320x0000 07C80x4A00 27C8
RESERVEDR320x0000 07CC0x4A00 27CC
RESERVEDR320x0000 07D00x4A00 27D0
RESERVEDR320x0000 07D40x4A00 27D4
RESERVEDR320x0000 07D80x4A00 27D8
RESERVEDR320x0000 07DC0x4A00 27DC
CTRL_CORE_IPU1_IRQ_23_24RW320x0000 07E00x4A00 27E0
CTRL_CORE_IPU1_IRQ_25_26RW320x0000 07E40x4A00 27E4
CTRL_CORE_IPU1_IRQ_27_28RW320x0000 07E80x4A00 27E8
CTRL_CORE_IPU1_IRQ_29_30RW320x0000 07EC0x4A00 27EC
CTRL_CORE_IPU1_IRQ_31_32RW320x0000 07F00x4A00 27F0
CTRL_CORE_IPU1_IRQ_33_34RW320x0000 07F40x4A00 27F4
CTRL_CORE_IPU1_IRQ_35_36RW320x0000 07F80x4A00 27F8
CTRL_CORE_IPU1_IRQ_37_38RW320x0000 07FC0x4A00 27FC
CTRL_CORE_IPU1_IRQ_39_40RW320x0000 08000x4A00 2800
CTRL_CORE_IPU1_IRQ_41_42RW320x0000 08040x4A00 2804
CTRL_CORE_IPU1_IRQ_43_44RW320x0000 08080x4A00 2808
CTRL_CORE_IPU1_IRQ_45_46RW320x0000 080C0x4A00 280C
CTRL_CORE_IPU1_IRQ_47_48RW320x0000 08100x4A00 2810
CTRL_CORE_IPU1_IRQ_49_50RW320x0000 08140x4A00 2814
CTRL_CORE_IPU1_IRQ_51_52RW320x0000 08180x4A00 2818
CTRL_CORE_IPU1_IRQ_53_54RW320x0000 081C0x4A00 281C
CTRL_CORE_IPU1_IRQ_55_56RW320x0000 08200x4A00 2820
CTRL_CORE_IPU1_IRQ_57_58RW320x0000 08240x4A00 2824
CTRL_CORE_IPU1_IRQ_59_60RW320x0000 08280x4A00 2828
CTRL_CORE_IPU1_IRQ_61_62RW320x0000 082C0x4A00 282C
CTRL_CORE_IPU1_IRQ_63_64RW320x0000 08300x4A00 2830
CTRL_CORE_IPU1_IRQ_65_66RW320x0000 08340x4A00 2834
CTRL_CORE_IPU1_IRQ_67_68RW320x0000 08380x4A00 2838
CTRL_CORE_IPU1_IRQ_69_70RW320x0000 083C0x4A00 283C
CTRL_CORE_IPU1_IRQ_71_72RW320x0000 08400x4A00 2840
CTRL_CORE_IPU1_IRQ_73_74RW320x0000 08440x4A00 2844
CTRL_CORE_IPU1_IRQ_75_76RW320x0000 08480x4A00 2848
CTRL_CORE_IPU1_IRQ_77_78RW320x0000 084C0x4A00 284C
CTRL_CORE_IPU1_IRQ_79_80RW320x0000 08500x4A00 2850
CTRL_CORE_IPU2_IRQ_23_24RW320x0000 08540x4A00 2854
CTRL_CORE_IPU2_IRQ_25_26RW320x0000 08580x4A00 2858
CTRL_CORE_IPU2_IRQ_27_28RW320x0000 085C0x4A00 285C
CTRL_CORE_IPU2_IRQ_29_30RW320x0000 08600x4A00 2860
CTRL_CORE_IPU2_IRQ_31_32RW320x0000 08640x4A00 2864
CTRL_CORE_IPU2_IRQ_33_34RW320x0000 08680x4A00 2868
CTRL_CORE_IPU2_IRQ_35_36RW320x0000 086C0x4A00 286C
CTRL_CORE_IPU2_IRQ_37_38RW320x0000 08700x4A00 2870
CTRL_CORE_IPU2_IRQ_39_40RW320x0000 08740x4A00 2874
CTRL_CORE_IPU2_IRQ_41_42RW320x0000 08780x4A00 2878
CTRL_CORE_IPU2_IRQ_43_44RW320x0000 087C0x4A00 287C
CTRL_CORE_IPU2_IRQ_45_46RW320x0000 08800x4A00 2880
CTRL_CORE_IPU2_IRQ_47_48RW320x0000 08840x4A00 2884
CTRL_CORE_IPU2_IRQ_49_50RW320x0000 08880x4A00 2888
CTRL_CORE_IPU2_IRQ_51_52RW320x0000 088C0x4A00 288C
CTRL_CORE_IPU2_IRQ_53_54RW320x0000 08900x4A00 2890
CTRL_CORE_IPU2_IRQ_55_56RW320x0000 08940x4A00 2894
CTRL_CORE_IPU2_IRQ_57_58RW320x0000 08980x4A00 2898
CTRL_CORE_IPU2_IRQ_59_60RW320x0000 089C0x4A00 289C
CTRL_CORE_IPU2_IRQ_61_62RW320x0000 08A00x4A00 28A0
CTRL_CORE_IPU2_IRQ_63_64RW320x0000 08A40x4A00 28A4
CTRL_CORE_IPU2_IRQ_65_66RW320x0000 08A80x4A00 28A8
CTRL_CORE_IPU2_IRQ_67_68RW320x0000 08AC0x4A00 28AC
CTRL_CORE_IPU2_IRQ_69_70RW320x0000 08B00x4A00 28B0
CTRL_CORE_IPU2_IRQ_71_72RW320x0000 08B40x4A00 28B4
CTRL_CORE_IPU2_IRQ_73_74RW320x0000 08B80x4A00 28B8
CTRL_CORE_IPU2_IRQ_75_76RW320x0000 08BC0x4A00 28BC
CTRL_CORE_IPU2_IRQ_77_78RW320x0000 08C00x4A00 28C0
CTRL_CORE_IPU2_IRQ_79_80RW320x0000 08C40x4A00 28C4
RESERVED_y (y = 0 to 31)R320x0000 08C8 + (y*4)0x4A00 28C8 + (y*4)
CTRL_CORE_DSP1_IRQ_32_33RW320x0000 09480x4A00 2948
CTRL_CORE_DSP1_IRQ_34_35RW320x0000 094C0x4A00 294C
CTRL_CORE_DSP1_IRQ_36_37RW320x0000 09500x4A00 2950
CTRL_CORE_DSP1_IRQ_38_39RW320x0000 09540x4A00 2954
CTRL_CORE_DSP1_IRQ_40_41RW320x0000 09580x4A00 2958
CTRL_CORE_DSP1_IRQ_42_43RW320x0000 095C0x4A00 295C
CTRL_CORE_DSP1_IRQ_44_45RW320x0000 09600x4A00 2960
CTRL_CORE_DSP1_IRQ_46_47RW320x0000 09640x4A00 2964
CTRL_CORE_DSP1_IRQ_48_49RW320x0000 09680x4A00 2968
CTRL_CORE_DSP1_IRQ_50_51RW320x0000 096C0x4A00 296C
CTRL_CORE_DSP1_IRQ_52_53RW320x0000 09700x4A00 2970
CTRL_CORE_DSP1_IRQ_54_55RW320x0000 09740x4A00 2974
CTRL_CORE_DSP1_IRQ_56_57RW320x0000 09780x4A00 2978
CTRL_CORE_DSP1_IRQ_58_59RW320x0000 097C0x4A00 297C
CTRL_CORE_DSP1_IRQ_60_61RW320x0000 09800x4A00 2980
CTRL_CORE_DSP1_IRQ_62_63RW320x0000 09840x4A00 2984
CTRL_CORE_DSP1_IRQ_64_65RW320x0000 09880x4A00 2988
CTRL_CORE_DSP1_IRQ_66_67RW320x0000 098C0x4A00 298C
CTRL_CORE_DSP1_IRQ_68_69RW320x0000 09900x4A00 2990
CTRL_CORE_DSP1_IRQ_70_71RW320x0000 09940x4A00 2994
CTRL_CORE_DSP1_IRQ_72_73RW320x0000 09980x4A00 2998
CTRL_CORE_DSP1_IRQ_74_75RW320x0000 099C0x4A00 299C
CTRL_CORE_DSP1_IRQ_76_77RW320x0000 09A00x4A00 29A0
CTRL_CORE_DSP1_IRQ_78_79RW320x0000 09A40x4A00 29A4
CTRL_CORE_DSP1_IRQ_80_81RW320x0000 09A80x4A00 29A8
CTRL_CORE_DSP1_IRQ_82_83RW320x0000 09AC0x4A00 29AC
CTRL_CORE_DSP1_IRQ_84_85RW320x0000 09B00x4A00 29B0
CTRL_CORE_DSP1_IRQ_86_87RW320x0000 09B40x4A00 29B4
CTRL_CORE_DSP1_IRQ_88_89RW320x0000 09B80x4A00 29B8
CTRL_CORE_DSP1_IRQ_90_91RW320x0000 09BC0x4A00 29BC
CTRL_CORE_DSP1_IRQ_92_93RW320x0000 09C00x4A00 29C0
CTRL_CORE_DSP1_IRQ_94_95RW320x0000 09C40x4A00 29C4
CTRL_CORE_DSP2_IRQ_32_33RW320x0000 09C80x4A00 29C8
CTRL_CORE_DSP2_IRQ_34_35RW320x0000 09CC0x4A00 29CC
CTRL_CORE_DSP2_IRQ_36_37RW320x0000 09D00x4A00 29D0
CTRL_CORE_DSP2_IRQ_38_39RW320x0000 09D40x4A00 29D4
CTRL_CORE_DSP2_IRQ_40_41RW320x0000 09D80x4A00 29D8
CTRL_CORE_DSP2_IRQ_42_43RW320x0000 09DC0x4A00 29DC
CTRL_CORE_DSP2_IRQ_44_45RW320x0000 09E00x4A00 29E0
CTRL_CORE_DSP2_IRQ_46_47RW320x0000 09E40x4A00 29E4
CTRL_CORE_DSP2_IRQ_48_49RW320x0000 09E80x4A00 29E8
CTRL_CORE_DSP2_IRQ_50_51RW320x0000 09EC0x4A00 29EC
CTRL_CORE_DSP2_IRQ_52_53RW320x0000 09F00x4A00 29F0
CTRL_CORE_DSP2_IRQ_54_55RW320x0000 09F40x4A00 29F4
CTRL_CORE_DSP2_IRQ_56_57RW320x0000 09F80x4A00 29F8
CTRL_CORE_DSP2_IRQ_58_59RW320x0000 09FC0x4A00 29FC
CTRL_CORE_DSP2_IRQ_60_61RW320x0000 0A000x4A00 2A00
CTRL_CORE_DSP2_IRQ_62_63RW320x0000 0A040x4A00 2A04
CTRL_CORE_DSP2_IRQ_64_65RW320x0000 0A080x4A00 2A08
CTRL_CORE_DSP2_IRQ_66_67RW320x0000 0A0C0x4A00 2A0C
CTRL_CORE_DSP2_IRQ_68_69RW320x0000 0A100x4A00 2A10
CTRL_CORE_DSP2_IRQ_70_71RW320x0000 0A140x4A00 2A14
CTRL_CORE_DSP2_IRQ_72_73RW320x0000 0A180x4A00 2A18
CTRL_CORE_DSP2_IRQ_74_75RW320x0000 0A1C0x4A00 2A1C
CTRL_CORE_DSP2_IRQ_76_77RW320x0000 0A200x4A00 2A20
CTRL_CORE_DSP2_IRQ_78_79RW320x0000 0A240x4A00 2A24
CTRL_CORE_DSP2_IRQ_80_81RW320x0000 0A280x4A00 2A28
CTRL_CORE_DSP2_IRQ_82_83RW320x0000 0A2C0x4A00 2A2C
CTRL_CORE_DSP2_IRQ_84_85RW320x0000 0A300x4A00 2A30
CTRL_CORE_DSP2_IRQ_86_87RW320x0000 0A340x4A00 2A34
CTRL_CORE_DSP2_IRQ_88_89RW320x0000 0A380x4A00 2A38
CTRL_CORE_DSP2_IRQ_90_91RW320x0000 0A3C0x4A00 2A3C
CTRL_CORE_DSP2_IRQ_92_93RW320x0000 0A400x4A00 2A40
CTRL_CORE_DSP2_IRQ_94_95RW320x0000 0A440x4A00 2A44
CTRL_CORE_MPU_IRQ_4_7RW320x0000 0A480x4A00 2A48
CTRL_CORE_MPU_IRQ_8_9RW320x0000 0A4C0x4A00 2A4C
CTRL_CORE_MPU_IRQ_10_11RW320x0000 0A500x4A00 2A50
CTRL_CORE_MPU_IRQ_12_13RW320x0000 0A540x4A00 2A54
CTRL_CORE_MPU_IRQ_14_15RW320x0000 0A580x4A00 2A58
CTRL_CORE_MPU_IRQ_16_17RW320x0000 0A5C0x4A00 2A5C
CTRL_CORE_MPU_IRQ_18_19RW320x0000 0A600x4A00 2A60
CTRL_CORE_MPU_IRQ_20_21RW320x0000 0A640x4A00 2A64
CTRL_CORE_MPU_IRQ_22_23RW320x0000 0A680x4A00 2A68
CTRL_CORE_MPU_IRQ_24_25RW320x0000 0A6C0x4A00 2A6C
CTRL_CORE_MPU_IRQ_26_27RW320x0000 0A700x4A00 2A70
CTRL_CORE_MPU_IRQ_28_29RW320x0000 0A740x4A00 2A74
CTRL_CORE_MPU_IRQ_30_31RW320x0000 0A780x4A00 2A78
CTRL_CORE_MPU_IRQ_32_33RW320x0000 0A7C0x4A00 2A7C
CTRL_CORE_MPU_IRQ_34_35RW320x0000 0A800x4A00 2A80
CTRL_CORE_MPU_IRQ_36_37RW320x0000 0A840x4A00 2A84
CTRL_CORE_MPU_IRQ_38_39RW320x0000 0A880x4A00 2A88
CTRL_CORE_MPU_IRQ_40_41RW320x0000 0A8C0x4A00 2A8C
CTRL_CORE_MPU_IRQ_42_43RW320x0000 0A900x4A00 2A90
CTRL_CORE_MPU_IRQ_44_45RW320x0000 0A940x4A00 2A94
CTRL_CORE_MPU_IRQ_46_47RW320x0000 0A980x4A00 2A98
CTRL_CORE_MPU_IRQ_48_49RW320x0000 0A9C0x4A00 2A9C
CTRL_CORE_MPU_IRQ_50_51RW320x0000 0AA00x4A00 2AA0
CTRL_CORE_MPU_IRQ_52_53RW320x0000 0AA40x4A00 2AA4
CTRL_CORE_MPU_IRQ_54_55RW320x0000 0AA80x4A00 2AA8
CTRL_CORE_MPU_IRQ_56_57RW320x0000 0AAC0x4A00 2AAC
CTRL_CORE_MPU_IRQ_58_59RW320x0000 0AB00x4A00 2AB0
CTRL_CORE_MPU_IRQ_60_61RW320x0000 0AB40x4A00 2AB4
CTRL_CORE_MPU_IRQ_62_63RW320x0000 0AB80x4A00 2AB8
CTRL_CORE_MPU_IRQ_64_65RW320x0000 0ABC0x4A00 2ABC
CTRL_CORE_MPU_IRQ_66_67RW320x0000 0AC00x4A00 2AC0
CTRL_CORE_MPU_IRQ_68_69RW320x0000 0AC40x4A00 2AC4
CTRL_CORE_MPU_IRQ_70_71RW320x0000 0AC80x4A00 2AC8
CTRL_CORE_MPU_IRQ_72_73RW320x0000 0ACC0x4A00 2ACC
CTRL_CORE_MPU_IRQ_74_75RW320x0000 0AD00x4A00 2AD0
CTRL_CORE_MPU_IRQ_76_77RW320x0000 0AD40x4A00 2AD4
CTRL_CORE_MPU_IRQ_78_79RW320x0000 0AD80x4A00 2AD8
CTRL_CORE_MPU_IRQ_80_81RW320x0000 0ADC0x4A00 2ADC
CTRL_CORE_MPU_IRQ_82_83RW320x0000 0AE00x4A00 2AE0
CTRL_CORE_MPU_IRQ_84_85RW320x0000 0AE40x4A00 2AE4
CTRL_CORE_MPU_IRQ_86_87RW320x0000 0AE80x4A00 2AE8
CTRL_CORE_MPU_IRQ_88_89RW320x0000 0AEC0x4A00 2AEC
CTRL_CORE_MPU_IRQ_90_91RW320x0000 0AF00x4A00 2AF0
CTRL_CORE_MPU_IRQ_92_93RW320x0000 0AF40x4A00 2AF4
CTRL_CORE_MPU_IRQ_94_95RW320x0000 0AF80x4A00 2AF8
CTRL_CORE_MPU_IRQ_96_97RW320x0000 0AFC0x4A00 2AFC
CTRL_CORE_MPU_IRQ_98_99RW320x0000 0B000x4A00 2B00
CTRL_CORE_MPU_IRQ_100_101RW320x0000 0B040x4A00 2B04
CTRL_CORE_MPU_IRQ_102_103RW320x0000 0B080x4A00 2B08
CTRL_CORE_MPU_IRQ_104_105RW320x0000 0B0C0x4A00 2B0C
CTRL_CORE_MPU_IRQ_106_107RW320x0000 0B100x4A00 2B10
CTRL_CORE_MPU_IRQ_108_109RW320x0000 0B140x4A00 2B14
CTRL_CORE_MPU_IRQ_110_111RW320x0000 0B180x4A00 2B18
CTRL_CORE_MPU_IRQ_112_113RW320x0000 0B1C0x4A00 2B1C
CTRL_CORE_MPU_IRQ_114_115RW320x0000 0B200x4A00 2B20
CTRL_CORE_MPU_IRQ_116_117RW320x0000 0B240x4A00 2B24
CTRL_CORE_MPU_IRQ_118_119RW320x0000 0B280x4A00 2B28
CTRL_CORE_MPU_IRQ_120_121RW320x0000 0B2C0x4A00 2B2C
CTRL_CORE_MPU_IRQ_122_123RW320x0000 0B300x4A00 2B30
CTRL_CORE_MPU_IRQ_124_125RW320x0000 0B340x4A00 2B34
CTRL_CORE_MPU_IRQ_126_127RW320x0000 0B380x4A00 2B38
CTRL_CORE_MPU_IRQ_128_129RW320x0000 0B3C0x4A00 2B3C
CTRL_CORE_MPU_IRQ_130_133RW320x0000 0B400x4A00 2B40
CTRL_CORE_MPU_IRQ_134_135RW320x0000 0B440x4A00 2B44
CTRL_CORE_MPU_IRQ_136_137RW320x0000 0B480x4A00 2B48
CTRL_CORE_MPU_IRQ_138_139RW320x0000 0B4C0x4A00 2B4C
CTRL_CORE_MPU_IRQ_140_141RW320x0000 0B500x4A00 2B50
CTRL_CORE_MPU_IRQ_142_143RW320x0000 0B540x4A00 2B54
CTRL_CORE_MPU_IRQ_144_145RW320x0000 0B580x4A00 2B58
CTRL_CORE_MPU_IRQ_146_147RW320x0000 0B5C0x4A00 2B5C
CTRL_CORE_MPU_IRQ_148_149RW320x0000 0B600x4A00 2B60
CTRL_CORE_MPU_IRQ_150_151RW320x0000 0B640x4A00 2B64
CTRL_CORE_MPU_IRQ_152_153RW320x0000 0B680x4A00 2B68
CTRL_CORE_MPU_IRQ_154_155RW320x0000 0B6C0x4A00 2B6C
CTRL_CORE_MPU_IRQ_156_157RW320x0000 0B700x4A00 2B70
CTRL_CORE_MPU_IRQ_158_159RW320x0000 0B740x4A00 2B74
CTRL_CORE_DMA_SYSTEM_DREQ_0_1RW320x0000 0B780x4A00 2B78
CTRL_CORE_DMA_SYSTEM_DREQ_2_3RW320x0000 0B7C0x4A00 2B7C
CTRL_CORE_DMA_SYSTEM_DREQ_4_5RW320x0000 0B800x4A00 2B80
CTRL_CORE_DMA_SYSTEM_DREQ_6_7RW320x0000 0B840x4A00 2B84
CTRL_CORE_DMA_SYSTEM_DREQ_8_9RW320x0000 0B880x4A00 2B88
CTRL_CORE_DMA_SYSTEM_DREQ_10_11RW320x0000 0B8C0x4A00 2B8C
CTRL_CORE_DMA_SYSTEM_DREQ_12_13RW320x0000 0B900x4A00 2B90
CTRL_CORE_DMA_SYSTEM_DREQ_14_15RW320x0000 0B940x4A00 2B94
CTRL_CORE_DMA_SYSTEM_DREQ_16_17RW320x0000 0B980x4A00 2B98
CTRL_CORE_DMA_SYSTEM_DREQ_18_19RW320x0000 0B9C0x4A00 2B9C
CTRL_CORE_DMA_SYSTEM_DREQ_20_21RW320x0000 0BA00x4A00 2BA0
CTRL_CORE_DMA_SYSTEM_DREQ_22_23RW320x0000 0BA40x4A00 2BA4
CTRL_CORE_DMA_SYSTEM_DREQ_24_25RW320x0000 0BA80x4A00 2BA8
CTRL_CORE_DMA_SYSTEM_DREQ_26_27RW320x0000 0BAC0x4A00 2BAC
CTRL_CORE_DMA_SYSTEM_DREQ_28_29RW320x0000 0BB00x4A00 2BB0
CTRL_CORE_DMA_SYSTEM_DREQ_30_31RW320x0000 0BB40x4A00 2BB4
CTRL_CORE_DMA_SYSTEM_DREQ_32_33RW320x0000 0BB80x4A00 2BB8
CTRL_CORE_DMA_SYSTEM_DREQ_34_35RW320x0000 0BBC0x4A00 2BBC
CTRL_CORE_DMA_SYSTEM_DREQ_36_37RW320x0000 0BC00x4A00 2BC0
CTRL_CORE_DMA_SYSTEM_DREQ_38_39RW320x0000 0BC40x4A00 2BC4
CTRL_CORE_DMA_SYSTEM_DREQ_40_41RW320x0000 0BC80x4A00 2BC8
CTRL_CORE_DMA_SYSTEM_DREQ_42_43RW320x0000 0BCC0x4A00 2BCC
CTRL_CORE_DMA_SYSTEM_DREQ_44_45RW320x0000 0BD00x4A00 2BD0
CTRL_CORE_DMA_SYSTEM_DREQ_46_47RW320x0000 0BD40x4A00 2BD4
CTRL_CORE_DMA_SYSTEM_DREQ_48_49RW320x0000 0BD80x4A00 2BD8
CTRL_CORE_DMA_SYSTEM_DREQ_50_51RW320x0000 0BDC0x4A00 2BDC
CTRL_CORE_DMA_SYSTEM_DREQ_52_53RW320x0000 0BE00x4A00 2BE0
CTRL_CORE_DMA_SYSTEM_DREQ_54_55RW320x0000 0BE40x4A00 2BE4
CTRL_CORE_DMA_SYSTEM_DREQ_56_57RW320x0000 0BE80x4A00 2BE8
CTRL_CORE_DMA_SYSTEM_DREQ_58_59RW320x0000 0BEC0x4A00 2BEC
CTRL_CORE_DMA_SYSTEM_DREQ_60_61RW320x0000 0BF00x4A00 2BF0
CTRL_CORE_DMA_SYSTEM_DREQ_62_63RW320x0000 0BF40x4A00 2BF4
CTRL_CORE_DMA_SYSTEM_DREQ_64_65RW320x0000 0BF80x4A00 2BF8
CTRL_CORE_DMA_SYSTEM_DREQ_66_67RW320x0000 0BFC0x4A00 2BFC
CTRL_CORE_DMA_SYSTEM_DREQ_68_69RW320x0000 0C000x4A00 2C00
CTRL_CORE_DMA_SYSTEM_DREQ_70_71RW320x0000 0C040x4A00 2C04
CTRL_CORE_DMA_SYSTEM_DREQ_72_73RW320x0000 0C080x4A00 2C08
CTRL_CORE_DMA_SYSTEM_DREQ_74_75RW320x0000 0C0C0x4A00 2C0C
CTRL_CORE_DMA_SYSTEM_DREQ_76_77RW320x0000 0C100x4A00 2C10
CTRL_CORE_DMA_SYSTEM_DREQ_78_79RW320x0000 0C140x4A00 2C14
CTRL_CORE_DMA_SYSTEM_DREQ_80_81RW320x0000 0C180x4A00 2C18
CTRL_CORE_DMA_SYSTEM_DREQ_82_83RW320x0000 0C1C0x4A00 2C1C
CTRL_CORE_DMA_SYSTEM_DREQ_84_85RW320x0000 0C200x4A00 2C20
CTRL_CORE_DMA_SYSTEM_DREQ_86_87RW320x0000 0C240x4A00 2C24
CTRL_CORE_DMA_SYSTEM_DREQ_88_89RW320x0000 0C280x4A00 2C28
CTRL_CORE_DMA_SYSTEM_DREQ_90_91RW320x0000 0C2C0x4A00 2C2C
CTRL_CORE_DMA_SYSTEM_DREQ_92_93RW320x0000 0C300x4A00 2C30
CTRL_CORE_DMA_SYSTEM_DREQ_94_95RW320x0000 0C340x4A00 2C34
CTRL_CORE_DMA_SYSTEM_DREQ_96_97RW320x0000 0C380x4A00 2C38
CTRL_CORE_DMA_SYSTEM_DREQ_98_99RW320x0000 0C3C0x4A00 2C3C
CTRL_CORE_DMA_SYSTEM_DREQ_100_101RW320x0000 0C400x4A00 2C40
CTRL_CORE_DMA_SYSTEM_DREQ_102_103RW320x0000 0C440x4A00 2C44
CTRL_CORE_DMA_SYSTEM_DREQ_104_105RW320x0000 0C480x4A00 2C48
CTRL_CORE_DMA_SYSTEM_DREQ_106_107RW320x0000 0C4C0x4A00 2C4C
CTRL_CORE_DMA_SYSTEM_DREQ_108_109RW320x0000 0C500x4A00 2C50
CTRL_CORE_DMA_SYSTEM_DREQ_110_111RW320x0000 0C540x4A00 2C54
CTRL_CORE_DMA_SYSTEM_DREQ_112_113RW320x0000 0C580x4A00 2C58
CTRL_CORE_DMA_SYSTEM_DREQ_114_115RW320x0000 0C5C0x4A00 2C5C
CTRL_CORE_DMA_SYSTEM_DREQ_116_117RW320x0000 0C600x4A00 2C60
CTRL_CORE_DMA_SYSTEM_DREQ_118_119RW320x0000 0C640x4A00 2C64
CTRL_CORE_DMA_SYSTEM_DREQ_120_121RW320x0000 0C680x4A00 2C68
CTRL_CORE_DMA_SYSTEM_DREQ_122_123RW320x0000 0C6C0x4A00 2C6C
CTRL_CORE_DMA_SYSTEM_DREQ_124_125RW320x0000 0C700x4A00 2C70
CTRL_CORE_DMA_SYSTEM_DREQ_126_127RW320x0000 0C740x4A00 2C74
CTRL_CORE_DMA_EDMA_DREQ_0_1RW320x0000 0C780x4A00 2C78
CTRL_CORE_DMA_EDMA_DREQ_2_3RW320x0000 0C7C0x4A00 2C7C
CTRL_CORE_DMA_EDMA_DREQ_4_5RW320x0000 0C800x4A00 2C80
CTRL_CORE_DMA_EDMA_DREQ_6_7RW320x0000 0C840x4A00 2C84
CTRL_CORE_DMA_EDMA_DREQ_8_9RW320x0000 0C880x4A00 2C88
CTRL_CORE_DMA_EDMA_DREQ_10_11RW320x0000 0C8C0x4A00 2C8C
CTRL_CORE_DMA_EDMA_DREQ_12_13RW320x0000 0C900x4A00 2C90
CTRL_CORE_DMA_EDMA_DREQ_14_15RW320x0000 0C940x4A00 2C94
CTRL_CORE_DMA_EDMA_DREQ_16_17RW320x0000 0C980x4A00 2C98
CTRL_CORE_DMA_EDMA_DREQ_18_19RW320x0000 0C9C0x4A00 2C9C
CTRL_CORE_DMA_EDMA_DREQ_20_21RW320x0000 0CA00x4A00 2CA0
CTRL_CORE_DMA_EDMA_DREQ_22_23RW320x0000 0CA40x4A00 2CA4
CTRL_CORE_DMA_EDMA_DREQ_24_25RW320x0000 0CA80x4A00 2CA8
CTRL_CORE_DMA_EDMA_DREQ_26_27RW320x0000 0CAC0x4A00 2CAC
CTRL_CORE_DMA_EDMA_DREQ_28_29RW320x0000 0CB00x4A00 2CB0
CTRL_CORE_DMA_EDMA_DREQ_30_31RW320x0000 0CB40x4A00 2CB4
CTRL_CORE_DMA_EDMA_DREQ_32_33RW320x0000 0CB80x4A00 2CB8
CTRL_CORE_DMA_EDMA_DREQ_34_35RW320x0000 0CBC0x4A00 2CBC
CTRL_CORE_DMA_EDMA_DREQ_36_37RW320x0000 0CC00x4A00 2CC0
CTRL_CORE_DMA_EDMA_DREQ_38_39RW320x0000 0CC40x4A00 2CC4
CTRL_CORE_DMA_EDMA_DREQ_40_41RW320x0000 0CC80x4A00 2CC8
CTRL_CORE_DMA_EDMA_DREQ_42_43RW320x0000 0CCC0x4A00 2CCC
CTRL_CORE_DMA_EDMA_DREQ_44_45RW320x0000 0CD00x4A00 2CD0
CTRL_CORE_DMA_EDMA_DREQ_46_47RW320x0000 0CD40x4A00 2CD4
CTRL_CORE_DMA_EDMA_DREQ_48_49RW320x0000 0CD80x4A00 2CD8
CTRL_CORE_DMA_EDMA_DREQ_50_51RW320x0000 0CDC0x4A00 2CDC
CTRL_CORE_DMA_EDMA_DREQ_52_53RW320x0000 0CE00x4A00 2CE0
CTRL_CORE_DMA_EDMA_DREQ_54_55RW320x0000 0CE40x4A00 2CE4
CTRL_CORE_DMA_EDMA_DREQ_56_57RW320x0000 0CE80x4A00 2CE8
CTRL_CORE_DMA_EDMA_DREQ_58_59RW320x0000 0CEC0x4A00 2CEC
CTRL_CORE_DMA_EDMA_DREQ_60_61RW320x0000 0CF00x4A00 2CF0
CTRL_CORE_DMA_EDMA_DREQ_62_63RW320x0000 0CF40x4A00 2CF4
CTRL_CORE_DMA_DSP1_DREQ_0_1RW320x0000 0CF80x4A00 2CF8
CTRL_CORE_DMA_DSP1_DREQ_2_3RW320x0000 0CFC0x4A00 2CFC
CTRL_CORE_DMA_DSP1_DREQ_4_5RW320x0000 0D000x4A00 2D00
CTRL_CORE_DMA_DSP1_DREQ_6_7RW320x0000 0D040x4A00 2D04
CTRL_CORE_DMA_DSP1_DREQ_8_9RW320x0000 0D080x4A00 2D08
CTRL_CORE_DMA_DSP1_DREQ_10_11RW320x0000 0D0C0x4A00 2D0C
CTRL_CORE_DMA_DSP1_DREQ_12_13RW320x0000 0D100x4A00 2D10
CTRL_CORE_DMA_DSP1_DREQ_14_15RW320x0000 0D140x4A00 2D14
CTRL_CORE_DMA_DSP1_DREQ_16_17RW320x0000 0D180x4A00 2D18
CTRL_CORE_DMA_DSP1_DREQ_18_19RW320x0000 0D1C0x4A00 2D1C
CTRL_CORE_DMA_DSP2_DREQ_0_1RW320x0000 0D200x4A00 2D20
CTRL_CORE_DMA_DSP2_DREQ_2_3RW320x0000 0D240x4A00 2D24
CTRL_CORE_DMA_DSP2_DREQ_4_5RW320x0000 0D280x4A00 2D28
CTRL_CORE_DMA_DSP2_DREQ_6_7RW320x0000 0D2C0x4A00 2D2C
CTRL_CORE_DMA_DSP2_DREQ_8_9RW320x0000 0D300x4A00 2D30
CTRL_CORE_DMA_DSP2_DREQ_10_11RW320x0000 0D340x4A00 2D34
CTRL_CORE_DMA_DSP2_DREQ_12_13RW320x0000 0D380x4A00 2D38
CTRL_CORE_DMA_DSP2_DREQ_14_15RW320x0000 0D3C0x4A00 2D3C
CTRL_CORE_DMA_DSP2_DREQ_16_17RW320x0000 0D400x4A00 2D40
CTRL_CORE_DMA_DSP2_DREQ_18_19RW320x0000 0D440x4A00 2D44
RESERVEDR320x0000 0D480x4A00 2D48
CTRL_CORE_OVS_DMARQ_IO_MUXRW320x0000 0D4C0x4A00 2D4C
CTRL_CORE_OVS_IRQ_IO_MUXRW320x0000 0D500x4A00 2D50
RESERVED_q (q = 0 to 42)R320x0000 0D54 + (q*4)0x4A00 2D54 + (q*4)
CTRL_CORE_CONTROL_PBIASRW320x0000 0E000x4A00 2E00
RESERVEDR320x0000 0E040x4A00 2E04
CTRL_CORE_CONTROL_HDMI_TX_PHYRW320x0000 0E0C0x4A00 2E0C
RESERVEDR320x0000 0E140x4A00 2E14
RESERVEDR320x0000 0E180x4A00 2E18
CTRL_CORE_CONTROL_USB2PHYCORERW320x0000 0E1C0x4A00 2E1C
CTRL_CORE_CONTROL_HDMI_1RW320x0000 0E200x4A00 2E20
RESERVEDRW320x0000 0E240x4A00 2E24
CTRL_CORE_CONTROL_DDRCACH1_0RW320x0000 0E300x4A00 2E30
CTRL_CORE_CONTROL_DDRCACH2_0RW320x0000 0E340x4A00 2E34
CTRL_CORE_CONTROL_DDRCH1_0RW320x0000 0E380x4A00 2E38
CTRL_CORE_CONTROL_DDRCH1_1RW320x0000 0E3C0x4A00 2E3C
CTRL_CORE_CONTROL_DDRCH2_0RW320x0000 0E400x4A00 2E40
CTRL_CORE_CONTROL_DDRCH2_1RW320x0000 0E440x4A00 2E44
CTRL_CORE_CONTROL_DDRCH1_2RW320x0000 0E480x4A00 2E48
RESERVEDR320x0000 0E4C0x4A00 2E4C
CTRL_CORE_CONTROL_DDRIO_0RW320x0000 0E500x4A00 2E50
CTRL_CORE_CONTROL_DDRIO_1RW320x0000 0E540x4A00 2E54
RESERVEDR320x0000 0E580x4A00 2E58
CTRL_CORE_CONTROL_HYST_1RW320x0000 0E5C0x4A00 2E5C
RESERVEDR320x0000 0E600x4A00 2E60
RESERVEDR320x0000 0E640x4A00 2E64
CTRL_CORE_CONTROL_SPARE_RWRW320x0000 0E680x4A00 2E68
RESERVEDR320x0000 0E6C0x4A00 2E6C
RESERVEDR320x0000 0E700x4A00 2E70
CTRL_CORE_SRCOMP_NORTH_SIDERW320x0000 0E740x4A00 2E74
CTRL_CORE_SRCOMP_SOUTH_SIDER320x0000 0E780x4A00 2E78
RESERVED_p (p = 0 to 352)R320x0000 0E7C + (p*4)0x4A00 2E7C + (p*4)
CTRL_CORE_PAD_GPMC_AD0RW320x0000 14000x4A00 3400
CTRL_CORE_PAD_GPMC_AD1RW320x0000 14040x4A00 3404
CTRL_CORE_PAD_GPMC_AD2RW320x0000 14080x4A00 3408
CTRL_CORE_PAD_GPMC_AD3RW320x0000 140C0x4A00 340C
CTRL_CORE_PAD_GPMC_AD4RW320x0000 14100x4A00 3410
CTRL_CORE_PAD_GPMC_AD5RW320x0000 14140x4A00 3414
CTRL_CORE_PAD_GPMC_AD6RW320x0000 14180x4A00 3418
CTRL_CORE_PAD_GPMC_AD7RW320x0000 141C0x4A00 341C
CTRL_CORE_PAD_GPMC_AD8RW320x0000 14200x4A00 3420
CTRL_CORE_PAD_GPMC_AD9RW320x0000 14240x4A00 3424
CTRL_CORE_PAD_GPMC_AD10RW320x0000 14280x4A00 3428
CTRL_CORE_PAD_GPMC_AD11RW320x0000 142C0x4A00 342C
CTRL_CORE_PAD_GPMC_AD12RW320x0000 14300x4A00 3430
CTRL_CORE_PAD_GPMC_AD13RW320x0000 14340x4A00 3434
CTRL_CORE_PAD_GPMC_AD14RW320x0000 14380x4A00 3438
CTRL_CORE_PAD_GPMC_AD15RW320x0000 143C0x4A00 343C
CTRL_CORE_PAD_GPMC_A0RW320x0000 14400x4A00 3440
CTRL_CORE_PAD_GPMC_A1RW320x0000 14440x4A00 3444
CTRL_CORE_PAD_GPMC_A2RW320x0000 14480x4A00 3448
CTRL_CORE_PAD_GPMC_A3RW320x0000 144C0x4A00 344C
CTRL_CORE_PAD_GPMC_A4RW320x0000 14500x4A00 3450
CTRL_CORE_PAD_GPMC_A5RW320x0000 14540x4A00 3454
CTRL_CORE_PAD_GPMC_A6RW320x0000 14580x4A00 3458
CTRL_CORE_PAD_GPMC_A7RW320x0000 145C0x4A00 345C
CTRL_CORE_PAD_GPMC_A8RW320x0000 14600x4A00 3460
CTRL_CORE_PAD_GPMC_A9RW320x0000 14640x4A00 3464
CTRL_CORE_PAD_GPMC_A10RW320x0000 14680x4A00 3468
CTRL_CORE_PAD_GPMC_A11RW320x0000 146C0x4A00 346C
CTRL_CORE_PAD_GPMC_A12RW320x0000 14700x4A00 3470
CTRL_CORE_PAD_GPMC_A13RW320x0000 14740x4A00 3474
CTRL_CORE_PAD_GPMC_A14RW320x0000 14780x4A00 3478
CTRL_CORE_PAD_GPMC_A15RW320x0000 147C0x4A00 347C
CTRL_CORE_PAD_GPMC_A16RW320x0000 14800x4A00 3480
CTRL_CORE_PAD_GPMC_A17RW320x0000 14840x4A00 3484
CTRL_CORE_PAD_GPMC_A18RW320x0000 14880x4A00 3488
CTRL_CORE_PAD_GPMC_A19RW320x0000 148C0x4A00 348C
CTRL_CORE_PAD_GPMC_A20RW320x0000 14900x4A00 3490
CTRL_CORE_PAD_GPMC_A21RW320x0000 14940x4A00 3494
CTRL_CORE_PAD_GPMC_A22RW320x0000 14980x4A00 3498
CTRL_CORE_PAD_GPMC_A23RW320x0000 149C0x4A00 349C
CTRL_CORE_PAD_GPMC_A24RW320x0000 14A00x4A00 34A0
CTRL_CORE_PAD_GPMC_A25RW320x0000 14A40x4A00 34A4
CTRL_CORE_PAD_GPMC_A26RW320x0000 14A80x4A00 34A8
CTRL_CORE_PAD_GPMC_A27RW320x0000 14AC0x4A00 34AC
CTRL_CORE_PAD_GPMC_CS1RW320x0000 14B00x4A00 34B0
CTRL_CORE_PAD_GPMC_CS0RW320x0000 14B40x4A00 34B4
CTRL_CORE_PAD_GPMC_CS2RW320x0000 14B80x4A00 34B8
CTRL_CORE_PAD_GPMC_CS3RW320x0000 14BC0x4A00 34BC
CTRL_CORE_PAD_GPMC_CLKRW320x0000 14C00x4A00 34C0
CTRL_CORE_PAD_GPMC_ADVN_ALERW320x0000 14C40x4A00 34C4
CTRL_CORE_PAD_GPMC_OEN_RENRW320x0000 14C80x4A00 34C8
CTRL_CORE_PAD_GPMC_WENRW320x0000 14CC0x4A00 34CC
CTRL_CORE_PAD_GPMC_BEN0RW320x0000 14D00x4A00 34D0
CTRL_CORE_PAD_GPMC_BEN1RW320x0000 14D40x4A00 34D4
CTRL_CORE_PAD_GPMC_WAIT0RW320x0000 14D80x4A00 34D8
CTRL_CORE_PAD_VIN1A_CLK0RW320x0000 14DC0x4A00 34DC
CTRL_CORE_PAD_VIN1B_CLK1RW320x0000 14E00x4A00 34E0
CTRL_CORE_PAD_VIN1A_DE0RW320x0000 14E40x4A00 34E4
CTRL_CORE_PAD_VIN1A_FLD0RW320x0000 14E80x4A00 34E8
CTRL_CORE_PAD_VIN1A_HSYNC0RW320x0000 14EC0x4A00 34EC
CTRL_CORE_PAD_VIN1A_VSYNC0RW320x0000 14F00x4A00 34F0
CTRL_CORE_PAD_VIN1A_D0RW320x0000 14F40x4A00 34F4
CTRL_CORE_PAD_VIN1A_D1RW320x0000 14F80x4A00 34F8
CTRL_CORE_PAD_VIN1A_D2RW320x0000 14FC0x4A00 34FC
CTRL_CORE_PAD_VIN1A_D3RW320x0000 15000x4A00 3500
CTRL_CORE_PAD_VIN1A_D4RW320x0000 15040x4A00 3504
CTRL_CORE_PAD_VIN1A_D5RW320x0000 15080x4A00 3508
CTRL_CORE_PAD_VIN1A_D6RW320x0000 150C0x4A00 350C
CTRL_CORE_PAD_VIN1A_D7RW320x0000 15100x4A00 3510
CTRL_CORE_PAD_VIN1A_D8RW320x0000 15140x4A00 3514
CTRL_CORE_PAD_VIN1A_D9RW320x0000 15180x4A00 3518
CTRL_CORE_PAD_VIN1A_D10RW320x0000 151C0x4A00 351C
CTRL_CORE_PAD_VIN1A_D11RW320x0000 15200x4A00 3520
CTRL_CORE_PAD_VIN1A_D12RW320x0000 15240x4A00 3524
CTRL_CORE_PAD_VIN1A_D13RW320x0000 15280x4A00 3528
CTRL_CORE_PAD_VIN1A_D14RW320x0000 152C0x4A00 352C
CTRL_CORE_PAD_VIN1A_D15RW320x0000 15300x4A00 3530
CTRL_CORE_PAD_VIN1A_D16RW320x0000 15340x4A00 3534
CTRL_CORE_PAD_VIN1A_D17RW320x0000 15380x4A00 3538
CTRL_CORE_PAD_VIN1A_D18RW320x0000 153C0x4A00 353C
CTRL_CORE_PAD_VIN1A_D19RW320x0000 15400x4A00 3540
CTRL_CORE_PAD_VIN1A_D20RW320x0000 15440x4A00 3544
CTRL_CORE_PAD_VIN1A_D21RW320x0000 15480x4A00 3548
CTRL_CORE_PAD_VIN1A_D22RW320x0000 154C0x4A00 354C
CTRL_CORE_PAD_VIN1A_D23RW320x0000 15500x4A00 3550
CTRL_CORE_PAD_VIN2A_CLK0RW320x0000 15540x4A00 3554
CTRL_CORE_PAD_VIN2A_DE0RW320x0000 15580x4A00 3558
CTRL_CORE_PAD_VIN2A_FLD0RW320x0000 155C0x4A00 355C
CTRL_CORE_PAD_VIN2A_HSYNC0RW320x0000 15600x4A00 3560
CTRL_CORE_PAD_VIN2A_VSYNC0RW320x0000 15640x4A00 3564
CTRL_CORE_PAD_VIN2A_D0RW320x0000 15680x4A00 3568
CTRL_CORE_PAD_VIN2A_D1RW320x0000 156C0x4A00 356C
CTRL_CORE_PAD_VIN2A_D2RW320x0000 15700x4A00 3570
CTRL_CORE_PAD_VIN2A_D3RW320x0000 15740x4A00 3574
CTRL_CORE_PAD_VIN2A_D4RW320x0000 15780x4A00 3578
CTRL_CORE_PAD_VIN2A_D5RW320x0000 157C0x4A00 357C
CTRL_CORE_PAD_VIN2A_D6RW320x0000 15800x4A00 3580
CTRL_CORE_PAD_VIN2A_D7RW320x0000 15840x4A00 3584
CTRL_CORE_PAD_VIN2A_D8RW320x0000 15880x4A00 3588
CTRL_CORE_PAD_VIN2A_D9RW320x0000 158C0x4A00 358C
CTRL_CORE_PAD_VIN2A_D10RW320x0000 15900x4A00 3590
CTRL_CORE_PAD_VIN2A_D11RW320x0000 15940x4A00 3594
CTRL_CORE_PAD_VIN2A_D12RW320x0000 15980x4A00 3598
CTRL_CORE_PAD_VIN2A_D13RW320x0000 159C0x4A00 359C
CTRL_CORE_PAD_VIN2A_D14RW320x0000 15A00x4A00 35A0
CTRL_CORE_PAD_VIN2A_D15RW320x0000 15A40x4A00 35A4
CTRL_CORE_PAD_VIN2A_D16RW320x0000 15A80x4A00 35A8
CTRL_CORE_PAD_VIN2A_D17RW320x0000 15AC0x4A00 35AC
CTRL_CORE_PAD_VIN2A_D18RW320x0000 15B00x4A00 35B0
CTRL_CORE_PAD_VIN2A_D19RW320x0000 15B40x4A00 35B4
CTRL_CORE_PAD_VIN2A_D20RW320x0000 15B80x4A00 35B8
CTRL_CORE_PAD_VIN2A_D21RW320x0000 15BC0x4A00 35BC
CTRL_CORE_PAD_VIN2A_D22RW320x0000 15C00x4A00 35C0
CTRL_CORE_PAD_VIN2A_D23RW320x0000 15C40x4A00 35C4
CTRL_CORE_PAD_VOUT1_CLKRW320x0000 15C80x4A00 35C8
CTRL_CORE_PAD_VOUT1_DERW320x0000 15CC0x4A00 35CC
CTRL_CORE_PAD_VOUT1_FLDRW320x0000 15D00x4A00 35D0
CTRL_CORE_PAD_VOUT1_HSYNCRW320x0000 15D40x4A00 35D4
CTRL_CORE_PAD_VOUT1_VSYNCRW320x0000 15D80x4A00 35D8
CTRL_CORE_PAD_VOUT1_D0RW320x0000 15DC0x4A00 35DC
CTRL_CORE_PAD_VOUT1_D1RW320x0000 15E00x4A00 35E0
CTRL_CORE_PAD_VOUT1_D2RW320x0000 15E40x4A00 35E4
CTRL_CORE_PAD_VOUT1_D3RW320x0000 15E80x4A00 35E8
CTRL_CORE_PAD_VOUT1_D4RW320x0000 15EC0x4A00 35EC
CTRL_CORE_PAD_VOUT1_D5RW320x0000 15F00x4A00 35F0
CTRL_CORE_PAD_VOUT1_D6RW320x0000 15F40x4A00 35F4
CTRL_CORE_PAD_VOUT1_D7RW320x0000 15F80x4A00 35F8
CTRL_CORE_PAD_VOUT1_D8RW320x0000 15FC0x4A00 35FC
CTRL_CORE_PAD_VOUT1_D9RW320x0000 16000x4A00 3600
CTRL_CORE_PAD_VOUT1_D10RW320x0000 16040x4A00 3604
CTRL_CORE_PAD_VOUT1_D11RW320x0000 16080x4A00 3608
CTRL_CORE_PAD_VOUT1_D12RW320x0000 160C0x4A00 360C
CTRL_CORE_PAD_VOUT1_D13RW320x0000 16100x4A00 3610
CTRL_CORE_PAD_VOUT1_D14RW320x0000 16140x4A00 3614
CTRL_CORE_PAD_VOUT1_D15RW320x0000 16180x4A00 3618
CTRL_CORE_PAD_VOUT1_D16RW320x0000 161C0x4A00 361C
CTRL_CORE_PAD_VOUT1_D17RW320x0000 16200x4A00 3620
CTRL_CORE_PAD_VOUT1_D18RW320x0000 16240x4A00 3624
CTRL_CORE_PAD_VOUT1_D19RW320x0000 16280x4A00 3628
CTRL_CORE_PAD_VOUT1_D20RW320x0000 162C0x4A00 362C
CTRL_CORE_PAD_VOUT1_D21RW320x0000 16300x4A00 3630
CTRL_CORE_PAD_VOUT1_D22RW320x0000 16340x4A00 3634
CTRL_CORE_PAD_VOUT1_D23RW320x0000 16380x4A00 3638
CTRL_CORE_PAD_MDIO_MCLKRW320x0000 163C0x4A00 363C
CTRL_CORE_PAD_MDIO_DRW320x0000 16400x4A00 3640
CTRL_CORE_PAD_RMII_MHZ_50_CLKRW320x0000 16440x4A00 3644
CTRL_CORE_PAD_UART3_RXDRW320x0000 16480x4A00 3648
CTRL_CORE_PAD_UART3_TXDRW320x0000 164C0x4A00 364C
CTRL_CORE_PAD_RGMII0_TXCRW320x0000 16500x4A00 3650
CTRL_CORE_PAD_RGMII0_TXCTLRW320x0000 16540x4A00 3654
CTRL_CORE_PAD_RGMII0_TXD3RW320x0000 16580x4A00 3658
CTRL_CORE_PAD_RGMII0_TXD2RW320x0000 165C0x4A00 365C
CTRL_CORE_PAD_RGMII0_TXD1RW320x0000 16600x4A00 3660
CTRL_CORE_PAD_RGMII0_TXD0RW320x0000 16640x4A00 3664
CTRL_CORE_PAD_RGMII0_RXCRW320x0000 16680x4A00 3668
CTRL_CORE_PAD_RGMII0_RXCTLRW320x0000 166C0x4A00 366C
CTRL_CORE_PAD_RGMII0_RXD3RW320x0000 16700x4A00 3670
CTRL_CORE_PAD_RGMII0_RXD2RW320x0000 16740x4A00 3674
CTRL_CORE_PAD_RGMII0_RXD1RW320x0000 16780x4A00 3678
CTRL_CORE_PAD_RGMII0_RXD0RW320x0000 167C0x4A00 367C
CTRL_CORE_PAD_USB1_DRVVBUSRW320x0000 16800x4A00 3680
CTRL_CORE_PAD_USB2_DRVVBUSRW320x0000 16840x4A00 3684
CTRL_CORE_PAD_GPIO6_14RW320x0000 16880x4A00 3688
CTRL_CORE_PAD_GPIO6_15RW320x0000 168C0x4A00 368C
CTRL_CORE_PAD_GPIO6_16RW320x0000 16900x4A00 3690
CTRL_CORE_PAD_XREF_CLK0RW320x0000 16940x4A00 3694
CTRL_CORE_PAD_XREF_CLK1RW320x0000 16980x4A00 3698
CTRL_CORE_PAD_XREF_CLK2RW320x0000 169C0x4A00 369C
CTRL_CORE_PAD_XREF_CLK3RW320x0000 16A00x4A00 36A0
CTRL_CORE_PAD_MCASP1_ACLKXRW320x0000 16A40x4A00 36A4
CTRL_CORE_PAD_MCASP1_FSXRW320x0000 16A80x4A00 36A8
CTRL_CORE_PAD_MCASP1_ACLKRRW320x0000 16AC0x4A00 36AC
CTRL_CORE_PAD_MCASP1_FSRRW320x0000 16B00x4A00 36B0
CTRL_CORE_PAD_MCASP1_AXR0RW320x0000 16B40x4A00 36B4
CTRL_CORE_PAD_MCASP1_AXR1RW320x0000 16B80x4A00 36B8
CTRL_CORE_PAD_MCASP1_AXR2RW320x0000 16BC0x4A00 36BC
CTRL_CORE_PAD_MCASP1_AXR3RW320x0000 16C00x4A00 36C0
CTRL_CORE_PAD_MCASP1_AXR4RW320x0000 16C40x4A00 36C4
CTRL_CORE_PAD_MCASP1_AXR5RW320x0000 16C80x4A00 36C8
CTRL_CORE_PAD_MCASP1_AXR6RW320x0000 16CC0x4A00 36CC
CTRL_CORE_PAD_MCASP1_AXR7RW320x0000 16D00x4A00 36D0
CTRL_CORE_PAD_MCASP1_AXR8RW320x0000 16D40x4A00 36D4
CTRL_CORE_PAD_MCASP1_AXR9RW320x0000 16D80x4A00 36D8
CTRL_CORE_PAD_MCASP1_AXR10RW320x0000 16DC0x4A00 36DC
CTRL_CORE_PAD_MCASP1_AXR11RW320x0000 16E00x4A00 36E0
CTRL_CORE_PAD_MCASP1_AXR12RW320x0000 16E40x4A00 36E4
CTRL_CORE_PAD_MCASP1_AXR13RW320x0000 16E80x4A00 36E8
CTRL_CORE_PAD_MCASP1_AXR14RW320x0000 16EC0x4A00 36EC
CTRL_CORE_PAD_MCASP1_AXR15RW320x0000 16F00x4A00 36F0
CTRL_CORE_PAD_MCASP2_ACLKXRW320x0000 16F40x4A00 36F4
CTRL_CORE_PAD_MCASP2_FSXRW320x0000 16F80x4A00 36F8
CTRL_CORE_PAD_MCASP2_ACLKRRW320x0000 16FC0x4A00 36FC
CTRL_CORE_PAD_MCASP2_FSRRW320x0000 17000x4A00 3700
CTRL_CORE_PAD_MCASP2_AXR0RW320x0000 17040x4A00 3704
CTRL_CORE_PAD_MCASP2_AXR1RW320x0000 17080x4A00 3708
CTRL_CORE_PAD_MCASP2_AXR2RW320x0000 170C0x4A00 370C
CTRL_CORE_PAD_MCASP2_AXR3RW320x0000 17100x4A00 3710
CTRL_CORE_PAD_MCASP2_AXR4RW320x0000 17140x4A00 3714
CTRL_CORE_PAD_MCASP2_AXR5RW320x0000 17180x4A00 3718
CTRL_CORE_PAD_MCASP2_AXR6RW320x0000 171C0x4A00 371C
CTRL_CORE_PAD_MCASP2_AXR7RW320x0000 17200x4A00 3720
CTRL_CORE_PAD_MCASP3_ACLKXRW320x0000 17240x4A00 3724
CTRL_CORE_PAD_MCASP3_FSXRW320x0000 17280x4A00 3728
CTRL_CORE_PAD_MCASP3_AXR0RW320x0000 172C0x4A00 372C
CTRL_CORE_PAD_MCASP3_AXR1RW320x0000 17300x4A00 3730
CTRL_CORE_PAD_MCASP4_ACLKXRW320x0000 17340x4A00 3734
CTRL_CORE_PAD_MCASP4_FSXRW320x0000 17380x4A00 3738
CTRL_CORE_PAD_MCASP4_AXR0RW320x0000 173C0x4A00 373C
CTRL_CORE_PAD_MCASP4_AXR1RW320x0000 17400x4A00 3740
CTRL_CORE_PAD_MCASP5_ACLKXRW320x0000 17440x4A00 3744
CTRL_CORE_PAD_MCASP5_FSXRW320x0000 17480x4A00 3748
CTRL_CORE_PAD_MCASP5_AXR0RW320x0000 174C0x4A00 374C
CTRL_CORE_PAD_MCASP5_AXR1RW320x0000 17500x4A00 3750
CTRL_CORE_PAD_MMC1_CLKRW320x0000 17540x4A00 3754
CTRL_CORE_PAD_MMC1_CMDRW320x0000 17580x4A00 3758
CTRL_CORE_PAD_MMC1_DAT0RW320x0000 175C0x4A00 375C
CTRL_CORE_PAD_MMC1_DAT1RW320x0000 17600x4A00 3760
CTRL_CORE_PAD_MMC1_DAT2RW320x0000 17640x4A00 3764
CTRL_CORE_PAD_MMC1_DAT3RW320x0000 17680x4A00 3768
CTRL_CORE_PAD_MMC1_SDCDRW320x0000 176C0x4A00 376C
CTRL_CORE_PAD_MMC1_SDWPRW320x0000 17700x4A00 3770
CTRL_CORE_PAD_GPIO6_10RW320x0000 17740x4A00 3774
CTRL_CORE_PAD_GPIO6_11RW320x0000 17780x4A00 3778
CTRL_CORE_PAD_MMC3_CLKRW320x0000 177C0x4A00 377C
CTRL_CORE_PAD_MMC3_CMDRW320x0000 17800x4A00 3780
CTRL_CORE_PAD_MMC3_DAT0RW320x0000 17840x4A00 3784
CTRL_CORE_PAD_MMC3_DAT1RW320x0000 17880x4A00 3788
CTRL_CORE_PAD_MMC3_DAT2RW320x0000 178C0x4A00 378C
CTRL_CORE_PAD_MMC3_DAT3RW320x0000 17900x4A00 3790
CTRL_CORE_PAD_MMC3_DAT4RW320x0000 17940x4A00 3794
CTRL_CORE_PAD_MMC3_DAT5RW320x0000 17980x4A00 3798
CTRL_CORE_PAD_MMC3_DAT6RW320x0000 179C0x4A00 379C
CTRL_CORE_PAD_MMC3_DAT7RW320x0000 17A00x4A00 37A0
CTRL_CORE_PAD_SPI1_SCLKRW320x0000 17A40x4A00 37A4
CTRL_CORE_PAD_SPI1_D1RW320x0000 17A80x4A00 37A8
CTRL_CORE_PAD_SPI1_D0RW320x0000 17AC0x4A00 37AC
CTRL_CORE_PAD_SPI1_CS0RW320x0000 17B00x4A00 37B0
CTRL_CORE_PAD_SPI1_CS1RW320x0000 17B40x4A00 37B4
CTRL_CORE_PAD_SPI1_CS2RW320x0000 17B80x4A00 37B8
CTRL_CORE_PAD_SPI1_CS3RW320x0000 17BC0x4A00 37BC
CTRL_CORE_PAD_SPI2_SCLKRW320x0000 17C00x4A00 37C0
CTRL_CORE_PAD_SPI2_D1RW320x0000 17C40x4A00 37C4
CTRL_CORE_PAD_SPI2_D0RW320x0000 17C80x4A00 37C8
CTRL_CORE_PAD_SPI2_CS0RW320x0000 17CC0x4A00 37CC
CTRL_CORE_PAD_DCAN1_TXRW320x0000 17D00x4A00 37D0
CTRL_CORE_PAD_DCAN1_RXRW320x0000 17D40x4A00 37D4
RESERVEDR320x0000 17D80x4A00 37D8
RESERVEDR320x0000 17DC0x4A00 37DC
CTRL_CORE_PAD_UART1_RXDRW320x0000 17E00x4A00 37E0
CTRL_CORE_PAD_UART1_TXDRW320x0000 17E40x4A00 37E4
CTRL_CORE_PAD_UART1_CTSNRW320x0000 17E80x4A00 37E8
CTRL_CORE_PAD_UART1_RTSNRW320x0000 17EC0x4A00 37EC
CTRL_CORE_PAD_UART2_RXDRW320x0000 17F00x4A00 37F0
CTRL_CORE_PAD_UART2_TXDRW320x0000 17F40x4A00 37F4
CTRL_CORE_PAD_UART2_CTSNRW320x0000 17F80x4A00 37F8
CTRL_CORE_PAD_UART2_RTSNRW320x0000 17FC0x4A00 37FC
CTRL_CORE_PAD_I2C1_SDARW320x0000 18000x4A00 3800
CTRL_CORE_PAD_I2C1_SCLRW320x0000 18040x4A00 3804
CTRL_CORE_PAD_I2C2_SDARW320x0000 18080x4A00 3808
CTRL_CORE_PAD_I2C2_SCLRW320x0000 180C0x4A00 380C
RESERVEDR320x0000 18100x4A00 3810
RESERVEDR320x0000 18140x4A00 3814
CTRL_CORE_PAD_WAKEUP0RW320x0000 18180x4A00 3818
CTRL_CORE_PAD_WAKEUP1RW320x0000 181C0x4A00 381C
CTRL_CORE_PAD_WAKEUP2RW320x0000 18200x4A00 3820
CTRL_CORE_PAD_WAKEUP3RW320x0000 18240x4A00 3824
CTRL_CORE_PAD_ON_OFFRW320x0000 18280x4A00 3828
CTRL_CORE_PAD_RTC_PORZRW320x0000 182C0x4A00 382C
CTRL_CORE_PAD_TMSRW320x0000 18300x4A00 3830
CTRL_CORE_PAD_TDIRW320x0000 18340x4A00 3834
CTRL_CORE_PAD_TDORW320x0000 18380x4A00 3838
CTRL_CORE_PAD_TCLKRW320x0000 183C0x4A00 383C
CTRL_CORE_PAD_TRSTNRW320x0000 18400x4A00 3840
CTRL_CORE_PAD_RTCKRW320x0000 18440x4A00 3844
CTRL_CORE_PAD_EMU0RW320x0000 18480x4A00 3848
CTRL_CORE_PAD_EMU1RW320x0000 184C0x4A00 384C
RESERVEDR320x0000 18500x4A00 3850
RESERVEDR320x0000 18540x4A00 3854
RESERVEDR320x0000 18580x4A00 3858
CTRL_CORE_PAD_RESETNRW320x0000 185C0x4A00 385C
CTRL_CORE_PAD_NMIN_DSPRW320x0000 18600x4A00 3860
CTRL_CORE_PAD_RSTOUTNRW320x0000 18640x4A00 3864
CTRL_CORE_PADCONF_WAKEUPEVENT_0R320x0000 18680x4A00 3868
CTRL_CORE_PADCONF_WAKEUPEVENT_1R320x0000 186C0x4A00 386C
CTRL_CORE_PADCONF_WAKEUPEVENT_2R320x0000 18700x4A00 3870
CTRL_CORE_PADCONF_WAKEUPEVENT_3R320x0000 18740x4A00 3874
CTRL_CORE_PADCONF_WAKEUPEVENT_4R320x0000 18780x4A00 3878
CTRL_CORE_PADCONF_WAKEUPEVENT_5R320x0000 187C0x4A00 387C
CTRL_CORE_PADCONF_WAKEUPEVENT_6R320x0000 18800x4A00 3880
CTRL_CORE_PADCONF_WAKEUPEVENT_7R320x0000 18840x4A00 3884
CTRL_CORE_PADCONF_WAKEUPEVENT_8R320x0000 18880x4A00 3888
RESERVED_j (j= 0 to 63)R320x0000 1A00 + (j*4)0x4A00 3A00 + (j*4)
RESERVEDR320x0000 1B000x4A00 3B00
RESERVEDR320x0000 1B040x4A00 3B04
CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_2R320x0000 1B080x4A00 3B08
CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_3R320x0000 1B0C0x4A00 3B0C
CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_4R320x0000 1B100x4A00 3B10
CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_5R320x0000 1B140x4A00 3B14
RESERVEDR320x0000 1B180x4A00 3B18
CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_1R320x0000 1B1C0x4A00 3B1C
CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_2R320x0000 1B200x4A00 3B20
CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_3R320x0000 1B240x4A00 3B24
CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_4R320x0000 1B280x4A00 3B28
CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_5R320x0000 1B2C0x4A00 3B2C
RESERVEDR320x0000 1B300x4A00 3B30
RESERVEDR320x0000 1B340x4A00 3B34
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_0R320x0000 1B380x4A00 3B38
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_1R320x0000 1B3C0x4A00 3B3C
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_2R320x0000 1B400x4A00 3B40
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_3R320x0000 1B440x4A00 3B44
CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_4R320x0000 1B480x4A00 3B48
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_0R320x0000 1B4C0x4A00 3B4C
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_1R320x0000 1B500x4A00 3B50
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_2R320x0000 1B540x4A00 3B54
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_3R320x0000 1B580x4A00 3B58
CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_4R320x0000 1B5C0x4A00 3B5C
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_0R320x0000 1B600x4A00 3B60
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_1R320x0000 1B640x4A00 3B64
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_2R320x0000 1B680x4A00 3B68
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_3R320x0000 1B6C0x4A00 3B6C
CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_4R320x0000 1B700x4A00 3B70
CTRL_CORE_LDOSRAM_CORE_4_VOLTAGE_CTRLRW320x0000 1B740x4A00 3B74
CTRL_CORE_LDOSRAM_CORE_5_VOLTAGE_CTRLRW320x0000 1B780x4A00 3B78
CTRL_CORE_LDOSRAM_DSPEVE_2_VOLTAGE_CTRLRW320x0000 1B7C0x4A00 3B7C
RESERVED_i (i = 0 to 32)R320x0000 1B80 + (i*4)0x4A00 3B80 +(i*4)
CTRL_CORE_SMA_SW_2RW320x0000 1C040x4A00 3C04
CTRL_CORE_SMA_SW_3RW320x0000 1C080x4A00 3C08
RESERVEDR320x0000 1C0C0x4A00 3C0C
RESERVEDR320x0000 1C100x4A00 3C10
CTRL_CORE_SMA_SW_6RW320x0000 1C140x4A00 3C14
CTRL_CORE_SMA_SW_7RW320x0000 1C180x4A00 3C18
CTRL_CORE_SMA_SW_8RW320x0000 1C1C0x4A00 3C1C
CTRL_CORE_SMA_SW_9RW320x0000 1C200x4A00 3C20
CTRL_CORE_PCIESS1_PCS1RW320x0000 1C240x4A00 3C24
CTRL_CORE_PCIESS1_PCS2RW320x0000 1C280x4A00 3C28
CTRL_CORE_PCIESS2_PCS1RW320x0000 1C2C0x4A00 3C2C
CTRL_CORE_PCIESS2_PCS2RW320x0000 1C300x4A00 3C30
CTRL_CORE_PCIE_PCSRW320x0000 1C340x4A00 3C34
CTRL_CORE_PCIE_PCS_REVISIONR320x0000 1C380x4A00 3C38
CTRL_CORE_PCIE_CONTROLRW320x0000 1C3C0x4A00 3C3C
CTRL_CORE_PHY_POWER_PCIESS1RW320x0000 1C400x4A00 3C40
CTRL_CORE_PHY_POWER_PCIESS2RW320x0000 1C440x4A00 3C44

18.5.4 CTRL_MODULE_CORE Register Description

Table 18-29 CTRL_CORE_STATUS
Address Offset0x0000 0134
Physical Address0x4A00 2134InstanceCTRL_MODULE_CORE
DescriptionControl Module Status Register
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDDEVICE_TYPERESERVED
BitsField NameDescriptionTypeReset
31:9RESERVEDR0x0
8:6DEVICE_TYPE

Device type captured at reset time.
Device type value sampled at power-on reset.

Read 0x3 = General Purpose (GP)

R0x3
5:0RESERVED

Reserved

R0x0
Table 18-30 CTRL_CORE_SEC_ERR_STATUS_FUNC_1
Address Offset0x0000 0148
Physical Address0x4A00 2148InstanceCTRL_MODULE_CORE
DescriptionFirewall Error Status functional Register 1
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE2_FW_ERROREVE1_FW_ERRORRESERVEDBB2D_FW_ERRORL4_WAKEUP_FW_ERRORRESERVEDDEBUGSS_FW_ERRORL4_CONFIG_FW_ERRORL4_PERIPH1_FW_ERRORRESERVEDDSS_FW_ERRORGPU_FW_ERRORRESERVEDIVAHD_SL2_FW_ERRORIPU1_FW_ERRORIVAHD_FW_ERROREMIF_FW_ERRORGPMC_FW_ERRORL3RAM1_FW_ERRORRESERVED
BitsField NameDescriptionTypeReset
31:30RESERVEDR0x0
29EVE2_FW_ERROR

EVE2 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
28EVE1_FW_ERROR

EVE1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
27:24RESERVEDR0x0
23BB2D_FW_ERROR

BB2D firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
22L4_WAKEUP_FW_ERROR

L4 wakeup firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
21:19RESERVEDR0x0
18DEBUGSS_FW_ERROR

DebugSS firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
17L4_CONFIG_FW_ERROR

L4 config firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
16L4_PERIPH1_FW_ERROR

L4 periph1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
15RESERVEDR0x0
14DSS_FW_ERROR

DSS firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
13GPU_FW_ERROR

GPU firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
12:7RESERVEDR0x0
6IVAHD_SL2_FW_ERROR

IVAHD SL2 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
5IPU1_FW_ERROR

IPU1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
4IVAHD_FW_ERROR

IVAHD firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
3EMIF_FW_ERROR

EMIF firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
2GPMC_FW_ERROR

GPMC firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
1L3RAM1_FW_ERROR

L3RAM1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
0RESERVEDR0x0
Table 18-31 CTRL_CORE_SEC_ERR_STATUS_DEBUG_1
Address Offset0x0000 0150
Physical Address0x4A00 2150InstanceCTRL_MODULE_CORE
DescriptionFirewall Error Status Debug Register 1
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE2_DBGFW_ERROREVE1_DBGFW_ERRORRESERVEDBB2D_DBGFW_ERRORL4_WAKEUP_DBGFW_ERRORRESERVEDDEBUGSS_DBGFW_ERRORL4_CONFIG_DBGFW_ERRORL4_PERIPH1_DBGFW_ERRORRESERVEDDSS_DBGFW_ERRORGPU_DBGFW_ERRORRESERVEDIVAHD_SL2_DBGFW_ERRORIPU1_DBGFW_ERRORIVAHD_DBGFW_ERROREMIF_DBGFW_ERRORGPMC_DBGFW_ERRORL3RAM1_DBGFW_ERRORRESERVED
BitsField NameDescriptionTypeReset
31:30RESERVEDR0x0
29EVE2_DBGFW_ERROR

EVE2 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
28EVE1_DBGFW_ERROR

EVE1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
27:24RESERVEDR0x0
23BB2D_DBGFW_ERROR

BB2D firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
22L4_WAKEUP_DBGFW_ERROR

L4 wakeup firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
21:19RESERVEDR0x0
18DEBUGSS_DBGFW_ERROR

DebugSS firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
17L4_CONFIG_DBGFW_ERROR

L4 config firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
16L4_PERIPH1_DBGFW_ERROR

L4 periph1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
15RESERVEDR0x0
14DSS_DBGFW_ERROR

DSS debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
13GPU_DBGFW_ERROR

GPU debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
12:7RESERVEDR0x0
6IVAHD_SL2_DBGFW_ERROR

IVAHD SL2 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
5IPU1_DBGFW_ERROR

IPU1 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
4IVAHD_DBGFW_ERROR

IVAHD debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
3EMIF_DBGFW_ERROR

EMIF debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
2GPMC_DBGFW_ERROR

GPMC debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
1L3RAM1_DBGFW_ERROR

L3RAM1 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
0RESERVEDR0x0
Table 18-32 CTRL_CORE_MPU_FORCEWRNP
Address Offset0x0000 015C
Physical Address0x4A00 215CInstanceCTRL_MODULE_CORE
DescriptionFORCE WRITE NON POSTED
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_FORCEWRNP
BitsField NameDescriptionTypeReset
31:1RESERVEDR0x0
0MPU_FORCEWRNP

Force mpu write non posted transactions

0x0 = disable force wrnp

0x1 = force wrnp

RW0x0
Table 18-33 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0
Address Offset0x0000 0194
Physical Address0x4A00 2194InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_0R0x0
Table 18-34 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1
Address Offset0x0000 0198
Physical Address0x4A00 2198InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_1R0x0
Table 18-35 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2
Address Offset0x0000 019C
Physical Address0x4A00 219CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_2R0x0
Table 18-36 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3
Address Offset0x0000 01A0
Physical Address0x4A00 21A0InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_3R0x0
Table 18-37 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4
Address Offset0x0000 01A4
Physical Address0x4A00 21A4InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_4R0x0
Table 18-38 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5
Address Offset0x0000 01A8
Physical Address0x4A00 21A8InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_5
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_5R0x0
Table 18-39 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0
Address Offset0x0000 01AC
Physical Address0x4A00 21ACInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_0R0x0
Table 18-40 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1
Address Offset0x0000 01B0
Physical Address0x4A00 21B0InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_1R0x0
Table 18-41 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2
Address Offset0x0000 01B4
Physical Address0x4A00 21B4InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_2R0x0
Table 18-42 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3
Address Offset0x0000 01B8
Physical Address0x4A00 21B8InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_3R0x0
Table 18-43 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4
Address Offset0x0000 01BC
Physical Address0x4A00 21BCInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_4R0x0
Table 18-44 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5
Address Offset0x0000 01C0
Physical Address0x4A00 21C0InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_5
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_5R0x0
Table 18-45 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6
Address Offset0x0000 01C4
Physical Address0x4A00 21C4InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_6
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_6R0x0
Table 18-46 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7
Address Offset0x0000 01C8
Physical Address0x4A00 21C8InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_7
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_7R0x0
Table 18-47 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0
Address Offset0x0000 01CC
Physical Address0x4A00 21CCInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_0R0x0
Table 18-48 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1
Address Offset0x0000 01D0
Physical Address0x4A00 21D0InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_1R0x0
Table 18-49 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2
Address Offset0x0000 01D4
Physical Address0x4A00 21D4InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_2R0x0
Table 18-50 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3
Address Offset0x0000 01D8
Physical Address0x4A00 21D8InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_3R0x0
Table 18-51 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4
Address Offset0x0000 01DC
Physical Address0x4A00 21DCInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_4R0x0
Table 18-52 CTRL_CORE_STD_FUSE_OPP_BGAP_GPU
Address Offset0x0000 01E0
Physical Address0x4A00 21E0InstanceCTRL_MODULE_CORE
DescriptionTrim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_BGAP_GPU_0STD_FUSE_OPP_BGAP_GPU_1STD_FUSE_OPP_BGAP_GPU_2STD_FUSE_OPP_BGAP_GPU_3
BitsField NameDescriptionTypeReset
31:24STD_FUSE_OPP_BGAP_GPU_0Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
23:16STD_FUSE_OPP_BGAP_GPU_1Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
15:8STD_FUSE_OPP_BGAP_GPU_2Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
7:0STD_FUSE_OPP_BGAP_GPU_3Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
Table 18-53 CTRL_CORE_STD_FUSE_OPP_BGAP_MPU
Address Offset0x0000 01E4
Physical Address0x4A00 21E4InstanceCTRL_MODULE_CORE
DescriptionTrim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_BGAP_MPU_0STD_FUSE_OPP_BGAP_MPU_1STD_FUSE_OPP_BGAP_MPU_2STD_FUSE_OPP_BGAP_MPU_3
BitsField NameDescriptionTypeReset
31:24STD_FUSE_OPP_BGAP_MPU_0Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
23:16STD_FUSE_OPP_BGAP_MPU_1Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
15:8STD_FUSE_OPP_BGAP_MPU_2Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
7:0STD_FUSE_OPP_BGAP_MPU_3Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
Table 18-54 CTRL_CORE_STD_FUSE_OPP_BGAP_CORE
Address Offset0x0000 01E8
Physical Address0x4A00 21E8InstanceCTRL_MODULE_CORE
DescriptionTrim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_BGAP_CORE_0STD_FUSE_OPP_BGAP_CORE_1STD_FUSE_OPP_BGAP_CORE_2STD_FUSE_OPP_BGAP_CORE_3
BitsField NameDescriptionTypeReset
31:24STD_FUSE_OPP_BGAP_CORE_0Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
23:16STD_FUSE_OPP_BGAP_CORE_1Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
15:8STD_FUSE_OPP_BGAP_CORE_2Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
7:0STD_FUSE_OPP_BGAP_CORE_3Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
Table 18-55 CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23
Address Offset0x0000 01EC
Physical Address0x4A00 21ECInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP BGAP. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_BGAP_MPU3STD_FUSE_OPP_BGAP_MPU2
BitsField NameDescriptionTypeReset
31:16STD_FUSE_OPP_BGAP_MPU3R0x0
15:0STD_FUSE_OPP_BGAP_MPU2R0x0
Table 18-56 CTRL_CORE_STD_FUSE_MPK_0
Address Offset0x0000 0220
Physical Address0x4A00 2220InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys. Root_public_key_hash [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_MPK_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_MPK_0R0x0
Table 18-57 CTRL_CORE_STD_FUSE_MPK_1
Address Offset0x0000 0224
Physical Address0x4A00 2224InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys. Root_public_key_hash [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_MPK_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_MPK_1R0x0
Table 18-58 CTRL_CORE_STD_FUSE_MPK_2
Address Offset0x0000 0228
Physical Address0x4A00 2228InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys. Root_public_key_hash [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_MPK_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_MPK_2R0x0
Table 18-59 CTRL_CORE_STD_FUSE_MPK_3
Address Offset0x0000 022C
Physical Address0x4A00 222CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys. Root_public_key_hash [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_MPK_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_MPK_3R0x0
Table 18-60 CTRL_CORE_STD_FUSE_MPK_4
Address Offset0x0000 0230
Physical Address0x4A00 2230InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys. Root_public_key_hash [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_MPK_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_MPK_4R0x0
Table 18-61 CTRL_CORE_STD_FUSE_MPK_5
Address Offset0x0000 0234
Physical Address0x4A00 2234InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys. Root_public_key_hash [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_MPK_5
BitsField NameDescriptionTypeReset
31:0STD_FUSE_MPK_5R0x0
Table 18-62 CTRL_CORE_STD_FUSE_MPK_6
Address Offset0x0000 0238
Physical Address0x4A00 2238InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys. Root_public_key_hash [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_MPK_6
BitsField NameDescriptionTypeReset
31:0STD_FUSE_MPK_6R0x0
Table 18-63 CTRL_CORE_STD_FUSE_MPK_7
Address Offset0x0000 023C
Physical Address0x4A00 223CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys. Root_public_key_hash [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_MPK_7
BitsField NameDescriptionTypeReset
31:0STD_FUSE_MPK_7R0x0
Table 18-64 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0
Address Offset0x0000 0240
Physical Address0x4A00 2240InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_LVT_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_LVT_0R0x0
Table 18-65 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1
Address Offset0x0000 0244
Physical Address0x4A00 2244InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_LVT_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_LVT_1R0x0
Table 18-66 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2
Address Offset0x0000 0248
Physical Address0x4A00 2248InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_LVT_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_LVT_2R0x0
Table 18-67 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3
Address Offset0x0000 024C
Physical Address0x4A00 224CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_LVT_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_LVT_3R0x0
Table 18-68 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4
Address Offset0x0000 0250
Physical Address0x4A00 2250InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_LVT_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_LVT_4R0x0
Table 18-69 CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5
Address Offset0x0000 0254
Physical Address0x4A00 2254InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_GPU_LVT_5
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_GPU_LVT_5R0x0
Table 18-70 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0
Address Offset0x0000 0258
Physical Address0x4A00 2258InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_LVT_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_LVT_0R0x0
Table 18-71 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1
Address Offset0x0000 025C
Physical Address0x4A00 225CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_LVT_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_LVT_1R0x0
Table 18-72 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2
Address Offset0x0000 0260
Physical Address0x4A00 2260InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_LVT_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_LVT_2R0x0
Table 18-73 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3
Address Offset0x0000 0264
Physical Address0x4A00 2264InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_LVT_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_LVT_3R0x0
Table 18-74 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4
Address Offset0x0000 0268
Physical Address0x4A00 2268InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_LVT_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_LVT_4R0x0
Table 18-75 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5
Address Offset0x0000 026C
Physical Address0x4A00 226CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_LVT_5
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_LVT_5R0x0
Table 18-76 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6
Address Offset0x0000 0270
Physical Address0x4A00 2270InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_LVT_6
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_LVT_6R0x0
Table 18-77 CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7
Address Offset0x0000 0274
Physical Address0x4A00 2274InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_MPU_LVT_7
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_MPU_LVT_7R0x0
Table 18-78 CTRL_CORE_CUST_FUSE_SWRV_0
Address Offset0x0000 02BC
Physical Address0x4A00 22BCInstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. Software Version Control [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_SWRV_0
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_SWRV_0R0x0
Table 18-79 CTRL_CORE_CUST_FUSE_SWRV_1
Address Offset0x0000 02C0
Physical Address0x4A00 22C0InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. Software Version Control [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_SWRV_1
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_SWRV_1R0x0
Table 18-80 CTRL_CORE_CUST_FUSE_SWRV_2
Address Offset0x0000 02C4
Physical Address0x4A00 22C4InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. Software Version Control [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_SWRV_2
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_SWRV_2R0x0
Table 18-81 CTRL_CORE_CUST_FUSE_SWRV_3
Address Offset0x0000 02C8
Physical Address0x4A00 22C8InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. Software Version Control [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_SWRV_3
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_SWRV_3R0x0
Table 18-82 CTRL_CORE_CUST_FUSE_SWRV_4
Address Offset0x0000 02CC
Physical Address0x4A00 22CCInstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. Software Version Control [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_SWRV_4
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_SWRV_4R0x0
Table 18-83 CTRL_CORE_CUST_FUSE_SWRV_5
Address Offset0x0000 02D0
Physical Address0x4A00 22D0InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. Software Version Control [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_SWRV_5
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_SWRV_5R0x0
Table 18-84 CTRL_CORE_CUST_FUSE_SWRV_6
Address Offset0x0000 02D4
Physical Address0x4A00 22D4InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. Software Version Control [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_SWRV_6
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_SWRV_6R0x0
Table 18-85 CTRL_CORE_DEV_CONF
Address Offset0x0000 0300
Physical Address0x4A00 2300InstanceCTRL_MODULE_CORE
DescriptionThis register is used to power down the USB2_PHY1
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUSBPHY_PD
BitsField NameDescriptionTypeReset
31:1RESERVED

Reserved

R0x0
0USBPHY_PDPower down the entire USB2_PHY1 (data, common module and UTMI).
0x0: Normal operation
0x1: Power down the USB2_PHY1		RW0x0
Table 18-86 CTRL_CORE_TEMP_SENSOR_MPU
Address Offset0x0000 032C
Physical Address0x4A00 232CInstanceCTRL_MODULE_CORE
DescriptionControl VBGAPTS temperature sensor and thermal comparator shutdown register
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBGAP_TMPSOFF_MPUBGAP_EOCZ_MPUBGAP_DTEMP_MPU
BitsField NameDescriptionTypeReset
31:12RESERVED

Reserved

R0x0
11BGAP_TMPSOFF_MPU

This bit indicates the temperature sensor state.
0x0: temperature sensor is ON
0x1: temperature sensor is OFF
NOTE: Software doesn't take care of this bit to get the temperature data. Only the BGAP_EOCZ_MPU bit is needed.

R0x1
10BGAP_EOCZ_MPU

ADC End of Conversion. Active low, when BGAP_DTEMP_MPU is valid.

R0x0
9:0BGAP_DTEMP_MPU

Temperature data from the ADC. Valid if EOCZ is low.

R0x0
Table 18-87 CTRL_CORE_TEMP_SENSOR_GPU
Address Offset0x0000 0330
Physical Address0x4A00 2330InstanceCTRL_MODULE_CORE
DescriptionControl VBGAPTS temperature sensor and thermal comparator shutdown register
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBGAP_TMPSOFF_GPUBGAP_EOCZ_GPUBGAP_DTEMP_GPU
BitsField NameDescriptionTypeReset
31:12RESERVED

Reserved

R0x0
11BGAP_TMPSOFF_GPU

This bit indicates the temperature sensor state.
0x0: temperature sensor is ON
0x1: temperature sensor is OFF
NOTE: Software doesn't take care of this bit to get the temperature data. Only the BGAP_EOCZ_GPU bit is needed.

R0x1
10BGAP_EOCZ_GPU

ADC End of Conversion. Active low, when BGAP_DTEMP_GPU is valid.

R0x0
9:0BGAP_DTEMP_GPU

Temperature data from the ADC. Valid if EOCZ is low.

R0x0
Table 18-88 CTRL_CORE_TEMP_SENSOR_CORE
Address Offset0x0000 0334
Physical Address0x4A00 2334InstanceCTRL_MODULE_CORE
DescriptionControl VBGAPTS temperature sensor and thermal comparator shutdown register
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBGAP_TMPSOFF_COREBGAP_EOCZ_COREBGAP_DTEMP_CORE
BitsField NameDescriptionTypeReset
31:12RESERVED

Reserved

R0x0
11BGAP_TMPSOFF_CORE

This bit indicates the temperature sensor state.
0x0: temperature sensor is ON
0x1: temperature sensor is OFF
NOTE: Software doesn't take care of this bit to get the temperature data. Only the BGAP_EOCZ_CORE bit is needed.

R0x1
10BGAP_EOCZ_CORE

ADC End of Conversion. Active low, when BGAP_DTEMP_CORE is valid.

R0x0
9:0BGAP_DTEMP_CORE

Temperature data from the ADC. Valid if EOCZ is low.

R0x0
Table 18-89 CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR
Address Offset0x0000 0358
Physical Address0x4A00 2358InstanceCTRL_MODULE_CORE
DescriptionCortex M4 register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDCORTEX_M4_MMUADDRTRANSLTR
BitsField NameDescriptionTypeReset
31:20RESERVED

Reserved

R0x0
19:0CORTEX_M4_MMUADDRTRANSLTR

Used to save the IPU AMMU translated/boot address

RW0x0
Table 18-90 CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR
Address Offset0x0000 035C
Physical Address0x4A00 235CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDCORTEX_M4_MMUADDRLOGICTR
BitsField NameDescriptionTypeReset
31:20RESERVED

Reserved

R0x0
19:0CORTEX_M4_MMUADDRLOGICTR

Used to save the IPU AMMU logical source address

RW0x0
Table 18-91 CTRL_CORE_HWOBS_CONTROL
Address Offset0x0000 0360
Physical Address0x4A00 2360InstanceCTRL_MODULE_CORE
DescriptionHW observability control. This register enables or disables HW observability outputs (to save power primarily)
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDHWOBS_CLKDIV_SEL_2HWOBS_CLKDIV_SEL_1RESERVEDHWOBS_CLKDIV_SELHWOBS_ALL_ZERO_MODEHWOBS_ALL_ONE_MODEHWOBS_MACRO_ENABLE
BitsField NameDescriptionTypeReset
31:19RESERVED

Reserved

R0x0
18:14HWOBS_CLKDIV_SEL_2

Clock divider selection on po_hwobs(2).

0x1 = output is not divided

0x2 = output is divided by 2

0x4 = output is divided by 4

0x8 = output is divided by 8

0x10 = output is divided by 16

RW0x0
13:9HWOBS_CLKDIV_SEL_1

Clock divider selection on po_hwobs(1).

0x1 = output is not divided

0x2 = output is divided by 2

0x4 = output is divided by 4

0x8 = output is divided by 8

0x10 = output is divided by 16

RW0x0
8RESERVEDReservedR0x0
7:3HWOBS_CLKDIV_SEL

Clock divider selection on po_hwobs(0).

0x1 = output is not divided

0x2 = output is divided by 2

0x4 = output is divided by 4

0x8 = output is divided by 8

0x10 = output is divided by 16

RW0x0
2HWOBS_ALL_ZERO_MODE

Used to gate observable signals. When set all outputs are set to zero (can be used to check the path from HW observability to external pads).

0x0 = hw observability ports are not gated

0x1 = hw observability ports are all set to 0

RW0x0
1HWOBS_ALL_ONE_MODE

Used to gate observable signals. When set all outputs are set to one (can be used to check the path from HW observability to external pads).

0x0 = hw observability ports are not gated

0x1 = hw observability ports are all set to 1

RW0x0
0HWOBS_MACRO_ENABLE

Used to gate observable signals coming from macros using the 32:bit HWOBS bus definition. When deasserted all outputs of the HWOBS busdef are set to zero.

0x0 = hw observability ports from macros are gated and set to zero

0x1 = hw observability ports from macros are not gated

RW0x0
Table 18-92 CTRL_CORE_PHY_POWER_USB
Address Offset0x0000 0370
Physical Address0x4A00 2370InstanceCTRL_MODULE_CORE
Descriptionphy_power_usb
TypeRW
313029282726252423222120191817161514131211109876543210
USB_PWRCTL_CLK_FREQUSB_PWRCTL_CLK_CMDRESERVED
BitsField NameDescriptionTypeReset
31:22USB_PWRCTL_CLK_FREQ

Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14.

RW0x0
21:14USB_PWRCTL_CLK_CMD

Powers up/down the USB3_PHY_TX and USB3_PHY_RX modules. This bit field is also used for partially power down these TX and RX modules. Each bit has the following meaning:

Bit[14] - 0x1: Powers-up the USB3_PHY_RX

Bit[15] - 0x1: Powers-up the USB3_PHY_TX

Bit[16] - A don’t care bit. Not used.

Bit[17] - A don’t care bit. Not used.

Bit[18] - 0x1: Disables the synchronized power-up of USB3_PHY_TX with USB3_PHY_RX. The TX power-up is independent of the RX power-up.

Bit[19] - 0x1: Disables the automatic power-cycling of USB3_PHY_RX in P3 power state when PLL_CLK stops and starts.

Bit[20] - 0x1: Partially powers-down the USB3_PHY_RX when it is in P3 power state. DCC, Phase interpolator, Equalizer are disabled.

Bit[21] - A don’t care bit. Not used.

RW0x0
13:0RESERVED

Reserved

R0x0
Table 18-93 CTRL_CORE_PHY_POWER_SATA
Address Offset0x0000 0374
Physical Address0x4A00 2374InstanceCTRL_MODULE_CORE
Descriptionphy_power_sata
TypeRW
313029282726252423222120191817161514131211109876543210
SATA_PWRCTL_CLK_FREQSATA_PWRCTL_CLK_CMDRESERVED
BitsField NameDescriptionTypeReset
31:22SATA_PWRCTL_CLK_FREQ

Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14.

RW0x0
21:14SATA_PWRCTL_CLK_CMD

Powers up/down the SATA_PHY_TX and SATA_PHY_RX modules.

0x0: Powers down SATA_PHY_TX and SATA_PHY_RX

0x1: Powers up SATA_PHY_RX

0x2: Powers up SATA_PHY_TX

0x3: Powers up SATA_PHY_TX and SATA_PHY_RX

0x4-0xFF: Reserved

RW0x0
13:0RESERVED

Reserved

R0x0
Table 18-94 CTRL_CORE_BANDGAP_MASK_1
Address Offset0x0000 0380
Physical Address0x4A00 2380InstanceCTRL_MODULE_CORE
Descriptionbgap_mask
TypeRW
313029282726252423222120191817161514131211109876543210
SIDLEMODECOUNTER_DELAYRESERVEDFREEZE_COREFREEZE_GPUFREEZE_MPUCLEAR_CORECLEAR_GPUCLEAR_MPURESERVEDMASK_HOT_COREMASK_COLD_COREMASK_HOT_GPUMASK_COLD_GPUMASK_HOT_MPUMASK_COLD_MPU
BitsField NameDescriptionTypeReset
31:30SIDLEMODE

sidlemode for bandgap

0x0 = No Idle

0x1 = Force Idle

0x2 = Smart Idle

0x3 = Reserved

RW0x0
29:27COUNTER_DELAY

Counter delay

0x0 = Imediat

0x1 = Delay of 1ms

0x2 = Delay of 10ms

0x3 = Delay of 100ms

0x4 = Delay of 250ms

0x5 = Delay of 500ms

RW0x0
26:24RESERVEDR0x0
23FREEZE_CORE

Freeze the FIFO CORE

0x0 = No operation

0x1 = Freeze the FIFO

RW0x0
22FREEZE_GPU

Freeze the FIFO GPU

0x0 = No operation

0x1 = Freeze the FIFO

RW0x0
21FREEZE_MPU

Freeze the FIFO MPU

0x0 = No operation

0x1 = Freeze the FIFO

RW0x0
20CLEAR_CORE

Reset the FIFO CORE

0x0 = No operation

0x1 = Reset the FIFO

RW0x0
19CLEAR_GPU

Reset the FIFO GPU

0x0 = No operation

0x1 = Reset the FIFO

RW0x0
18CLEAR_MPU

Reset the FIFO MPU

0x0 = No operation

0x1 = Reset the FIFO

RW0x0
17:6RESERVEDR0x0
5MASK_HOT_CORE

Mask for hot event CORE

0x0 = hot event is masked

0x1 = hot event is not masked

RW0x0
4MASK_COLD_CORE

Mask for cold event CORE

0x0 = cold event is masked

0x1 = cold event is not masked

RW0x0
3MASK_HOT_GPU

Mask for hot event GPU

0x0 = hot event is masked

0x1 = hot event is not masked

RW0x0
2MASK_COLD_GPU

Mask for cold event GPU

0x0 = cold event is masked

0x1 = cold event is not masked

RW0x0
1MASK_HOT_MPU

Mask for hot event MPU

0x0 = hot event is masked

0x1 = hot event is not masked

RW0x0
0MASK_COLD_MPU

Mask for cold event MPU

0x0 = cold event is masked

0x1 = cold event is not masked

RW0x0
Table 18-95 CTRL_CORE_BANDGAP_THRESHOLD_MPU
Address Offset0x0000 0384
Physical Address0x4A00 2384InstanceCTRL_MODULE_CORE
DescriptionBGAP THRESHOLD MPU
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTHOLD_HOT_MPURESERVEDTHOLD_COLD_MPU
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16THOLD_HOT_MPU

Value for the high temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
15:10RESERVEDR0x0
9:0THOLD_COLD_MPU

Value for the low temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
Table 18-96 CTRL_CORE_BANDGAP_THRESHOLD_GPU
Address Offset0x0000 0388
Physical Address0x4A00 2388InstanceCTRL_MODULE_CORE
DescriptionBGAP THRESHOLD MM
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTHOLD_HOT_GPURESERVEDTHOLD_COLD_GPU
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16THOLD_HOT_GPU

Value for the high temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
15:10RESERVEDR0x0
9:0THOLD_COLD_GPU

Value for the low temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
Table 18-97 CTRL_CORE_BANDGAP_THRESHOLD_CORE
Address Offset0x0000 038C
Physical Address0x4A00 238CInstanceCTRL_MODULE_CORE
DescriptionBGAP THRESHOLD CORE
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTHOLD_HOT_CORERESERVEDTHOLD_COLD_CORE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16THOLD_HOT_CORE

Value for the high temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
15:10RESERVEDR0x0
9:0THOLD_COLD_CORE

Value for the low temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
Table 18-98 CTRL_CORE_BANDGAP_TSHUT_MPU
Address Offset0x0000 0390
Physical Address0x4A00 2390InstanceCTRL_MODULE_CORE
DescriptionBGAP TSHUT THRESHOLD MPU
TypeR
313029282726252423222120191817161514131211109876543210
TSHUT_MUXCTRL_MPURESERVEDTSHUT_HOT_MPURESERVEDTSHUT_COLD_MPU
BitsField NameDescriptionTypeReset
31TSHUT_MUXCTRL_MPUWriting a ‘1’ to this field allows SW to override the TSHUT_HOT and TSHUT_COLD values that are set by default in efuseRW0x0
30:26RESERVEDR0x0
25:16TSHUT_HOT_MPUControls the TSHUT_HOT reset threshold, which protects the device from thermal runaway and potential device damage. The register defaults to 123°C. Software override of this register value is not recommended, and should only be done with extreme caution as damage to the device can occur above the default setting.RW0x0
15:10RESERVEDR0x0
9:0TSHUT_COLD_MPU

Controls the TSHUT_COLD reset threshold, which is the limit where the TSHUT comparator releases the device from reset after cooling from a TSHUT condition. The register defaults to 105°C. Software override of this register value is not recommended, and should only be done with extreme caution.

RW0x0
Table 18-99 CTRL_CORE_BANDGAP_TSHUT_GPU
Address Offset0x0000 0394
Physical Address0x4A00 2394InstanceCTRL_MODULE_CORE
DescriptionBGAP TSHUT THRESHOLD GPU
TypeR
313029282726252423222120191817161514131211109876543210
TSHUT_MUXCTRL_GPURESERVEDTSHUT_HOT_GPURESERVEDTSHUT_COLD_GPU
BitsField NameDescriptionTypeReset
31TSHUT_MUXCTRL_GPU

Writing a ‘1’ to this field allows SW to override the TSHUT_HOT and TSHUT_COLD values that are set by default in efuse.

RW0x0
30:26RESERVEDR0x0
25:16TSHUT_HOT_GPU

Controls the TSHUT_HOT reset threshold, which protects the device from thermal runaway and potential device damage. The register defaults to 123°C. Software override of this register value is not recommended, and should only be done with extreme caution as damage to the device can occur above the default setting

RW0x0
15:10RESERVEDR0x0
9:0TSHUT_COLD_GPU

Controls the TSHUT_COLD reset threshold, which is the limit where the TSHUT comparator releases the device from reset after cooling from a TSHUT condition. The register defaults to 105°C. Software override of this register value is not recommended, and should only be done with extreme caution.

RW0x0
Table 18-100 CTRL_CORE_BANDGAP_TSHUT_CORE
Address Offset0x0000 0398
Physical Address0x4A00 2398InstanceCTRL_MODULE_CORE
DescriptionBGAP TSHUT THRESHOLD CORE
TypeR
313029282726252423222120191817161514131211109876543210
TSHUT_MUXCTRL_CORERESERVEDTSHUT_HOT_CORERESERVEDTSHUT_COLD_CORE
BitsField NameDescriptionTypeReset
31TSHUT_MUXCTRL_CORE

Writing a ‘1’ to this field allows SW to override the TSHUT_HOT and TSHUT_COLD values that are set by default in efuse.

RW0x0
30:26RESERVEDR0x0
25:16TSHUT_HOT_CORE

Controls the TSHUT_HOT reset threshold, which protects the device from thermal runaway and potential device damage. The register defaults to 123°C. Software override of this register value is not recommended, and should only be done with extreme caution as damage to the device can occur above the default setting.

RW0x0
15:10RESERVEDR0x0
9:0TSHUT_COLD_CORE

Controls the TSHUT_COLD reset threshold, which is the limit where the TSHUT comparator releases the device from reset after cooling from a TSHUT condition. The register defaults to 105°C. Software override of this register value is not recommended, and should only be done with extreme caution.

RW0x0
Table 18-101 CTRL_CORE_BANDGAP_STATUS_1
Address Offset0x0000 03A8
Physical Address0x4A00 23A8InstanceCTRL_MODULE_CORE
DescriptionBGAP STATUS
TypeR
313029282726252423222120191817161514131211109876543210
ALERTRESERVEDHOT_CORECOLD_COREHOT_GPUCOLD_GPUHOT_MPUCOLD_MPU
BitsField NameDescriptionTypeReset
31ALERT

Alert temperature when '1'

R0x0
30:6RESERVEDR0x0
5HOT_CORE

Event for hot temperature mpu bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
4COLD_CORE

Event for cold temperature mpu bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
3HOT_GPU

Event for hot temperature gpu bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
2COLD_GPU

Event for cold temperature gpu bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
1HOT_MPU

Event for hot temperature core bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
0COLD_MPU

Event for cold temperature core bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
Table 18-102 CTRL_CORE_SATA_EXT_MODE
Address Offset0x0000 03AC
Physical Address0x4A00 23ACInstanceCTRL_MODULE_CORE
DescriptionSATA EXTENDED MODE
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSATA_EXTENDED_MODE
BitsField NameDescriptionTypeReset
31:1RESERVEDR0x0
0SATA_EXTENDED_MODE

sata extended mode

0x0 = no extended mode

0x1 = extended mode

RW0x0
Table 18-103 CTRL_CORE_DTEMP_MPU_0
Address Offset0x0000 03C0
Physical Address0x4A00 23C0InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE MPU DOMAIN. Most recent sample
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_MPU_0DTEMP_TEMPERATURE_MPU_0
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_MPU_0

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_MPU_0

temperature

R0x0
Table 18-104 CTRL_CORE_DTEMP_MPU_1
Address Offset0x0000 03C4
Physical Address0x4A00 23C4InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE MPU DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_MPU_1DTEMP_TEMPERATURE_MPU_1
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_MPU_1

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_MPU_1

temperature

R0x0
Table 18-105 CTRL_CORE_DTEMP_MPU_2
Address Offset0x0000 03C8
Physical Address0x4A00 23C8InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE MPU DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_MPU_2DTEMP_TEMPERATURE_MPU_2
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_MPU_2

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_MPU_2

temperature

R0x0
Table 18-106 CTRL_CORE_DTEMP_MPU_3
Address Offset0x0000 03CC
Physical Address0x4A00 23CCInstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE MPU DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_MPU_3DTEMP_TEMPERATURE_MPU_3
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_MPU_3

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_MPU_3

temperature

R0x0
Table 18-107 CTRL_CORE_DTEMP_MPU_4
Address Offset0x0000 03D0
Physical Address0x4A00 23D0InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE MPU DOMAIN. Oldest sample
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_MPU_4DTEMP_TEMPERATURE_MPU_4
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_MPU_4

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_MPU_4

temperature

R0x0
Table 18-108 CTRL_CORE_DTEMP_GPU_0
Address Offset0x0000 03D4
Physical Address0x4A00 23D4InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE GPU DOMAIN. Most recent sample.
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_GPU_0DTEMP_TEMPERATURE_GPU_0
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_GPU_0

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_GPU_0

temperature

R0x0
Table 18-109 CTRL_CORE_DTEMP_GPU_1
Address Offset0x0000 03D8
Physical Address0x4A00 23D8InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE GPU DOMAIN.
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_GPU_1DTEMP_TEMPERATURE_GPU_1
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_GPU_1

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_GPU_1

temperature

R0x0
Table 18-110 CTRL_CORE_DTEMP_GPU_2
Address Offset0x0000 03DC
Physical Address0x4A00 23DCInstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE GPU DOMAIN.
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_GPU_2DTEMP_TEMPERATURE_GPU_2
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_GPU_2

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_GPU_2

temperature

R0x0
Table 18-111 CTRL_CORE_DTEMP_GPU_3
Address Offset0x0000 03E0
Physical Address0x4A00 23E0InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE GPU DOMAIN.
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_GPU_3DTEMP_TEMPERATURE_GPU_3
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_GPU_3

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_GPU_3

temperature

R0x0
Table 18-112 CTRL_CORE_DTEMP_GPU_4
Address Offset0x0000 03E4
Physical Address0x4A00 23E4InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE GPU DOMAIN. Oldest sample.
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_GPU_4DTEMP_TEMPERATURE_GPU_4
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_GPU_4

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_GPU_4

temperature

R0x0
Table 18-113 CTRL_CORE_DTEMP_CORE_0
Address Offset0x0000 03E8
Physical Address0x4A00 23E8InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE CORE DOMAIN. Most recent sample.
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_CORE_0DTEMP_TEMPERATURE_CORE_0
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_CORE_0

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_CORE_0

temperature

R0x0
Table 18-114 CTRL_CORE_DTEMP_CORE_1
Address Offset0x0000 03EC
Physical Address0x4A00 23ECInstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE CORE DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_CORE_1DTEMP_TEMPERATURE_CORE_1
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_CORE_1

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_CORE_1

temperature

R0x0
Table 18-115 CTRL_CORE_DTEMP_CORE_2
Address Offset0x0000 03F0
Physical Address0x4A00 23F0InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE CORE DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_CORE_2DTEMP_TEMPERATURE_CORE_2
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_CORE_2

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_CORE_2

temperature

R0x0
Table 18-116 CTRL_CORE_DTEMP_CORE_3
Address Offset0x0000 03F4
Physical Address0x4A00 23F4InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE CORE DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_CORE_3DTEMP_TEMPERATURE_CORE_3
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_CORE_3

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_CORE_3

temperature

R0x0
Table 18-117 CTRL_CORE_DTEMP_CORE_4
Address Offset0x0000 03F8
Physical Address0x4A00 23F8InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE CORE DOMAIN. Oldest sample.
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_CORE_4DTEMP_TEMPERATURE_CORE_4
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_CORE_4

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_CORE_4

temperature

R0x0
Table 18-118 CTRL_CORE_SMA_SW_0
Address Offset0x0000 03FC
Physical Address0x4A00 23FCInstanceCTRL_MODULE_CORE
DescriptionOCP Spare Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSATA_PLL_SOFT_RESETRESERVEDISOLATEEMIF2_CKE_GATING_CTRLEMIF1_CKE_GATING_CTRL
BitsField NameDescriptionTypeReset
31:19RESERVEDR0x0
18SATA_PLL_SOFT_RESETSoftware reset control for SATA PLLRW0x0
17:3RESERVEDR0x0
2ISOLATEThis bit is used during the isolation/de-isolation sequence described in Isolation Requirements.RW0x0
1EMIF2_CKE_GATING_CTRLForces the EMIF2 CKE pad to tri-state.
0x0: The CKE pad is not in tri-state and can be controlled by EMIF2
0x1: The CKE pad is in tri-state		RW0x0
0EMIF1_CKE_GATING_CTRLForces the EMIF1 CKE pad to tri-state.
0x0: The CKE pad is not in tri-state and can be controlled by EMIF1
0x1: The CKE pad is in tri-state		RW0x0
Table 18-119 CTRL_CORE_SEC_ERR_STATUS_FUNC_2
Address Offset0x0000 0414
Physical Address0x4A00 2414InstanceCTRL_MODULE_CORE
DescriptionFirewall Error Status functional Register 2
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTC1_EDMA_FW_ERRORRESERVEDQSPI_FW_ERRORRESERVEDTPCC_EDMA_FW_ERRORTC0_EDMA_FW_ERRORRESERVEDMCASP3_FW_ERRORMCASP2_FW_ERRORMCASP1_FW_ERRORVCP2_FW_ERRORVCP1_FW_ERRORPCIESS2_FW_ERRORPCIESS1_FW_ERRORIPU2_FW_ERRORL4_PERIPH3_FW_ERRORL4_PERIPH2_FW_ERRORL3RAM3_FW_ERRORL3RAM2_FW_ERRORDSP2_FW_ERRORDSP1_FW_ERROR
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26TC1_EDMA_FW_ERROR

EDMA TC1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
25:23RESERVEDR0x0
22QSPI_FW_ERROR

QSPI firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
21:18RESERVEDR
17TPCC_EDMA_FW_ERROR

EDMA TPCC firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
16TC0_EDMA_FW_ERROR

EDMA TC0 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
15:14RESERVEDR
13MCASP3_FW_ERROR

McASP3 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
12MCASP2_FW_ERROR

McASP2 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
11MCASP1_FW_ERROR

McASP1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
10VCP2_FW_ERROR

VCP2 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
9VCP1_FW_ERROR

VCP1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
8PCIESS2_FW_ERROR

PCIeSS2 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
7PCIESS1_FW_ERROR

PCIeSS1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
6IPU2_FW_ERROR

IPU2 firewall.

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
5L4_PERIPH3_FW_ERROR

L4 periph3 init firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
4L4_PERIPH2_FW_ERROR

L4 periph2 init firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
3L3RAM3_FW_ERROR

L3RAM3 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
2L3RAM2_FW_ERROR

L3RAM2 target firewall.

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
1DSP2_FW_ERROR

DSP2 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
0DSP1_FW_ERROR

DSP1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
Table 18-120 CTRL_CORE_SEC_ERR_STATUS_DEBUG_2
Address Offset0x0000 041C
Physical Address0x4A00 241CInstanceCTRL_MODULE_CORE
DescriptionFirewall Error Status debug Register 2
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTC1_EDMA_DBGFW_ERRORRESERVEDQSPI_DBGFW_ERRORRESERVEDTPCC_EDMA_DBGFW_ERRORTC0_EDMA_DBGFW_ERRORRESERVEDMCASP3_DBGFW_ERRORMCASP2_DBGFW_ERRORMCASP1_DBGFW_ERRORVCP2_DBGFW_ERRORVCP1_DBGFW_ERRORPCIESS2_DBGFW_ERRORPCIESS1_DBGFW_ERRORIPU2_DBGFW_ERRORL4_PERIPH3_DBGFW_ERRORL4_PERIPH2_DBGFW_ERRORL3RAM3_DBGFW_ERRORL3RAM2_DBGFW_ERRORDSP2_DBGFW_ERRORDSP1_DBGFW_ERROR
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26TC1_EDMA_DBGFW_ERROR

EDMA TC1 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
25:23RESERVEDR0x0
22QSPI_DBGFW_ERROR

QSPI debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
21:18RESERVEDR0x0
17TPCC_EDMA_DBGFW_ERROR

EDMA TPCC debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
16TC0_EDMA_DBGFW_ERROR

EDMA TC0 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
15:14RESERVEDR0x0
13MCASP3_DBGFW_ERROR

McASP3 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
12MCASP2_DBGFW_ERROR

McASP2 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
11MCASP1_DBGFW_ERROR

McASP1 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
10VCP2_DBGFW_ERROR

VCP2 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
9VCP1_DBGFW_ERROR

VCP1 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
8PCIESS2_DBGFW_ERROR

PCIeSS2 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
7PCIESS1_DBGFW_ERROR

PCIeSS1 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
6IPU2_DBGFW_ERROR

IPU2 debug firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
5L4_PERIPH3_DBGFW_ERROR

L4 periph3 init firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
4L4_PERIPH2_DBGFW_ERROR

L4 periph2 init firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
3L3RAM3_DBGFW_ERROR

L3RAM3 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
2L3RAM2_DBGFW_ERROR

L3RAM2 target debug firewall.

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
1DSP2_DBGFW_ERROR

DSP2 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
0DSP1_DBGFW_ERROR

DSP1 firewall

0x0 = No error from firewall

0x1 = Error from firewall

RW
W1toClr		0x0
Table 18-121 CTRL_CORE_EMIF_INITIATOR_PRIORITY_1
Address Offset0x0000 0420
Physical Address0x4A00 2420InstanceCTRL_MODULE_CORE
DescriptionRegister for priority settings for EMIF arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_EMIF_PRIORITYRESERVEDDSP1_MDMA_EMIF_PRIORITYRESERVEDDSP1_CFG_EMIF_PRIORITYRESERVEDDSP1_EDMA_EMIF_PRIORITYRESERVEDDSP2_EDMA_EMIF_PRIORITYRESERVEDDSP2_CFG_EMIF_PRIORITY
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30:28MPU_EMIF_PRIORITY

MPU priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
27:19RESERVEDR0x88
18:16DSP1_MDMA_EMIF_PRIORITY

DSP1 MDMA priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
15RESERVEDR0x0
14:12DSP1_CFG_EMIF_PRIORITY

DSP1 CFG priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
11RESERVEDR0x0
10:8DSP1_EDMA_EMIF_PRIORITY

DSP1 EDMA priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
7RESERVEDR0x0
6:4DSP2_EDMA_EMIF_PRIORITY

DSP2 EDMA priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
3RESERVEDR0x0
2:0DSP2_CFG_EMIF_PRIORITY

DSP2 CFG priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
Table 18-122 CTRL_CORE_EMIF_INITIATOR_PRIORITY_2
Address Offset0x0000 0424
Physical Address0x4A00 2424InstanceCTRL_MODULE_CORE
DescriptionRegister for priority settings for EMIF arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_MDMA_EMIF_PRIORITYRESERVEDIVA_ICONT1_EMIF_PRIORITYRESERVEDEVE1_TC0_EMIF_PRIORITYRESERVEDEVE2_TC0_EMIF_PRIORITYRESERVED
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30:28DSP2_MDMA_EMIF_PRIORITY

DSP2 MDMA priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
27RESERVEDR0x0
26:24IVA_ICONT1_EMIF_PRIORITY

IVA ICONT1 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
23:19RESERVEDR0x0
18:16EVE1_TC0_EMIF_PRIORITY

EVE1 TC0 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
15RESERVEDR0x0
14:12EVE2_TC0_EMIF_PRIORITY

EVE2 TC0 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
11:0RESERVEDR0x444
Table 18-123 CTRL_CORE_EMIF_INITIATOR_PRIORITY_3
Address Offset0x0000 0428
Physical Address0x4A00 2428InstanceCTRL_MODULE_CORE
DescriptionRegister for priority settings for EMIF arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_EMIF_PRIORITYRESERVEDIPU2_EMIF_PRIORITYRESERVEDDMA_SYSTEM_EMIF_PRIORITYRESERVEDEDMA_TC0_EMIF_PRIORITY
BitsField NameDescriptionTypeReset
31:19RESERVEDR0x888
18:16IPU1_EMIF_PRIORITY

IPU1 priority setting

0x0 = highest prioroty

0x7 = lowest priority

RW0x4
15RESERVEDR0x0
14:12IPU2_EMIF_PRIORITY

IPU2 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
11RESERVEDR0x0
10:8DMA_SYSTEM_EMIF_PRIORITY

DMA SYSTEM priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
7:3RESERVEDR0x8
2:0EDMA_TC0_EMIF_PRIORITY

EDMA TC0 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
Table 18-124 CTRL_CORE_EMIF_INITIATOR_PRIORITY_4
Address Offset0x0000 042C
Physical Address0x4A00 242CInstanceCTRL_MODULE_CORE
DescriptionRegister for priority settings for EMIF arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEDMA_TC1_EMIF_PRIORITYRESERVEDDSS_EMIF_PRIORITYRESERVEDMLB_MMU1_EMIF_PRIORITYRESERVEDPCIESS1_EMIF_PRIORITYRESERVEDPCIESS2_EMIF_PRIORITYRESERVEDVIP1_P1_P2_EMIF_PRIORITYRESERVEDVIP2_P1_P2_EMIF_PRIORITYRESERVEDVIP3_P1_P2_EMIF_PRIORITY
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30:28EDMA_TC1_EMIF_PRIORITY

EDMA TC1 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
27RESERVEDR0x0
26:24DSS_EMIF_PRIORITY

DSS priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
23RESERVEDR0x0
22:20MLB_MMU1_EMIF_PRIORITY

MLB, MMU1 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
19RESERVEDR0x0
18:16PCIESS1_EMIF_PRIORITY

PCIeSS1 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
15RESERVEDR0x0
14:12PCIESS2_EMIF_PRIORITY

PCIeSS2 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
11RESERVEDR0x0
10:8VIP1_P1_P2_EMIF_PRIORITY

VIP1 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
7RESERVEDR0x0
6:4VIP2_P1_P2_EMIF_PRIORITY

VIP2 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
3RESERVEDR0x0
2:0VIP3_P1_P2_EMIF_PRIORITY

VIP3 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
Table 18-125 CTRL_CORE_EMIF_INITIATOR_PRIORITY_5
Address Offset0x0000 0430
Physical Address0x4A00 2430InstanceCTRL_MODULE_CORE
DescriptionRegister for priority settings for EMIF arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVPE_P1_P2_EMIF_PRIORITYRESERVEDMMC1_GPU_P1_EMIF_PRIORITYRESERVEDMMC2_GPU_P2_EMIF_PRIORITYRESERVEDBB2D_P1_P2_EMIF_PRIORITYRESERVEDGMAC_SW_EMIF_PRIORITYRESERVEDUSB1_EMIF_PRIORITYRESERVEDUSB2_EMIF_PRIORITYRESERVEDUSB3_EMIF_PRIORITY
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30:28VPE_P1_P2_EMIF_PRIORITY

VPE priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
27RESERVEDR0x0
26:24MMC1_GPU_P1_EMIF_PRIORITY

MMC1, GPU P1 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
23RESERVEDR0x0
22:20MMC2_GPU_P2_EMIF_PRIORITY

MMC2, GPU P2 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
19RESERVEDR0x0
18:16BB2D_P1_P2_EMIF_PRIORITY

BB2D priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
15RESERVEDR0x0
14:12GMAC_SW_EMIF_PRIORITY

GMAC_SW priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
11RESERVEDR0x0
10:8USB1_EMIF_PRIORITY

USB1 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
7RESERVEDR0x0
6:4USB2_EMIF_PRIORITY

USB2 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
3RESERVEDR0x0
2:0USB3_EMIF_PRIORITY

USB3 priority setting

0x0 = highest priority

0x7 = lowest priorty

RW0x4
Table 18-126 CTRL_CORE_EMIF_INITIATOR_PRIORITY_6
Address Offset0x0000 0434
Physical Address0x4A00 2434InstanceCTRL_MODULE_CORE
DescriptionRegister for priority settings for EMIF arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUSB4_EMIF_PRIORITYRESERVEDSATA_EMIF_PRIORITYRESERVEDEVE1_TC1_EMIF_PRIORITYRESERVEDEVE2_TC1_EMIF_PRIORITYRESERVED
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30:28USB4_EMIF_PRIORITY

USB4 priority setting

0x0 = highest priority

0x7 = lowest prority

RW0x4
27:15RESERVEDR0x888
14:12SATA_EMIF_PRIORITY

SATA priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
11RESERVEDR0x0
10:8EVE1_TC1_EMIF_PRIORITY

EVE1 TC1 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
7RESERVEDR0x0
6:4EVE2_TC1_EMIF_PRIORITY

EVE2 TC1 priority setting

0x0 = highest priority

0x7 = lowest priority

RW0x4
3:0RESERVEDR0x4
Table 18-127 CTRL_CORE_L3_INITIATOR_PRESSURE_1
Address Offset0x0000 043C
Physical Address0x4A00 243CInstanceCTRL_MODULE_CORE
DescriptionRegister for pressure settings for L3 arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_L3_PRESSURERESERVEDDSP1_CFG_L3_PRESSURERESERVEDDSP2_CFG_L3_PRESSURERESERVED
BitsField NameDescriptionTypeReset
31:28RESERVEDR0x0
27:26MPU_L3_PRESSURE

MPU pressure setting

0x0 = lowest

0x3 = highest

RW0x0
25:19RESERVEDR0x0
18:17DSP1_CFG_L3_PRESSURE

DSP1 CFG pressure setting

0x0 = lowest

0x3 = highest

RW0x0
16:11RESERVEDR0x0
10:9DSP2_CFG_L3_PRESSURE

DSP2 CFG pressure setting

0x0 = lowest

0x3 = highest

RW0x0
8:0RESERVEDR0x0
Table 18-128 CTRL_CORE_L3_INITIATOR_PRESSURE_2
Address Offset0x0000 0440
Physical Address0x4A00 2440InstanceCTRL_MODULE_CORE
DescriptionRegister for pressure settings for L3 arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_L3_PRESSURERESERVEDIPU2_L3_PRESSURERESERVED
BitsField NameDescriptionTypeReset
31:14RESERVEDR0x0
13:12IPU1_L3_PRESSURE

IPU1 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
11RESERVEDR0x0
10:9IPU2_L3_PRESSURE

IPU2 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
8:0RESERVEDR0x0
Table 18-129 CTRL_CORE_L3_INITIATOR_PRESSURE_4
Address Offset0x0000 0448
Physical Address0x4A00 2448InstanceCTRL_MODULE_CORE
DescriptionRegister for pressure settings for L3 arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPU_P1_L3_PRESSURERESERVEDGPU_P2_L3_PRESSURERESERVED
BitsField NameDescriptionTypeReset
31:25RESERVED

Reserved

R0x0
24:23GPU_P1_L3_PRESSURE

GPU P1 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
22RESERVEDR0x0
21:20GPU_P2_L3_PRESSURE

GPU P2 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
19:0RESERVEDR0x0
Table 18-130 CTRL_CORE_L3_INITIATOR_PRESSURE_5
Address Offset0x0000 044C
Physical Address0x4A00 244CInstanceCTRL_MODULE_CORE
DescriptionRegister for pressure settings for L3 arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSATA_L3_PRESSURERESERVEDMMC1_L3_PRESSURE
BitsField NameDescriptionTypeReset
31:5RESERVEDR0x0
4:3SATA_L3_PRESSURE

SATA pressure setting

0x0 = lowest

0x3 = highest

RW0x0
2RESERVEDR0x0
1:0MMC1_L3_PRESSURE

MMC1 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
Table 18-131 CTRL_CORE_L3_INITIATOR_PRESSURE_6
Address Offset0x0000 0450
Physical Address0x4A00 2450InstanceCTRL_MODULE_CORE
DescriptionRegister for pressure settings for L3 arbitration
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC2_L3_PRESSUREUSB1_L3_PRESSURERESERVEDUSB2_L3_PRESSURERESERVEDUSB3_L3_PRESSURERESERVEDUSB4_L3_PRESSURERESERVED
BitsField NameDescriptionTypeReset
31:19RESERVEDR0x0
18:17MMC2_L3_PRESSURE

MMC2 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
16:15USB1_L3_PRESSURE

USB1 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
14RESERVEDR0x0
13:12USB2_L3_PRESSURE

USB2 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
11RESERVEDR0x0
10:9USB3_L3_PRESSURE

USB3 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
8RESERVEDR0x0
7:6USB4_L3_PRESSURE

USB4 pressure setting

0x0 = lowest

0x3 = highest

RW0x0
5:0RESERVEDR0x0
Table 18-132 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0
Address Offset0x0000 0458
Physical Address0x4A00 2458InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_iva [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_0R0x0
Table 18-133 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1
Address Offset0x0000 045C
Physical Address0x4A00 245CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_iva [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_1R0x0
Table 18-134 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2
Address Offset0x0000 0460
Physical Address0x4A00 2460InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_iva [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_2R0x0
Table 18-135 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3
Address Offset0x0000 0464
Physical Address0x4A00 2464InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_iva [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_3R0x0
Table 18-136 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4
Address Offset0x0000 0468
Physical Address0x4A00 2468InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_iva [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_4R0x0
Table 18-137 CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL
Address Offset0x0000 046C
Physical Address0x4A00 246CInstanceCTRL_MODULE_CORE
DescriptionDSPEVE Voltage Body Bias LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOVBBDSPEVE_FBB_MUX_CTRLLDOVBBDSPEVE_FBB_VSET_INLDOVBBDSPEVE_FBB_VSET_OUT
BitsField NameDescriptionTypeReset
31:11RESERVEDR0x0
10LDOVBBDSPEVE_FBB_MUX_CTRL

Override control of EFUSE Forward Body Bias voltage value

0x0 = efuse value is used

0x1 = override value is used

RW0x0
9:5LDOVBBDSPEVE_FBB_VSET_IN

EFUSE Forward Body Bias voltage value

R0x0
4:0LDOVBBDSPEVE_FBB_VSET_OUT

Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_x[24:20] VSETABB bit fields. This value applies if LDOVBBDSPEVE_FBB_MUX_CTRL is set to 0x1.

RW0x0
Table 18-138 CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL
Address Offset0x0000 0470
Physical Address0x4A00 2470InstanceCTRL_MODULE_CORE
DescriptionIVA Voltage Body Bias LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOVBBIVA_FBB_MUX_CTRLLDOVBBIVA_FBB_VSET_INLDOVBBIVA_FBB_VSET_OUT
BitsField NameDescriptionTypeReset
31:11RESERVEDR0x0
10LDOVBBIVA_FBB_MUX_CTRL

Override control of EFUSE Forward Body Bias voltage value

0x0 = efuse value is used

0x1 = override value is used

RW0x0
9:5LDOVBBIVA_FBB_VSET_IN

EFUSE Forward Body Bias voltage value

R0x0
4:0LDOVBBIVA_FBB_VSET_OUT

Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_x[24:20] VSETABB bit fields. This value applies if LDOVBBIVA_FBB_MUX_CTRL is set to 0x1.

RW0x0
Table 18-139 CTRL_CORE_CUST_FUSE_UID_0
Address Offset0x0000 04E8
Physical Address0x4A00 24E8InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. UID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_UID_0
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_UID_0R0x0
Table 18-140 CTRL_CORE_CUST_FUSE_UID_1
Address Offset0x0000 04EC
Physical Address0x4A00 24ECInstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. UID [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_UID_1
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_UID_1R0x0
Table 18-141 CTRL_CORE_CUST_FUSE_UID_2
Address Offset0x0000 04F0
Physical Address0x4A00 24F0InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. UID [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_UID_2
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_UID_2R0x0
Table 18-142 CTRL_CORE_CUST_FUSE_UID_3
Address Offset0x0000 04F4
Physical Address0x4A00 24F4InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. UID [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_UID_3
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_UID_3R0x0
Table 18-143 CTRL_CORE_CUST_FUSE_UID_4
Address Offset0x0000 04F8
Physical Address0x4A00 24F8InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. UID [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_UID_4
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_UID_4R0x0
Table 18-144 CTRL_CORE_CUST_FUSE_UID_5
Address Offset0x0000 04FC
Physical Address0x4A00 24FCInstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. UID [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_UID_5
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_UID_5R0x0
Table 18-145 CTRL_CORE_CUST_FUSE_UID_6
Address Offset0x0000 0500
Physical Address0x4A00 2500InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. UID [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_UID_6
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_UID_6R0x0
Table 18-146 CTRL_CORE_CUST_FUSE_PCIE_ID_0
Address Offset0x0000 0508
Physical Address0x4A00 2508InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. PCIe ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_PCIE_ID_0
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_PCIE_ID_0R0x0
Table 18-147 CTRL_CORE_CUST_FUSE_USB_ID_0
Address Offset0x0000 0510
Physical Address0x4A00 2510InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. USB ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_USB_ID_0
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_USB_ID_0R0x0
Table 18-148 CTRL_CORE_MAC_ID_SW_0
Address Offset0x0000 0514
Physical Address0x4A00 2514InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys, MAC ID_1 [63:32].
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDSTD_FUSE_MAC_ID_SW_0
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:0STD_FUSE_MAC_ID_SW_0This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 0.
Bits [23:16] contain the 4th octet of the MAC address.
Bits [15:8] contain the 5th octet of the MAC address.
Bits [7:0] contain the last (6th) octet of the MAC address.		R0x0
Table 18-149 CTRL_CORE_MAC_ID_SW_1
Address Offset0x0000 0518
Physical Address0x4A00 2518InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys, MAC ID_1 [31:0].
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDSTD_FUSE_MAC_ID_SW_1
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:0STD_FUSE_MAC_ID_SW_1This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 0.
Bits [23:16] contain the first octet of the MAC address.
Bits [15:8] contain the second octet of the MAC address.
Bits [7:0] contain the third octet of the MAC address.		R0x0
Table 18-150 CTRL_CORE_MAC_ID_SW_2
Address Offset0x0000 051C
Physical Address0x4A00 251CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys, MAC ID_2 [63:32].
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDSTD_FUSE_MAC_ID_SW_2
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:0STD_FUSE_MAC_ID_SW_2This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 1.
Bits [23:16] contain the 4th octet of the MAC address.
Bits [15:8] contain the 5th octet of the MAC address.
Bits [7:0] contain the last (6th) octet of the MAC address.		R0x0
Table 18-151 CTRL_CORE_MAC_ID_SW_3
Address Offset0x0000 0520
Physical Address0x4A00 2520InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse keys, MAC ID_2 [31:0].
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDSTD_FUSE_MAC_ID_SW_3
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:0STD_FUSE_MAC_ID_SW_3This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 1.
Bits [23:16] contain the first octet of the MAC address.
Bits [15:8] contain the second octet of the MAC address.
Bits [7:0] contain the third octet of the MAC address.		R0x0
Table 18-152 CTRL_CORE_SMA_SW_1
Address Offset0x0000 0534
Physical Address0x4A00 2534InstanceCTRL_MODULE_CORE
DescriptionOCP Spare Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII2_ID_MODE_NRGMII1_ID_MODE_NDSS_CH2_ON_OFFDSS_CH1_ON_OFFDSS_CH0_ON_OFFDSS_CH2_IPCDSS_CH1_IPCDSS_CH0_IPCDSS_CH2_RFDSS_CH1_RFDSS_CH0_RFRESERVEDVIP3_CLK_INV_PORT_1AVIP3_CLK_INV_PORT_2AVPE_CLK_DIV_BY_2_ENVIP2_CLK_INV_PORT_2BVIP2_CLK_INV_PORT_1BVIP2_CLK_INV_PORT_2AVIP2_CLK_INV_PORT_1AVIP1_CLK_INV_PORT_2BVIP1_CLK_INV_PORT_1BVIP1_CLK_INV_PORT_2AVIP1_CLK_INV_PORT_1A
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26RGMII2_ID_MODE_NEthernet RGMII port 2 internal delay on transmit (SR2.0)
0x0: Internal delay enabled
0x1: Internal delay disabled		RW0x0
25RGMII1_ID_MODE_NEthernet RGMII port 1 internal delay on transmit (SR2.0)
0x0: Internal delay enabled
0x1: Internal delay disabled		RW0x0
24DSS_CH2_ON_OFFDSS Channel 2 Pixel clock control On/Off
0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data
0x1: HSYNC and VSYNC are driven according to bit DSS_CH2_RF		RW0x0
23DSS_CH1_ON_OFFDSS Channel 1 Pixel clock control On/Off
0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data
0x1: HSYNC and VSYNC are driven according to bit DSS_CH1_RF		RW0x0
22DSS_CH0_ON_OFFDSS Channel 0 Pixel clock control On/Off
0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data
0x1: HSYNC and VSYNC are driven according to bit DSS_CH0_RF		RW0x0
21DSS_CH2_IPCDSS Channel 2 IPC control
0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock
0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock		RW0x0
20DSS_CH1_IPCDSS Channel 1 IPC control
0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock
0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock		RW0x0
19DSS_CH0_IPCDSS Channel 0 IPC control
0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock
0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock		RW0x0
18DSS_CH2_RFDSS Channel 2 Rise/Fall control
0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1)
0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1)		RW0x0
17DSS_CH1_RFDSS Channel 1 Rise/Fall control
0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1)
0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1)		RW0x0
16DSS_CH0_RFDSS Channel 0 Rise/Fall control
0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1)
0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1)		RW0x0
15:11RESERVEDR0x0
10VIP3_CLK_INV_PORT_1AVIP3 Slice 1 Clock inversion for Port A enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled 		RW0x0
9VIP3_CLK_INV_PORT_2AVIP3 Slice 0 Clock inversion for Port A enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled		RW0x0
8VPE_CLK_DIV_BY_2_EN

Selects alternative clock source for VPE.

0x0: Default clock source from DPLL_CORE is selected

0x1: Alternative clock source from DPLL_VIDEO1 is selected

RW0x0
7VIP2_CLK_INV_PORT_2BVIP2 Slice 1 Clock inversion for Port B enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled		RW0x0
6VIP2_CLK_INV_PORT_1BVIP2 Slice 0 Clock inversion for Port B enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled		RW0x0
5VIP2_CLK_INV_PORT_2AVIP2 Slice 1 Clock inversion for Port A enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled		RW0x0
4VIP2_CLK_INV_PORT_1AVIP2 Slice 0 Clock inversion for Port A enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled		RW0x0
3VIP1_CLK_INV_PORT_2BVIP1 Slice 1 Clock inversion for Port B enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled		RW0x0
2VIP1_CLK_INV_PORT_1BVIP1 Slice 0 Clock inversion for Port B enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled		RW0x0
1VIP1_CLK_INV_PORT_2AVIP1 Slice 1 Clock inversion for Port A enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled		RW0x0
0VIP1_CLK_INV_PORT_1AVIP1 Slice 0 Clock inversion for Port A enable
0x0: clock inversion is disabled
0x1: clock inversion is enabled		RW0x0
Table 18-153 CTRL_CORE_DSS_PLL_CONTROL
Address Offset0x0000 0538
Physical Address0x4A00 2538InstanceCTRL_MODULE_CORE
DescriptionDSS PLLs Mux control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSDVENC_CLK_SELECTIONDSI1_C_CLK1_SELECTIONDSI1_B_CLK1_SELECTIONDSI1_A_CLK1_SELECTIONPLL_HDMI_DSS_CONTROL_DISABLEPLL_VIDEO2_DSS_CONTROL_DISABLEPLL_VIDEO1_DSS_CONTROL_DISABLE
BitsField NameDescriptionTypeReset
31:11RESERVED

Reserved

RW0x0
10:9SDVENC_CLK_SELECTION

SDVENC_CLK mux configuration

0x0: HDMI_CLK

0x1: DPLL_VIDEO1_HSDIVIDER_clkout3

RW0x1
8:7DSI1_C_CLK1_SELECTION

DSI1_C_CLK1 mux configuration

0x0: DPLL_VIDEO2

0x1: DPLL_VIDEO1

0x2: DPLL_HDMI

RW0x1
6:5DSI1_B_CLK1_SELECTION

DSI1_B_CLK1 mux configuration

0x0: DPLL_VIDEO1

0x1: DPLL_VIDEO2

0x2: DPLL_HDMI

0x3: DPLL_ABE

RW0x1
4:3DSI1_A_CLK1_SELECTION

DSI1_A_CLK1 mux configuration

0x0: DPLL_VIDEO1

0x1: DPLL_HDMI

RW0x1
2PLL_HDMI_DSS_CONTROL_DISABLE

HDMI PLL disable

0x0: PLL enabled

0x1: PLL disabled

RW0x1
1PLL_VIDEO2_DSS_CONTROL_DISABLE

VIDEO2 PLL disable

0x0: PLL enabled

0x1: PLL disabled

RW0x1
0PLL_VIDEO1_DSS_CONTROL_DISABLE

VIDEO1 PLL disable

0x0: PLL enabled

0x1: PLL disabled

RW0x1
Table 18-154 CTRL_CORE_MMR_LOCK_1
Address Offset0x0000 0540
Physical Address0x4A00 2540InstanceCTRL_MODULE_CORE
DescriptionRegister to lock memory region starting at address offset 0x0000 0100 and ending at address offset 0x0000 079F
TypeRW
313029282726252423222120191817161514131211109876543210
MMR_LOCK_1
BitsField NameDescriptionTypeReset
31:0MMR_LOCK_1

Lock value for region 0x0000 0100 to 0x0000 079F

0x1A1C8144 = lock value

0x2FF1AC2B = unlock value

RW0x1A1C8144
Table 18-155 CTRL_CORE_MMR_LOCK_2
Address Offset0x0000 0544
Physical Address0x4A00 2544InstanceCTRL_MODULE_CORE
DescriptionRegister to lock memory region starting at address offset 0x0000 07A0 and ending at address offset 0x0000 0D9F
TypeRW
313029282726252423222120191817161514131211109876543210
MMR_LOCK_2
BitsField NameDescriptionTypeReset
31:0MMR_LOCK_2

Lock value for region 0x0000 07A0 to 0x0000 0D9F

0xFDF45530 = lock value

0xF757FDC0 = unlock value

RW0xFDF45530
Table 18-156 CTRL_CORE_MMR_LOCK_3
Address Offset0x0000 0548
Physical Address0x4A00 2548InstanceCTRL_MODULE_CORE
DescriptionRegister to lock memory region starting at address offset 0x0000 0DA0 and ending at address offset 0x0000 0FFF
TypeRW
313029282726252423222120191817161514131211109876543210
MMR_LOCK_3
BitsField NameDescriptionTypeReset
31:0MMR_LOCK_3

Lock value for region 0x0000 0DA0 to 0x0000 0FFF

0x1AE6E320 = lock value

0xE2BC3A6D = unlock value

RW0x1AE6E320
Table 18-157 CTRL_CORE_MMR_LOCK_4
Address Offset0x0000 054C
Physical Address0x4A00 254CInstanceCTRL_MODULE_CORE
DescriptionRegister to lock memory region starting at address offset 0x0000 1000 and ending at address offset 0x0000 13FF
TypeRW
313029282726252423222120191817161514131211109876543210
MMR_LOCK_4
BitsField NameDescriptionTypeReset
31:0MMR_LOCK_4

Lock value for region 0x0000 1000 to 0x0000 13FF

0x2FFA927C = lock value

0x1EBF131D = unlock value

RW0x2FFA927C
Table 18-158 CTRL_CORE_MMR_LOCK_5
Address Offset0x0000 0550
Physical Address0x4A00 2550InstanceCTRL_MODULE_CORE
DescriptionRegister to lock memory region starting at address offset 0x0000 1400 and ending at address offset 0x0000 1FFF
TypeRW
313029282726252423222120191817161514131211109876543210
MMR_LOCK_5
BitsField NameDescriptionTypeReset
31:0MMR_LOCK_5

Lock value for region 0x0000 1400 to 0x0000 1FFF

0x143F832C = lock value

0x6F361E05 = unlock value

RW0x143F832C
Table 18-159 CTRL_CORE_CONTROL_IO_1
Address Offset0x0000 0554
Physical Address0x4A00 2554InstanceCTRL_MODULE_CORE
DescriptionRegister to configure some IP level signals
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMU2_DISABLERESERVEDMMU1_DISABLERESERVEDTC1_DEFAULT_BURST_SIZERESERVEDTC0_DEFAULT_BURST_SIZERESERVEDGMII2_SELRESERVEDGMII1_SEL
BitsField NameDescriptionTypeReset
31:21RESERVEDR0x0
20MMU2_DISABLE

MMU2 DISABLE setting

RW0x0
19:17RESERVEDR0x0
16MMU1_DISABLE

MMU1 DISABLE setting

RW0x0
15:14RESERVEDR0x0
13:12TC1_DEFAULT_BURST_SIZE

EDMA TC1 Default Burst Size (DBS) setting

0x0: 16 byte burst

0x1: 32 byte burst

0x2: 64 byte burst

0x3: 128 byte burst

RW0x3
11:10RESERVEDR0x0
9:8TC0_DEFAULT_BURST_SIZE

EDMA TC0 Default Burst Size (DBS) setting

0x0: 16 byte burst

0x1: 32 byte burst

0x2: 64 byte burst

0x3: 128 byte burst

RW0x3
7:6RESERVEDR0x0
5:4GMII2_SEL

GMII2 selection setting

0x0: GMII/MII

0x1: RMII

0x2: RGMII

0x3: Reserved

RW0x0
3:2RESERVEDR0x0
1:0GMII1_SEL

GMII1 selection setting

0x0: GMII/MII

0x1: RMII

0x2: RGMII

0x3: Reserved

RW0x0
Table 18-160 CTRL_CORE_CONTROL_IO_2
Address Offset0x0000 0558
Physical Address0x4A00 2558InstanceCTRL_MODULE_CORE
DescriptionRegister to configure some IP level signals
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGMAC_RESET_ISOLATION_ENABLEPWMSS3_TBCLKENPWMSS2_TBCLKENPWMSS1_TBCLKENRESERVEDPCIE_1LANE_2LANE_SELECTIONRESERVEDQSPI_MEMMAPPED_CSRESERVEDDCAN2_RAMINIT_STARTDSS_DESHDCP_DISABLEDCAN1_RAMINIT_STARTDCAN2_RAMINIT_DONEDCAN1_RAMINIT_DONEDSS_DESHDCP_CLKEN
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23GMAC_RESET_ISOLATION_ENABLE

Reset isolation enable setting

0x0 = Reset is not isolated

0x1 = Reset is isolated

RW0x0
22PWMSS3_TBCLKEN

PWMSS3 CLOCK ENABLE setting

RW0x0
21PWMSS2_TBCLKEN

PWMSS2 CLOCK ENABLE setting

RW0x0
20PWMSS1_TBCLKEN

PWMSS1 CLOCK ENABLE setting

RW0x0
19:14RESERVEDR0x0
13PCIE_1LANE_2LANE_SELECTIONReserved RW0x0
12:11RESERVEDR0x0
10:8QSPI_MEMMAPPED_CS

QSPI CS MAPPING setting.

0x0: The QSPI configuration registers are accessed

0x1: An external device connected to CS0 is accessed

0x2: An external device connected to CS1 is accessed

0x3: An external device connected to CS2 is accessed

0x4-0x7: An external device connected to CS3 is accessed

RW0x0
7:6RESERVEDR0x0
5DCAN2_RAMINIT_START

DCAN2 RAM INIT START setting

To initialize DCAN2 RAM, the bit should be set to 0x1. It is not auto cleared by hardware.
Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again.		RW0x0
4DSS_DESHDCP_DISABLE

DSS DESHDCP DISABLE setting

RW0x0
3DCAN1_RAMINIT_START

DCAN1 RAM INIT START setting

To initialize DCAN1 RAM, the bit should be set to 0x1. It is not auto cleared by hardware.
Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again.		RW0x0
2DCAN2_RAMINIT_DONE

DCAN2 RAM INIT DONE status

RW0x0
1DCAN1_RAMINIT_DONE

DCAN1 RAM INIT DONE status

RW0x0
0DSS_DESHDCP_CLKEN

DSS DESHDCP CLOCK ENABLE setting

RW0x0
Table 18-161 CTRL_CORE_CONTROL_DSP1_RST_VECT
Address Offset0x0000 055C
Physical Address0x4A00 255CInstanceCTRL_MODULE_CORE
DescriptionRegister for storing DSP1 reset vector
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_NUM_MMRESERVEDDSP1_RST_VECT
BitsField NameDescriptionTypeReset
31:27RESERVED

Reserved

RW0x0
26:24DSP1_NUM_MM

Number of DSP instances in the SoC

0x1 = 1

0x2 = 2

RW0x0
23:22RESERVEDR0x0
21:0DSP1_RST_VECT

DSP1 reset vector address

RW0x0
Table 18-162 CTRL_CORE_CONTROL_DSP2_RST_VECT
Address Offset0x0000 0560
Physical Address0x4A00 2560InstanceCTRL_MODULE_CORE
DescriptionRegister for storing DSP2 reset vector
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_NUM_MMRESERVEDDSP2_RST_VECT
BitsField NameDescriptionTypeReset
31:27RESERVED

Reserved

RW0x0
26:24DSP2_NUM_MM

Number of DSP instances in the SoC

0x1 = 1

0x2 = 2

RW0x0
23:22RESERVEDR0x0
21:0DSP2_RST_VECT

DSP2 reset vector address

RW0x0
Table 18-163 CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE
Address Offset0x0000 0564
Physical Address0x4A00 2564InstanceCTRL_MODULE_CORE
DescriptionTrim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDSTD_FUSE_OPP_BGAP_DSPEVE_0STD_FUSE_OPP_BGAP_DSPEVE_1
BitsField NameDescriptionTypeReset
31:16RESERVEDR0x-
15:8STD_FUSE_OPP_BGAP_DSPEVE_0Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use.R0x-
7:0STD_FUSE_OPP_BGAP_DSPEVE_1Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use.R0x-
Table 18-164 CTRL_CORE_STD_FUSE_OPP_BGAP_IVA
Address Offset0x0000 0568
Physical Address0x4A00 2568InstanceCTRL_MODULE_CORE
DescriptionTrim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_BGAP_IVA_0STD_FUSE_OPP_BGAP_IVA_1STD_FUSE_OPP_BGAP_IVA_2STD_FUSE_OPP_BGAP_IVA_3
BitsField NameDescriptionTypeReset
31:24STD_FUSE_OPP_BGAP_IVA_0Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
23:16STD_FUSE_OPP_BGAP_IVA_1Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
15:8STD_FUSE_OPP_BGAP_IVA_2Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
7:0STD_FUSE_OPP_BGAP_IVA_3Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.R0x-
Table 18-165 CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL
Address Offset0x0000 056C
Physical Address0x4A00 256CInstanceCTRL_MODULE_CORE
DescriptionDSPEVE SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMDSPEVE_RETMODE_MUX_CTRLLDOSRAMDSPEVE_RETMODE_VSET_INLDOSRAMDSPEVE_RETMODE_VSET_OUTRESERVEDLDOSRAMDSPEVE_ACTMODE_MUX_CTRLLDOSRAMDSPEVE_ACTMODE_VSET_INLDOSRAMDSPEVE_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMDSPEVE_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMDSPEVE_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMDSPEVE_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMDSPEVE_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMDSPEVE_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMDSPEVE_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-166 CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL
Address Offset0x0000 0570
Physical Address0x4A00 2570InstanceCTRL_MODULE_CORE
DescriptionIVA SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMIVA_RETMODE_MUX_CTRLLDOSRAMIVA_RETMODE_VSET_INLDOSRAMIVA_RETMODE_VSET_OUTRESERVEDLDOSRAMIVA_ACTMODE_MUX_CTRLLDOSRAMIVA_ACTMODE_VSET_INLDOSRAMIVA_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMIVA_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMIVA_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMIVA_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMIVA_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMIVA_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMIVA_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-167 CTRL_CORE_TEMP_SENSOR_DSPEVE
Address Offset0x0000 0574
Physical Address0x4A00 2574InstanceCTRL_MODULE_CORE
DescriptionControl VBGAPTS temperature sensor and thermal comparator shutdown register
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBGAP_TMPSOFF_DSPEVEBGAP_EOCZ_DSPEVEBGAP_DTEMP_DSPEVE
BitsField NameDescriptionTypeReset
31:12RESERVEDR0x0
11BGAP_TMPSOFF_DSPEVE

This bit indicates the temperature sensor state.
0x0: temperature sensor is ON
0x1: temperature sensor is OFF
NOTE: Software doesn't take care of this bit to get the temperature data. Only the BGAP_EOCZ_DSPEVE bit is needed.

R0x1
10BGAP_EOCZ_DSPEVE

ADC End of Conversion. Active low, when BGAP_DTEMP_DSPEVE is valid.

R0x0
9:0BGAP_DTEMP_DSPEVE

Temperature data from the ADC. Valid if EOCZ is low.

R0x0
Table 18-168 CTRL_CORE_TEMP_SENSOR_IVA
Address Offset0x0000 0578
Physical Address0x4A00 2578InstanceCTRL_MODULE_CORE
DescriptionControl VBGAPTS temperature sensor and thermal comparator shutdown register
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDBGAP_TMPSOFF_IVABGAP_EOCZ_IVABGAP_DTEMP_IVA
BitsField NameDescriptionTypeReset
31:12RESERVEDR0x0
11BGAP_TMPSOFF_IVA

This bit indicates the temperature sensor state.
0x0: temperature sensor is ON
0x1: temperature sensor is OFF
NOTE: Software doesn't take care of this bit to get the temperature data. Only the BGAP_EOCZ_IVA bit is needed.

R0x1
10BGAP_EOCZ_IVA

ADC End of Conversion. Active low, when BGAP_DTEMP_IVA is valid.

R0x0
9:0BGAP_DTEMP_IVA

Temperature data from the ADC. Valid if EOCZ is low.

R0x0
Table 18-169 CTRL_CORE_BANDGAP_MASK_2
Address Offset0x0000 057C
Physical Address0x4A00 257CInstanceCTRL_MODULE_CORE
Descriptionbgap_mask
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDFREEZE_IVAFREEZE_DSPEVERESERVEDCLEAR_IVACLEAR_DSPEVERESERVEDMASK_HOT_IVAMASK_COLD_IVAMASK_HOT_DSPEVEMASK_COLD_DSPEVE
BitsField NameDescriptionTypeReset
31:23RESERVEDR0x0
22FREEZE_IVA

Freeze the FIFO IVA

0x0 = No operation

0x1 = Freeze the FIFO

RW0x0
21FREEZE_DSPEVE

Freeze the FIFO DSPEVE

0x0 = No operation

0x1 = Freeze the FIFO

RW0x0
20RESERVEDR0x0
19CLEAR_IVA

Reset the FIFO IVA

0x0 = No operation

0x1 = Reset the FIFO

RW0x0
18CLEAR_DSPEVE

Reset the FIFO DSPEVE

0x0 = No operation

0x1 = Reset the FIFO

RW0x0
17:4RESERVEDR0x0
3MASK_HOT_IVA

Mask for hot event IVA

0x0 = hot event is masked

0x1 = hot event is not masked

RW0x0
2MASK_COLD_IVA

Mask for cold event IVA

0x0 = cold event is masked

0x1 = cold event is not masked

RW0x0
1MASK_HOT_DSPEVE

Mask for hot event DSPEVE

0x0 = hot event is masked

0x1 = hot event is not masked

RW0x0
0MASK_COLD_DSPEVE

Mask for cold event DSPEVE

0x0 = cold event is masked

0x1 = cold event is not masked

RW0x0
Table 18-170 CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE
Address Offset0x0000 0580
Physical Address0x4A00 2580InstanceCTRL_MODULE_CORE
DescriptionBGAP THRESHOLD DSPEVE
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTHOLD_HOT_DSPEVERESERVEDTHOLD_COLD_DSPEVE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16THOLD_HOT_DSPEVE

Value for the high temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
15:10RESERVEDR0x0
9:0THOLD_COLD_DSPEVE

Value for the low temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
Table 18-171 CTRL_CORE_BANDGAP_THRESHOLD_IVA
Address Offset0x0000 0584
Physical Address0x4A00 2584InstanceCTRL_MODULE_CORE
DescriptionBGAP THRESHOLD IVA
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTHOLD_HOT_IVARESERVEDTHOLD_COLD_IVA
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16THOLD_HOT_IVA

Value for the high temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
15:10RESERVEDR0x0
9:0THOLD_COLD_IVA

Value for the low temperature threshold. The values for loading this bit field are listed in Table 18-10.

RW0x0
Table 18-172 CTRL_CORE_BANDGAP_TSHUT_DSPEVE
Address Offset0x0000 0588
Physical Address0x4A00 2588InstanceCTRL_MODULE_CORE
DescriptionBGAP TSHUT THRESHOLD IVA
TypeR
313029282726252423222120191817161514131211109876543210
TSHUT_MUXCTRL_DSPEVERESERVEDTSHUT_HOT_DSPEVERESERVEDTSHUT_COLD_DSPEVE
BitsField NameDescriptionTypeReset
31TSHUT_MUXCTRL_DSPEVEWriting a ‘1’ to this field allows SW to override the TSHUT_HOT and TSHUT_COLD values that are set by default in efuse.RW0x0
30:26RESERVEDR0x0
25:16TSHUT_HOT_DSPEVE

Controls the TSHUT_HOT reset threshold, which protects the device from thermal runaway and potential device damage. The register defaults to 123°C. Software override of this register value is not recommended, and should only be done with extreme caution as damage to the device can occur above the default setting.

RW0x0
15:10RESERVEDR0x0
9:0TSHUT_COLD_DSPEVE

Controls the TSHUT_COLD reset threshold, which is the limit where the TSHUT comparator releases the device from reset after cooling from a TSHUT condition. The register defaults to 105°C. Software override of this register value is not recommended, and should only be done with extreme caution.

RW0x0
Table 18-173 CTRL_CORE_BANDGAP_TSHUT_IVA
Address Offset0x0000 058C
Physical Address0x4A00 258CInstanceCTRL_MODULE_CORE
DescriptionBGAP TSHUT THRESHOLD IVA
TypeR
313029282726252423222120191817161514131211109876543210
TSHUT_MUXCTRL_IVARESERVEDTSHUT_HOT_IVARESERVEDTSHUT_COLD_IVA
BitsField NameDescriptionTypeReset
31TSHUT_MUXCTRL_IVA

Writing a ‘1’ to this field allows SW to override the TSHUT_HOT and TSHUT_COLD values that are set by default in efuse.

RW0x0
30:26RESERVEDR0x0
25:16TSHUT_HOT_IVA

Controls the TSHUT_HOT reset threshold, which protects the device from thermal runaway and potential device damage. The register defaults to 123°C. Software override of this register value is not recommended, and should only be done with extreme caution as damage to the device can occur above the default setting.

RW0x0
15:10RESERVEDR0x0
9:0TSHUT_COLD_IVA

Controls the TSHUT_COLD reset threshold, which is the limit where the TSHUT comparator releases the device from reset after cooling from a TSHUT condition. The register defaults to 105°C. Software override of this register value is not recommended, and should only be done with extreme caution.

RW0x0
Table 18-174 CTRL_CORE_BANDGAP_STATUS_2
Address Offset0x0000 0598
Physical Address0x4A00 2598InstanceCTRL_MODULE_CORE
DescriptionBGAP STATUS
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDHOT_IVACOLD_IVAHOT_DSPEVECOLD_DSPEVE
BitsField NameDescriptionTypeReset
31:4RESERVEDR0x0
3HOT_IVA

Event for hot temperature iva bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
2COLD_IVA

Event for cold temperature iva bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
1HOT_DSPEVE

Event for hot temperature dspeve bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
0COLD_DSPEVE

Event for cold temperature dspeve bandgap when '1'

0x0 = event not detected

0x1 = event detected

R0x0
Table 18-175 CTRL_CORE_DTEMP_DSPEVE_0
Address Offset0x0000 059C
Physical Address0x4A00 259CInstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE DSPEVE DOMAIN. Most recent sample
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_DSPEVE_0DTEMP_TEMPERATURE_DSPEVE_0
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_DSPEVE_0

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_DSPEVE_0

temperature

R0x0
Table 18-176 CTRL_CORE_DTEMP_DSPEVE_1
Address Offset0x0000 05A0
Physical Address0x4A00 25A0InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE DSPEVE DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_DSPEVE_1DTEMP_TEMPERATURE_DSPEVE_1
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_DSPEVE_1

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_DSPEVE_1

temperature

R0x0
Table 18-177 CTRL_CORE_DTEMP_DSPEVE_2
Address Offset0x0000 05A4
Physical Address0x4A00 25A4InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE DSPEVE DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_DSPEVE_2DTEMP_TEMPERATURE_DSPEVE_2
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_DSPEVE_2

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_DSPEVE_2

temperature

R0x0
Table 18-178 CTRL_CORE_DTEMP_DSPEVE_3
Address Offset0x0000 05A8
Physical Address0x4A00 25A8InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE DSPEVE DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_DSPEVE_3DTEMP_TEMPERATURE_DSPEVE_3
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_DSPEVE_3

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_DSPEVE_3

temperature

R0x0
Table 18-179 CTRL_CORE_DTEMP_DSPEVE_4
Address Offset0x0000 05AC
Physical Address0x4A00 25ACInstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE DSPEVE DOMAIN. Oldest sample
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_DSPEVE_4DTEMP_TEMPERATURE_DSPEVE_4
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_DSPEVE_4

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_DSPEVE_4

temperature

R0x0
Table 18-180 CTRL_CORE_DTEMP_IVA_0
Address Offset0x0000 05B0
Physical Address0x4A00 25B0InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE IVA DOMAIN. Most recent sample
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_IVA_0DTEMP_TEMPERATURE_IVA_0
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_IVA_0

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_IVA_0

temperature

R0x0
Table 18-181 CTRL_CORE_DTEMP_IVA_1
Address Offset0x0000 05B4
Physical Address0x4A00 25B4InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE IVA DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_IVA_1DTEMP_TEMPERATURE_IVA_1
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_IVA_1

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_IVA_1

temperature

R0x0
Table 18-182 CTRL_CORE_DTEMP_IVA_2
Address Offset0x0000 05B8
Physical Address0x4A00 25B8InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE IVA DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_IVA_2DTEMP_TEMPERATURE_IVA_2
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_IVA_2

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_IVA_2

temperature

R0x0
Table 18-183 CTRL_CORE_DTEMP_IVA_3
Address Offset0x0000 05BC
Physical Address0x4A00 25BCInstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE IVA DOMAIN
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_IVA_3DTEMP_TEMPERATURE_IVA_3
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_IVA_3

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_IVA_3

temperature

R0x0
Table 18-184 CTRL_CORE_DTEMP_IVA_4
Address Offset0x0000 05C0
Physical Address0x4A00 25C0InstanceCTRL_MODULE_CORE
DescriptionTAGGED TEMPERATURE IVA DOMAIN. Oldest sample
TypeR
313029282726252423222120191817161514131211109876543210
DTEMP_TAG_IVA_4DTEMP_TEMPERATURE_IVA_4
BitsField NameDescriptionTypeReset
31:10DTEMP_TAG_IVA_4

tag. Indicate number of times in the bgap state machine.

R0x0
9:0DTEMP_TEMPERATURE_IVA_4

temperature

R0x0
Table 18-185 CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_5
Address offset0x0000 05C4
Physical Address0x0000 05C4InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_PLUS.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_IVA_5
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_PLUS which has to be written to the CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_IVA_5AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_PLUS. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-186 CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2
Address offset0x0000 05CC
Physical Address0x4A00 25CCInstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_IVA_2
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_NOM which has to be written to the CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_IVA_2AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-187 CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3
Address offset0x0000 05D0
Physical Address0x4A00 25D0InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_IVA_3
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_OD which has to be written to the CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_IVA_3AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-188 CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4
Address offset0x0000 05D4
Physical Address0x4A00 25D4InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_IVA_4
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_HIGH which has to be written to the CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_IVA_4AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-189 CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_5
Address offset0x0000 05D8
Physical Address0x0000 05D8InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_PLUS.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_DSPEVE_5
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_PLUS which has to be written to the CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_DSPEVE_5AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_PLUS. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-190 CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2
Address offset0x0000 05E0
Physical Address0x4A00 25E0InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_DSPEVE_2
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_NOM which has to be written to the CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_DSPEVE_2AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-191 CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3
Address offset0x0000 05E4
Physical Address0x4A00 25E4InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_DSPEVE_3
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_OD which has to be written to the CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_DSPEVE_3AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-192 CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4
Address offset0x0000 05E8
Physical Address0x4A00 25E8InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_DSPEVE_4
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_HIGH which has to be written to the CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_DSPEVE_4AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-193 CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2
Address Offset0x0000 05F4
Physical Address0x4A00 25F4InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDSTD_FUSE_OPP_VMIN_CORE_2
BitsField NameDescriptionTypeReset
31:12RESERVEDReservedR0x-
11:0STD_FUSE_OPP_VMIN_CORE_2

AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value.

R0x-
Table 18-194 CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL
Address Offset0x0000 0680
Physical Address0x4A00 2680InstanceCTRL_MODULE_CORE
DescriptionCORE 2nd SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMCORE_2_RETMODE_MUX_CTRLLDOSRAMCORE_2_RETMODE_VSET_INLDOSRAMCORE_2_RETMODE_VSET_OUTRESERVEDLDOSRAMCORE_2_ACTMODE_MUX_CTRLLDOSRAMCORE_2_ACTMODE_VSET_INLDOSRAMCORE_2_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMCORE_2_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMCORE_2_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMCORE_2_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMCORE_2_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMCORE_2_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMCORE_2_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-195 CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL
Address Offset0x0000 0684
Physical Address0x4A00 2684InstanceCTRL_MODULE_CORE
DescriptionCORE 3rd SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMCORE_3_RETMODE_MUX_CTRLLDOSRAMCORE_3_RETMODE_VSET_INLDOSRAMCORE_3_RETMODE_VSET_OUTRESERVEDLDOSRAMCORE_3_ACTMODE_MUX_CTRLLDOSRAMCORE_3_ACTMODE_VSET_INLDOSRAMCORE_3_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMCORE_3_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMCORE_3_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMCORE_3_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMCORE_3_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMCORE_3_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMCORE_3_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-196 CTRL_CORE_NMI_DESTINATION_1
Address Offset0x0000 068C
Physical Address0x4A00 268CInstanceCTRL_MODULE_CORE
DescriptionRegister for routing NMI interrupt to respective cores
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_C1IPU2_C0IPU1_C1
BitsField NameDescriptionTypeReset
31:24RESERVED

Reserved

RW0x0
23:16IPU2_C1

Enable IPU2 CORE1 to receive the NMI interrupt

0x0 = NMI disabled

0x1 = NMI enabled

RW0x0
15:8IPU2_C0

Enable IPU2 CORE0 to receive the NMI interrupt

0x0 = NMI disabled

0x1 = NMI enabled

RW0x0
7:0IPU1_C1

Enable IPU1 CORE1 to receive the NMI interrupt

0x0 = NMI disabled

0x1 = NMI enabled

RW0x0
Table 18-197 CTRL_CORE_NMI_DESTINATION_2
Address Offset0x0000 0690
Physical Address0x4A00 2690InstanceCTRL_MODULE_CORE
DescriptionRegister for routing NMI interrupt to respective cores
TypeRW
313029282726252423222120191817161514131211109876543210
IPU1_C0DSP2DSP1MPU
BitsField NameDescriptionTypeReset
31:24IPU1_C0

Enable IPU1 CORE0 to receive the NMI interrupt

0x0 = NMI disabled

0x1 = NMI enabled

RW0x0
23:16DSP2

Enable DSP2 to receive the NMI interrupt

0x0 = NMI disabled

0x1 = NMI enabled

RW0x0
15:8DSP1

Enable DSP1 to receive the NMI interrupt

0x0 = NMI disabled

0x1 = NMI enabled

RW0x0
7:0MPU

Comes from Efuse (MPU_EN)

0x0 = NMI disabled

0x1 = NMI enabled

RW0x0
Table 18-198 CTRL_CORE_IP_PRESSURE
Address Offset0x0000 0698
Physical Address0x4A00 2698InstanceCTRL_MODULE_CORE
DescriptionRegister to override the L3 pressure setting for the MLB module
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMLB_L3_PRESSURE_ENABLEMLB_L3_PRESSURE
BitsField NameDescriptionTypeReset
31:3RESERVEDR0x0
2MLB_L3_PRESSURE_ENABLE

Override enable for the MLB L3 pressure setting

0x0 = Overriding of the L3 pressure setting for the MLB module is disabled

0x1 = Overriding of the L3 pressure setting for the MLB module is enabled

RW0x0
1:0MLB_L3_PRESSURE

MLB L3 pressure setting

0x0 = Lowest

0x3 = Highest

RW0x0
Table 18-199 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0
Address Offset0x0000 06A0
Physical Address0x4A00 26A0InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_DSPEVE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_0R0x0
Table 18-200 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1
Address Offset0x0000 06A4
Physical Address0x4A00 26A4InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_DSPEVE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_1R0x0
Table 18-201 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2
Address Offset0x0000 06A8
Physical Address0x4A00 26A8InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_DSPEVE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_2R0x0
Table 18-202 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3
Address Offset0x0000 06AC
Physical Address0x4A00 26ACInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_DSPEVE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_3R0x0
Table 18-203 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4
Address Offset0x0000 06B0
Physical Address0x4A00 26B0InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_DSPEVE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_4R0x0
Table 18-204 CTRL_CORE_CUST_FUSE_SWRV_7
Address Offset0x0000 06B4
Physical Address0x4A00 26B4InstanceCTRL_MODULE_CORE
DescriptionCustomer Fuse keys. SWRV [31:0] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
CUST_FUSE_SWRV_7
BitsField NameDescriptionTypeReset
31:0CUST_FUSE_SWRV_7R0x0
Table 18-205 CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0
Address Offset0x0000 06B8
Physical Address0x4A00 26B8InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse Calibration override value [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0R0x0
Table 18-206 CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1
Address Offset0x0000 06BC
Physical Address0x4A00 26BCInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse Calibration override value [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1R0x0
Table 18-207 CTRL_CORE_PCIE_POWER_STATE
Address Offset0x0000 06C0
Physical Address0x4A00 26C0InstanceCTRL_MODULE_CORE
DescriptionRegister to PCIe related controls
TypeRW
313029282726252423222120191817161514131211109876543210
BYPASS_EN_APLL_PCIECLKOOUTEN_APLL_PCIERESERVEDEFUSE_TRIM_ACS_PCIEEFUSE_TRIM_PCIE_PLL
BitsField NameDescriptionTypeReset
31BYPASS_EN_APLL_PCIE

Bypass enable bit setting for APLL_PCIe

RW0x0
30CLKOOUTEN_APLL_PCIE

Clock output enable bit setting for APLL_PCIe

RW0x0
29:26RESERVEDR0x0
25:16EFUSE_TRIM_ACS_PCIE

MMR override capability for ACS_PCIe efuse trim bits

RW0x0
15:0EFUSE_TRIM_PCIE_PLL

MMR override capability for PCIe PLL efuse trim bits

RW0x0
Table 18-208 CTRL_CORE_BOOTSTRAP
Address Offset0x0000 06C4
Physical Address0x4A00 26C4InstanceCTRL_MODULE_CORE
DescriptionRegister to view all the sysboot settings
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDDSP_CLOCK_DIVIDERRESERVEDBOOTDEVICESIZEMUXCS0DEVICEBOOTWAITENSPEEDSELECTSYSBOOT_76BOOTMODE
BitsField NameDescriptionTypeReset
31:16RESERVEDR0x0
15DSP_CLOCK_DIVIDER

SR1.1 Only:

Divide factor for DSP clock
0x0: DSP_CLK2 is selected. Not supported on this SoC.
0x1: DSP_CLK3 is selected

SR2.0 Only:

Permanently disables the internal PU/PD resistors on pads gpmc_a[27:24, 22:19].

0x0: Internal pull-down resistors are enabled

0x1: Internal pull-down resistors are permanently disabled

R0x0
14RESERVED

For proper device operation, a value of 0 is required on the sysboot14 pad.

R0x0
13BOOTDEVICESIZE

Select the size of the flash device on CS0.

0x0: 8-bit

0x1: 16-bit

R0x0
12:11MUXCS0DEVICE

Select IC boot sequence to be executed from a multiplexed address and data device attached to CS0.

0x0: Non-muxed device attached

0x1: Addr-Data Mux device attached

0x2: Reserved

0x3: Reserved

R0x0
10BOOTWAITEN

Enable the monitoring on CS0 of the wait pin at IC reset release time for read accesses.

0x0: Wait pin is not monitored for read accesses

0x1: Wait pin is monitored for read accesses

R0x0
9:8SPEEDSELECT

Indicates the SYS_CLK1 frequency (from osc0). Note that the internal FUNC_32K_CLK is equal to SYS_CLK1/610, which is nominally 32.7869 kHz with 20 MHz clock.

0x0: Reserved

0x1: 20 MHz

0x2: 27 MHz

0x3: 19.2 MHz

R0x0
7:6SYSBOOT_76

Sector offset for the location of the redundant SBL images in QSPI.

0x0: 64 KB offset

0x1: 128 KB offset

0x2: 256 KB offset

0x3: 512 KB offset

R0x0
5:0BOOTMODE

SYSBOOT mode

R0x0
Table 18-209 CTRL_CORE_MLB_SIG_IO_CTRL
Address Offset0x0000 06C8
Physical Address0x4A00 26C8InstanceCTRL_MODULE_CORE
DescriptionRegister to set the MLB's SIG IO characteristics
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSIG_NC_INRESERVEDSIG_PC_INRESERVEDSIG_REMOVE_SKEWSIG_PWRDNRXSIG_PWRDNTXSIG_EN_EXT_RESRESERVED
BitsField NameDescriptionTypeReset
31:22RESERVEDR0x0
21:16SIG_NC_IN

efuse trim for Nmos impedance

RW0x0
15:14RESERVEDR0x0
13:8SIG_PC_IN

efuse trim for Pmos impedance

RW0x0
7RESERVEDR0x0
6SIG_REMOVE_SKEW

Adjust for skew generated by the receiver due to asymmetric inputs.

0x0: skew compensation is disabled

0x1: skew compensation is enabled

RW0x0
5SIG_PWRDNRX

powerdown receiver, active high

0x0 = Powered ON

0x1 = Powered OFF

RW0x1
4SIG_PWRDNTX

powerdown transmitter, active high

0x0 = Powered ON

0x1 = Powered OFF

RW0x1
3SIG_EN_EXT_RES

disables internal resistors

0x0 = Disabled

0x1 = Enabled

RW0x0
2:0RESERVEDR0x0
Table 18-210 CTRL_CORE_MLB_DAT_IO_CTRL
Address Offset0x0000 06CC
Physical Address0x4A00 26CCInstanceCTRL_MODULE_CORE
DescriptionRegister to set the MLB's DAT IO characteristics
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDAT_NC_INRESERVEDDAT_PC_INRESERVEDDAT_REMOVE_SKEWDAT_PWRDNRXDAT_PWRDNTXDAT_EN_EXT_RESRESERVED
BitsField NameDescriptionTypeReset
31:22RESERVEDR0x0
21:16DAT_NC_IN

efuse trim for Nmos impedance

RW0x0
15:14RESERVEDR0x0
13:8DAT_PC_IN

efuse trim for Pmos impedance

RW0x0
7RESERVEDR0x0
6DAT_REMOVE_SKEW

Adjust for skew generated by the receiver due to asymmetric inputs.

0x0: skew compensation is disabled

0x1: skew compensation is enabled

RW0x0
5DAT_PWRDNRX

powerdown receiver, active high

0x0 = Powered ON

0x1 = Powered OFF

RW0x1
4DAT_PWRDNTX

powerdown transmitter, active high

0x0 = Powered ON

0x1 = Powered OFF

RW0x1
3DAT_EN_EXT_RES

Enable/disable internal resistors

0x0 = Disabled

0x1 = Enabled

RW0x0
2:0RESERVEDR0x0
Table 18-211 CTRL_CORE_MLB_CLK_BG_CTRL
Address Offset0x0000 06D0
Physical Address0x4A00 26D0InstanceCTRL_MODULE_CORE
DescriptionRegister to set the MLB's clock receiver IO and bandgap characteristics
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDT_HYSTERISIS_ENRESERVEDBG_TRIMBG_PWRDNCLK_PWRDN
BitsField NameDescriptionTypeReset
31:17RESERVEDR0x0
16T_HYSTERISIS_EN

Hysterisis enable

0x0: Disabled

0x1: Enabled

RW0x0
15:8RESERVEDR0x0
7:2BG_TRIM

Trim values for MLB bandgap

RW0x0
1BG_PWRDN

MLB bandgap cell enable.

0x0: The MLB bandgap cell is powered (enabled)

0x1: The MLB bandgap cell is disabled

RW0x0
0CLK_PWRDN

Enable the MLB differential clock receiver.

0x0: MLB differential clock receiver is enabled

0x1: MLB differential clock receiver is disabled

RW0x1
Table 18-212 CTRL_CORE_EVE1_IRQ_0_1
Address Offset0x0000 07A0
Physical Address0x4A00 27A0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE1_IRQ_1RESERVEDEVE1_IRQ_0
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16EVE1_IRQ_1RW0x2
15:9RESERVEDR0x0
8:0EVE1_IRQ_0RW0x1
Table 18-213 CTRL_CORE_EVE1_IRQ_2_3
Address Offset0x0000 07A4
Physical Address0x4A00 27A4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE1_IRQ_3RESERVEDEVE1_IRQ_2
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16EVE1_IRQ_3RW0x4
15:9RESERVEDR0x0
8:0EVE1_IRQ_2RW0x3
Table 18-214 CTRL_CORE_EVE1_IRQ_4_5
Address Offset0x0000 07A8
Physical Address0x4A00 27A8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE1_IRQ_5RESERVEDEVE1_IRQ_4
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16EVE1_IRQ_5RW0x6
15:9RESERVEDR0x0
8:0EVE1_IRQ_4RW0x5
Table 18-215 CTRL_CORE_EVE1_IRQ_6_7
Address Offset0x0000 07AC
Physical Address0x4A00 27ACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE1_IRQ_7RESERVEDEVE1_IRQ_6
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16EVE1_IRQ_7RW0x8
15:9RESERVEDR0x0
8:0EVE1_IRQ_6RW0x7
Table 18-216 CTRL_CORE_EVE2_IRQ_0_1
Address Offset0x0000 07B0
Physical Address0x4A00 27B0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE2_IRQ_1RESERVEDEVE2_IRQ_0
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16EVE2_IRQ_1RW0x2
15:9RESERVEDR0x0
8:0EVE2_IRQ_0RW0x1
Table 18-217 CTRL_CORE_EVE2_IRQ_2_3
Address Offset0x0000 07B4
Physical Address0x4A00 27B4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE2_IRQ_3RESERVEDEVE2_IRQ_2
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16EVE2_IRQ_3RW0x4
15:9RESERVEDR0x0
8:0EVE2_IRQ_2RW0x3
Table 18-218 CTRL_CORE_EVE2_IRQ_4_5
Address Offset0x0000 07B8
Physical Address0x4A00 27B8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE2_IRQ_5RESERVEDEVE2_IRQ_4
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16EVE2_IRQ_5RW0x6
15:9RESERVEDR0x0
8:0EVE2_IRQ_4RW0x5
Table 18-219 CTRL_CORE_EVE2_IRQ_6_7
Address Offset0x0000 07BC
Physical Address0x4A00 27BCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEVE2_IRQ_7RESERVEDEVE2_IRQ_6
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16EVE2_IRQ_7RW0x8
15:9RESERVEDR0x0
8:0EVE2_IRQ_6RW0x7
Table 18-220 CTRL_CORE_IPU1_IRQ_23_24
Address Offset0x0000 07E0
Physical Address0x4A00 27E0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_24RESERVEDIPU1_IRQ_23
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_24RW0x30
15:9RESERVEDR0x0
8:0IPU1_IRQ_23RW0x14
Table 18-221 CTRL_CORE_IPU1_IRQ_25_26
Address Offset0x0000 07E4
Physical Address0x4A00 27E4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_26RESERVEDIPU1_IRQ_25
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_26RW0x60
15:9RESERVEDR0x0
8:0IPU1_IRQ_25RW0x0
Table 18-222 CTRL_CORE_IPU1_IRQ_27_28
Address Offset0x0000 07E8
Physical Address0x4A00 27E8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_28RESERVEDIPU1_IRQ_27
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_28RW0x7F
15:9RESERVEDR0x0
8:0IPU1_IRQ_27RW0x7E
Table 18-223 CTRL_CORE_IPU1_IRQ_29_30
Address Offset0x0000 07EC
Physical Address0x4A00 27ECInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_30RESERVEDIPU1_IRQ_29
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_30RW0x81
15:9RESERVEDR0x0
8:0IPU1_IRQ_29RW0x80
Table 18-224 CTRL_CORE_IPU1_IRQ_31_32
Address Offset0x0000 07F0
Physical Address0x4A00 27F0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_32RESERVEDIPU1_IRQ_31
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_32RW0x13
15:9RESERVEDR0x0
8:0IPU1_IRQ_31RW0x82
Table 18-225 CTRL_CORE_IPU1_IRQ_33_34
Address Offset0x0000 07F4
Physical Address0x4A00 27F4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_34RESERVEDIPU1_IRQ_33
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_34RW0x7
15:9RESERVEDR0x0
8:0IPU1_IRQ_33RW0x83
Table 18-226 CTRL_CORE_IPU1_IRQ_35_36
Address Offset0x0000 07F8
Physical Address0x4A00 27F8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_36RESERVEDIPU1_IRQ_35
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_36RW0x9
15:9RESERVEDR0x0
8:0IPU1_IRQ_35RW0x8
Table 18-227 CTRL_CORE_IPU1_IRQ_37_38
Address Offset0x0000 07FC
Physical Address0x4A00 27FCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_38RESERVEDIPU1_IRQ_37
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_38RW0x84
15:9RESERVEDR0x0
8:0IPU1_IRQ_37RW0xA
Table 18-228 CTRL_CORE_IPU1_IRQ_39_40
Address Offset0x0000 0800
Physical Address0x4A00 2800InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_40RESERVEDIPU1_IRQ_39
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_40RW0x63
15:9RESERVEDR0x0
8:0IPU1_IRQ_39RW0x62
Table 18-229 CTRL_CORE_IPU1_IRQ_41_42
Address Offset0x0000 0804
Physical Address0x4A00 2804InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_42RESERVEDIPU1_IRQ_41
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_42RW0x34
15:9RESERVEDR0x0
8:0IPU1_IRQ_41RW0x33
Table 18-230 CTRL_CORE_IPU1_IRQ_43_44
Address Offset0x0000 0808
Physical Address0x4A00 2808InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_44RESERVEDIPU1_IRQ_43
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_44RW0x39
15:9RESERVEDR0x0
8:0IPU1_IRQ_43RW0x38
Table 18-231 CTRL_CORE_IPU1_IRQ_45_46
Address Offset0x0000 080C
Physical Address0x4A00 280CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_46RESERVEDIPU1_IRQ_45
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_46RW0x5
15:9RESERVEDR0x0
8:0IPU1_IRQ_45RW0x45
Table 18-232 CTRL_CORE_IPU1_IRQ_47_48
Address Offset0x0000 0810
Physical Address0x4A00 2810InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_48RESERVEDIPU1_IRQ_47
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_48RW0xE
15:9RESERVEDR0x0
8:0IPU1_IRQ_47RW0x85
Table 18-233 CTRL_CORE_IPU1_IRQ_49_50
Address Offset0x0000 0814
Physical Address0x4A00 2814InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_50RESERVEDIPU1_IRQ_49
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_50RW0x86
15:9RESERVEDR0x0
8:0IPU1_IRQ_49RW0x42
Table 18-234 CTRL_CORE_IPU1_IRQ_51_52
Address Offset0x0000 0818
Physical Address0x4A00 2818InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_52RESERVEDIPU1_IRQ_51
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_52RW0x19
15:9RESERVEDR0x0
8:0IPU1_IRQ_51RW0x18
Table 18-235 CTRL_CORE_IPU1_IRQ_53_54
Address Offset0x0000 081C
Physical Address0x4A00 281CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_54RESERVEDIPU1_IRQ_53
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_54RW0x23
15:9RESERVEDR0x0
8:0IPU1_IRQ_53RW0x22
Table 18-236 CTRL_CORE_IPU1_IRQ_55_56
Address Offset0x0000 0820
Physical Address0x4A00 2820InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_56RESERVEDIPU1_IRQ_55
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_56RW0x2A
15:9RESERVEDR0x0
8:0IPU1_IRQ_55RW0x28
Table 18-237 CTRL_CORE_IPU1_IRQ_57_58
Address Offset0x0000 0824
Physical Address0x4A00 2824InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_58RESERVEDIPU1_IRQ_57
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_58RW0x3D
15:9RESERVEDR0x0
8:0IPU1_IRQ_57RW0x3C
Table 18-238 CTRL_CORE_IPU1_IRQ_59_60
Address Offset0x0000 0828
Physical Address0x4A00 2828InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_60RESERVEDIPU1_IRQ_59
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_60RW0x0
15:9RESERVEDR0x0
8:0IPU1_IRQ_59RW0x32
Table 18-239 CTRL_CORE_IPU1_IRQ_61_62
Address Offset0x0000 082C
Physical Address0x4A00 282CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_62RESERVEDIPU1_IRQ_61
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_62RW0x16
15:9RESERVEDR0x0
8:0IPU1_IRQ_61RW0x0
Table 18-240 CTRL_CORE_IPU1_IRQ_63_64
Address Offset0x0000 0830
Physical Address0x4A00 2830InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_64RESERVEDIPU1_IRQ_63
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_64RW0x6C
15:9RESERVEDR0x0
8:0IPU1_IRQ_63RW0x53
Table 18-241 CTRL_CORE_IPU1_IRQ_65_66
Address Offset0x0000 0834
Physical Address0x4A00 2834InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_66RESERVEDIPU1_IRQ_65
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_66RW0x4E
15:9RESERVEDR0x0
8:0IPU1_IRQ_65RW0x78
Table 18-242 CTRL_CORE_IPU1_IRQ_67_68
Address Offset0x0000 0838
Physical Address0x4A00 2838InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_68RESERVEDIPU1_IRQ_67
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_68RW0x59
15:9RESERVEDR0x0
8:0IPU1_IRQ_67RW0x51
Table 18-243 CTRL_CORE_IPU1_IRQ_69_70
Address Offset0x0000 083C
Physical Address0x4A00 283CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_70RESERVEDIPU1_IRQ_69
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_70RW0x0
15:9RESERVEDR0x0
8:0IPU1_IRQ_69RW0x0
Table 18-244 CTRL_CORE_IPU1_IRQ_71_72
Address Offset0x0000 0840
Physical Address0x4A00 2840InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_72RESERVEDIPU1_IRQ_71
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_72RW0x76
15:9RESERVEDR0x0
8:0IPU1_IRQ_71RW0x77
Table 18-245 CTRL_CORE_IPU1_IRQ_73_74
Address Offset0x0000 0844
Physical Address0x4A00 2844InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_74RESERVEDIPU1_IRQ_73
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_74RW0x49
15:9RESERVEDR0x0
8:0IPU1_IRQ_73RW0x48
Table 18-246 CTRL_CORE_IPU1_IRQ_75_76
Address Offset0x0000 0848
Physical Address0x4A00 2848InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_76RESERVEDIPU1_IRQ_75
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_76RW0x57
15:9RESERVEDR0x0
8:0IPU1_IRQ_75RW0x75
Table 18-247 CTRL_CORE_IPU1_IRQ_77_78
Address Offset0x0000 084C
Physical Address0x4A00 284CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_78RESERVEDIPU1_IRQ_77
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU1_IRQ_78RW0x3E
15:9RESERVEDR0x0
8:0IPU1_IRQ_77RW0x58
Table 18-248 CTRL_CORE_IPU1_IRQ_79_80
Address Offset0x0000 0850
Physical Address0x4A00 2850InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU1_IRQ_79
BitsField NameDescriptionTypeReset
31:9RESERVEDR0x0
8:0IPU1_IRQ_79RW0x3F
Table 18-249 CTRL_CORE_IPU2_IRQ_23_24
Address Offset0x0000 0854
Physical Address0x4A00 2854InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_24RESERVEDIPU2_IRQ_23
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_24RW0x30
15:9RESERVEDR0x0
8:0IPU2_IRQ_23RW0x14
Table 18-250 CTRL_CORE_IPU2_IRQ_25_26
Address Offset0x0000 0858
Physical Address0x4A00 2858InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_26RESERVEDIPU2_IRQ_25
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_26RW0x60
15:9RESERVEDR0x0
8:0IPU2_IRQ_25RW0x0
Table 18-251 CTRL_CORE_IPU2_IRQ_27_28
Address Offset0x0000 085C
Physical Address0x4A00 285CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_28RESERVEDIPU2_IRQ_27
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_28RW0x7F
15:9RESERVEDR0x0
8:0IPU2_IRQ_27RW0x7E
Table 18-252 CTRL_CORE_IPU2_IRQ_29_30
Address Offset0x0000 0860
Physical Address0x4A00 2860InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_30RESERVEDIPU2_IRQ_29
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_30RW0x81
15:9RESERVEDR0x0
8:0IPU2_IRQ_29RW0x80
Table 18-253 CTRL_CORE_IPU2_IRQ_31_32
Address Offset0x0000 0864
Physical Address0x4A00 2864InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_32RESERVEDIPU2_IRQ_31
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_32RW0x13
15:9RESERVEDR0x0
8:0IPU2_IRQ_31RW0x82
Table 18-254 CTRL_CORE_IPU2_IRQ_33_34
Address Offset0x0000 0868
Physical Address0x4A00 2868InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_34RESERVEDIPU2_IRQ_33
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_34RW0x7
15:9RESERVEDR0x0
8:0IPU2_IRQ_33RW0x83
Table 18-255 CTRL_CORE_IPU2_IRQ_35_36
Address Offset0x0000 086C
Physical Address0x4A00 286CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_36RESERVEDIPU2_IRQ_35
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_36RW0x9
15:9RESERVEDR0x0
8:0IPU2_IRQ_35RW0x8
Table 18-256 CTRL_CORE_IPU2_IRQ_37_38
Address Offset0x0000 0870
Physical Address0x4A00 2870InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_38RESERVEDIPU2_IRQ_37
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_38RW0x84
15:9RESERVEDR0x0
8:0IPU2_IRQ_37RW0xA
Table 18-257 CTRL_CORE_IPU2_IRQ_39_40
Address Offset0x0000 0874
Physical Address0x4A00 2874InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_40RESERVEDIPU2_IRQ_39
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_40RW0x63
15:9RESERVEDR0x0
8:0IPU2_IRQ_39RW0x62
Table 18-258 CTRL_CORE_IPU2_IRQ_41_42
Address Offset0x0000 0878
Physical Address0x4A00 2878InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_42RESERVEDIPU2_IRQ_41
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_42RW0x34
15:9RESERVEDR0x0
8:0IPU2_IRQ_41RW0x33
Table 18-259 CTRL_CORE_IPU2_IRQ_43_44
Address Offset0x0000 087C
Physical Address0x4A00 287CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_44RESERVEDIPU2_IRQ_43
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_44RW0x39
15:9RESERVEDR0x0
8:0IPU2_IRQ_43RW0x38
Table 18-260 CTRL_CORE_IPU2_IRQ_45_46
Address Offset0x0000 0880
Physical Address0x4A00 2880InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_46RESERVEDIPU2_IRQ_45
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_46RW0x5
15:9RESERVEDR0x0
8:0IPU2_IRQ_45RW0x45
Table 18-261 CTRL_CORE_IPU2_IRQ_47_48
Address Offset0x0000 0884
Physical Address0x4A00 2884InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_48RESERVEDIPU2_IRQ_47
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_48RW0xE
15:9RESERVEDR0x0
8:0IPU2_IRQ_47RW0x85
Table 18-262 CTRL_CORE_IPU2_IRQ_49_50
Address Offset0x0000 0888
Physical Address0x4A00 2888InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_50RESERVEDIPU2_IRQ_49
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_50RW0x86
15:9RESERVEDR0x0
8:0IPU2_IRQ_49RW0x42
Table 18-263 CTRL_CORE_IPU2_IRQ_51_52
Address Offset0x0000 088C
Physical Address0x4A00 288CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_52RESERVEDIPU2_IRQ_51
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_52RW0x19
15:9RESERVEDR0x0
8:0IPU2_IRQ_51RW0x18
Table 18-264 CTRL_CORE_IPU2_IRQ_53_54
Address Offset0x0000 0890
Physical Address0x4A00 2890InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_54RESERVEDIPU2_IRQ_53
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_54RW0x23
15:9RESERVEDR0x0
8:0IPU2_IRQ_53RW0x22
Table 18-265 CTRL_CORE_IPU2_IRQ_55_56
Address Offset0x0000 0894
Physical Address0x4A00 2894InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_56RESERVEDIPU2_IRQ_55
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_56RW0x2A
15:9RESERVEDR0x0
8:0IPU2_IRQ_55RW0x28
Table 18-266 CTRL_CORE_IPU2_IRQ_57_58
Address Offset0x0000 0898
Physical Address0x4A00 2898InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_58RESERVEDIPU2_IRQ_57
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_58RW0x3D
15:9RESERVEDR0x0
8:0IPU2_IRQ_57RW0x3C
Table 18-267 CTRL_CORE_IPU2_IRQ_59_60
Address Offset0x0000 089C
Physical Address0x4A00 289CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_60RESERVEDIPU2_IRQ_59
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_60RW0x0
15:9RESERVEDR0x0
8:0IPU2_IRQ_59RW0x32
Table 18-268 CTRL_CORE_IPU2_IRQ_61_62
Address Offset0x0000 08A0
Physical Address0x4A00 28A0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_62RESERVEDIPU2_IRQ_61
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_62RW0x16
15:9RESERVEDR0x0
8:0IPU2_IRQ_61RW0x0
Table 18-269 CTRL_CORE_IPU2_IRQ_63_64
Address Offset0x0000 08A4
Physical Address0x4A00 28A4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_64RESERVEDIPU2_IRQ_63
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_64RW0x6C
15:9RESERVEDR0x0
8:0IPU2_IRQ_63RW0x53
Table 18-270 CTRL_CORE_IPU2_IRQ_65_66
Address Offset0x0000 08A8
Physical Address0x4A00 28A8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_66RESERVEDIPU2_IRQ_65
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_66RW0x4E
15:9RESERVEDR0x0
8:0IPU2_IRQ_65RW0x78
Table 18-271 CTRL_CORE_IPU2_IRQ_67_68
Address Offset0x0000 08AC
Physical Address0x4A00 28ACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_68RESERVEDIPU2_IRQ_67
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_68RW0x59
15:9RESERVEDR0x0
8:0IPU2_IRQ_67RW0x51
Table 18-272 CTRL_CORE_IPU2_IRQ_69_70
Address Offset0x0000 08B0
Physical Address0x4A00 28B0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_70RESERVEDIPU2_IRQ_69
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_70RW0x0
15:9RESERVEDR0x0
8:0IPU2_IRQ_69RW0x0
Table 18-273 CTRL_CORE_IPU2_IRQ_71_72
Address Offset0x0000 08B4
Physical Address0x4A00 28B4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_72RESERVEDIPU2_IRQ_71
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_72RW0x76
15:9RESERVEDR0x0
8:0IPU2_IRQ_71RW0x77
Table 18-274 CTRL_CORE_IPU2_IRQ_73_74
Address Offset0x0000 08B8
Physical Address0x4A00 28B8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_74RESERVEDIPU2_IRQ_73
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_74RW0x49
15:9RESERVEDR0x0
8:0IPU2_IRQ_73RW0x48
Table 18-275 CTRL_CORE_IPU2_IRQ_75_76
Address Offset0x0000 08BC
Physical Address0x4A00 28BCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_76RESERVEDIPU2_IRQ_75
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_76RW0x57
15:9RESERVEDR0x0
8:0IPU2_IRQ_75RW0x75
Table 18-276 CTRL_CORE_IPU2_IRQ_77_78
Address Offset0x0000 08C0
Physical Address0x4A00 28C0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_78RESERVEDIPU2_IRQ_77
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16IPU2_IRQ_78RW0x3E
15:9RESERVEDR0x0
8:0IPU2_IRQ_77RW0x58
Table 18-277 CTRL_CORE_IPU2_IRQ_79_80
Address Offset0x0000 08C4
Physical Address0x4A00 28C4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDIPU2_IRQ_79
BitsField NameDescriptionTypeReset
31:9RESERVEDR0x0
8:0IPU2_IRQ_79RW0x3F
Table 18-278 CTRL_CORE_DSP1_IRQ_32_33
Address Offset0x0000 0948
Physical Address0x4A00 2948InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_33RESERVEDDSP1_IRQ_32
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_33RW0x2
15:9RESERVEDR0x0
8:0DSP1_IRQ_32RW0x1
Table 18-279 CTRL_CORE_DSP1_IRQ_34_35
Address Offset0x0000 094C
Physical Address0x4A00 294CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_35RESERVEDDSP1_IRQ_34
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_35RW0x4
15:9RESERVEDR0x0
8:0DSP1_IRQ_34RW0x3
Table 18-280 CTRL_CORE_DSP1_IRQ_36_37
Address Offset0x0000 0950
Physical Address0x4A00 2950InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_37RESERVEDDSP1_IRQ_36
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_37RW0x6
15:9RESERVEDR0x0
8:0DSP1_IRQ_36RW0x5
Table 18-281 CTRL_CORE_DSP1_IRQ_38_39
Address Offset0x0000 0954
Physical Address0x4A00 2954InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_39RESERVEDDSP1_IRQ_38
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_39RW0x8
15:9RESERVEDR0x0
8:0DSP1_IRQ_38RW0x7
Table 18-282 CTRL_CORE_DSP1_IRQ_40_41
Address Offset0x0000 0958
Physical Address0x4A00 2958InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_41RESERVEDDSP1_IRQ_40
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_41RW0xA
15:9RESERVEDR0x0
8:0DSP1_IRQ_40RW0x9
Table 18-283 CTRL_CORE_DSP1_IRQ_42_43
Address Offset0x0000 095C
Physical Address0x4A00 295CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_43RESERVEDDSP1_IRQ_42
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_43RW0xC
15:9RESERVEDR0x0
8:0DSP1_IRQ_42RW0xB
Table 18-284 CTRL_CORE_DSP1_IRQ_44_45
Address Offset0x0000 0960
Physical Address0x4A00 2960InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_45RESERVEDDSP1_IRQ_44
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_45RW0xE
15:9RESERVEDR0x0
8:0DSP1_IRQ_44RW0xD
Table 18-285 CTRL_CORE_DSP1_IRQ_46_47
Address Offset0x0000 0964
Physical Address0x4A00 2964InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_47RESERVEDDSP1_IRQ_46
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_47RW0x10
15:9RESERVEDR0x0
8:0DSP1_IRQ_46RW0xF
Table 18-286 CTRL_CORE_DSP1_IRQ_48_49
Address Offset0x0000 0968
Physical Address0x4A00 2968InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_49RESERVEDDSP1_IRQ_48
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_49RW0x12
15:9RESERVEDR0x0
8:0DSP1_IRQ_48RW0x11
Table 18-287 CTRL_CORE_DSP1_IRQ_50_51
Address Offset0x0000 096C
Physical Address0x4A00 296CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_51RESERVEDDSP1_IRQ_50
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_51RW0x14
15:9RESERVEDR0x0
8:0DSP1_IRQ_50RW0x13
Table 18-288 CTRL_CORE_DSP1_IRQ_52_53
Address Offset0x0000 0970
Physical Address0x4A00 2970InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_53RESERVEDDSP1_IRQ_52
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_53RW0x16
15:9RESERVEDR0x0
8:0DSP1_IRQ_52RW0x15
Table 18-289 CTRL_CORE_DSP1_IRQ_54_55
Address Offset0x0000 0974
Physical Address0x4A00 2974InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_55RESERVEDDSP1_IRQ_54
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_55RW0x18
15:9RESERVEDR0x0
8:0DSP1_IRQ_54RW0x17
Table 18-290 CTRL_CORE_DSP1_IRQ_56_57
Address Offset0x0000 0978
Physical Address0x4A00 2978InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_57RESERVEDDSP1_IRQ_56
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_57RW0x1A
15:9RESERVEDR0x0
8:0DSP1_IRQ_56RW0x19
Table 18-291 CTRL_CORE_DSP1_IRQ_58_59
Address Offset0x0000 097C
Physical Address0x4A00 297CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_59RESERVEDDSP1_IRQ_58
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_59RW0x1C
15:9RESERVEDR0x0
8:0DSP1_IRQ_58RW0x1B
Table 18-292 CTRL_CORE_DSP1_IRQ_60_61
Address Offset0x0000 0980
Physical Address0x4A00 2980InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_61RESERVEDDSP1_IRQ_60
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_61RW0x1E
15:9RESERVEDR0x0
8:0DSP1_IRQ_60RW0x1D
Table 18-293 CTRL_CORE_DSP1_IRQ_62_63
Address Offset0x0000 0984
Physical Address0x4A00 2984InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_63RESERVEDDSP1_IRQ_62
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_63RW0x20
15:9RESERVEDR0x0
8:0DSP1_IRQ_62RW0x1F
Table 18-294 CTRL_CORE_DSP1_IRQ_64_65
Address Offset0x0000 0988
Physical Address0x4A00 2988InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_65RESERVEDDSP1_IRQ_64
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_65RW0x22
15:9RESERVEDR0x0
8:0DSP1_IRQ_64RW0x21
Table 18-295 CTRL_CORE_DSP1_IRQ_66_67
Address Offset0x0000 098C
Physical Address0x4A00 298CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_67RESERVEDDSP1_IRQ_66
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_67RW0x24
15:9RESERVEDR0x0
8:0DSP1_IRQ_66RW0x23
Table 18-296 CTRL_CORE_DSP1_IRQ_68_69
Address Offset0x0000 0990
Physical Address0x4A00 2990InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_69RESERVEDDSP1_IRQ_68
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_69RW0x26
15:9RESERVEDR0x0
8:0DSP1_IRQ_68RW0x25
Table 18-297 CTRL_CORE_DSP1_IRQ_70_71
Address Offset0x0000 0994
Physical Address0x4A00 2994InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_71RESERVEDDSP1_IRQ_70
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_71RW0x28
15:9RESERVEDR0x0
8:0DSP1_IRQ_70RW0x27
Table 18-298 CTRL_CORE_DSP1_IRQ_72_73
Address Offset0x0000 0998
Physical Address0x4A00 2998InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_73RESERVEDDSP1_IRQ_72
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_73RW0x2A
15:9RESERVEDR0x0
8:0DSP1_IRQ_72RW0x29
Table 18-299 CTRL_CORE_DSP1_IRQ_74_75
Address Offset0x0000 099C
Physical Address0x4A00 299CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_75RESERVEDDSP1_IRQ_74
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_75RW0x2C
15:9RESERVEDR0x0
8:0DSP1_IRQ_74RW0x2B
Table 18-300 CTRL_CORE_DSP1_IRQ_76_77
Address Offset0x0000 09A0
Physical Address0x4A00 29A0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_77RESERVEDDSP1_IRQ_76
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_77RW0x2E
15:9RESERVEDR0x0
8:0DSP1_IRQ_76RW0x2D
Table 18-301 CTRL_CORE_DSP1_IRQ_78_79
Address Offset0x0000 09A4
Physical Address0x4A00 29A4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_79RESERVEDDSP1_IRQ_78
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_79RW0x30
15:9RESERVEDR0x0
8:0DSP1_IRQ_78RW0x2F
Table 18-302 CTRL_CORE_DSP1_IRQ_80_81
Address Offset0x0000 09A8
Physical Address0x4A00 29A8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_81RESERVEDDSP1_IRQ_80
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_81RW0x32
15:9RESERVEDR0x0
8:0DSP1_IRQ_80RW0x31
Table 18-303 CTRL_CORE_DSP1_IRQ_82_83
Address Offset0x0000 09AC
Physical Address0x4A00 29ACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_83RESERVEDDSP1_IRQ_82
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_83RW0x34
15:9RESERVEDR0x0
8:0DSP1_IRQ_82RW0x33
Table 18-304 CTRL_CORE_DSP1_IRQ_84_85
Address Offset0x0000 09B0
Physical Address0x4A00 29B0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_85RESERVEDDSP1_IRQ_84
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_85RW0x36
15:9RESERVEDR0x0
8:0DSP1_IRQ_84RW0x35
Table 18-305 CTRL_CORE_DSP1_IRQ_86_87
Address Offset0x0000 09B4
Physical Address0x4A00 29B4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_87RESERVEDDSP1_IRQ_86
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_87RW0x38
15:9RESERVEDR0x0
8:0DSP1_IRQ_86RW0x37
Table 18-306 CTRL_CORE_DSP1_IRQ_88_89
Address Offset0x0000 09B8
Physical Address0x4A00 29B8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_89RESERVEDDSP1_IRQ_88
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_89RW0x3A
15:9RESERVEDR0x0
8:0DSP1_IRQ_88RW0x39
Table 18-307 CTRL_CORE_DSP1_IRQ_90_91
Address Offset0x0000 09BC
Physical Address0x4A00 29BCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_91RESERVEDDSP1_IRQ_90
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_91RW0x3C
15:9RESERVEDR0x0
8:0DSP1_IRQ_90RW0x3B
Table 18-308 CTRL_CORE_DSP1_IRQ_92_93
Address Offset0x0000 09C0
Physical Address0x4A00 29C0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_93RESERVEDDSP1_IRQ_92
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_93RW0x3E
15:9RESERVEDR0x0
8:0DSP1_IRQ_92RW0x3D
Table 18-309 CTRL_CORE_DSP1_IRQ_94_95
Address Offset0x0000 09C4
Physical Address0x4A00 29C4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP1_IRQ_95RESERVEDDSP1_IRQ_94
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP1_IRQ_95RW0x40
15:9RESERVEDR0x0
8:0DSP1_IRQ_94RW0x3F
Table 18-310 CTRL_CORE_DSP2_IRQ_32_33
Address Offset0x0000 09C8
Physical Address0x4A00 29C8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_33RESERVEDDSP2_IRQ_32
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_33RW0x2
15:9RESERVEDR0x0
8:0DSP2_IRQ_32RW0x1
Table 18-311 CTRL_CORE_DSP2_IRQ_34_35
Address Offset0x0000 09CC
Physical Address0x4A00 29CCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_35RESERVEDDSP2_IRQ_34
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_35RW0x4
15:9RESERVEDR0x0
8:0DSP2_IRQ_34RW0x3
Table 18-312 CTRL_CORE_DSP2_IRQ_36_37
Address Offset0x0000 09D0
Physical Address0x4A00 29D0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_37RESERVEDDSP2_IRQ_36
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_37RW0x6
15:9RESERVEDR0x0
8:0DSP2_IRQ_36RW0x5
Table 18-313 CTRL_CORE_DSP2_IRQ_38_39
Address Offset0x0000 09D4
Physical Address0x4A00 29D4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_39RESERVEDDSP2_IRQ_38
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_39RW0x8
15:9RESERVEDR0x0
8:0DSP2_IRQ_38RW0x7
Table 18-314 CTRL_CORE_DSP2_IRQ_40_41
Address Offset0x0000 09D8
Physical Address0x4A00 29D8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_41RESERVEDDSP2_IRQ_40
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_41RW0xA
15:9RESERVEDR0x0
8:0DSP2_IRQ_40RW0x9
Table 18-315 CTRL_CORE_DSP2_IRQ_42_43
Address Offset0x0000 09DC
Physical Address0x4A00 29DCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_43RESERVEDDSP2_IRQ_42
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_43RW0xC
15:9RESERVEDR0x0
8:0DSP2_IRQ_42RW0xB
Table 18-316 CTRL_CORE_DSP2_IRQ_44_45
Address Offset0x0000 09E0
Physical Address0x4A00 29E0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_45RESERVEDDSP2_IRQ_44
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_45RW0xE
15:9RESERVEDR0x0
8:0DSP2_IRQ_44RW0xD
Table 18-317 CTRL_CORE_DSP2_IRQ_46_47
Address Offset0x0000 09E4
Physical Address0x4A00 29E4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_47RESERVEDDSP2_IRQ_46
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_47RW0x10
15:9RESERVEDR0x0
8:0DSP2_IRQ_46RW0xF
Table 18-318 CTRL_CORE_DSP2_IRQ_48_49
Address Offset0x0000 09E8
Physical Address0x4A00 29E8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_49RESERVEDDSP2_IRQ_48
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_49RW0x12
15:9RESERVEDR0x0
8:0DSP2_IRQ_48RW0x11
Table 18-319 CTRL_CORE_DSP2_IRQ_50_51
Address Offset0x0000 09EC
Physical Address0x4A00 29ECInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_51RESERVEDDSP2_IRQ_50
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_51RW0x14
15:9RESERVEDR0x0
8:0DSP2_IRQ_50RW0x13
Table 18-320 CTRL_CORE_DSP2_IRQ_52_53
Address Offset0x0000 09F0
Physical Address0x4A00 29F0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_53RESERVEDDSP2_IRQ_52
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_53RW0x16
15:9RESERVEDR0x0
8:0DSP2_IRQ_52RW0x15
Table 18-321 CTRL_CORE_DSP2_IRQ_54_55
Address Offset0x0000 09F4
Physical Address0x4A00 29F4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_55RESERVEDDSP2_IRQ_54
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_55RW0x18
15:9RESERVEDR0x0
8:0DSP2_IRQ_54RW0x17
Table 18-322 CTRL_CORE_DSP2_IRQ_56_57
Address Offset0x0000 09F8
Physical Address0x4A00 29F8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_57RESERVEDDSP2_IRQ_56
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_57RW0x1A
15:9RESERVEDR0x0
8:0DSP2_IRQ_56RW0x19
Table 18-323 CTRL_CORE_DSP2_IRQ_58_59
Address Offset0x0000 09FC
Physical Address0x4A00 29FCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_59RESERVEDDSP2_IRQ_58
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_59RW0x1C
15:9RESERVEDR0x0
8:0DSP2_IRQ_58RW0x1B
Table 18-324 CTRL_CORE_DSP2_IRQ_60_61
Address Offset0x0000 0A00
Physical Address0x4A00 2A00InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_61RESERVEDDSP2_IRQ_60
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_61RW0x1E
15:9RESERVEDR0x0
8:0DSP2_IRQ_60RW0x1D
Table 18-325 CTRL_CORE_DSP2_IRQ_62_63
Address Offset0x0000 0A04
Physical Address0x4A00 2A04InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_63RESERVEDDSP2_IRQ_62
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_63RW0x20
15:9RESERVEDR0x0
8:0DSP2_IRQ_62RW0x1F
Table 18-326 CTRL_CORE_DSP2_IRQ_64_65
Address Offset0x0000 0A08
Physical Address0x4A00 2A08InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_65RESERVEDDSP2_IRQ_64
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_65RW0x22
15:9RESERVEDR0x0
8:0DSP2_IRQ_64RW0x21
Table 18-327 CTRL_CORE_DSP2_IRQ_66_67
Address Offset0x0000 0A0C
Physical Address0x4A00 2A0CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_67RESERVEDDSP2_IRQ_66
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_67RW0x24
15:9RESERVEDR0x0
8:0DSP2_IRQ_66RW0x23
Table 18-328 CTRL_CORE_DSP2_IRQ_68_69
Address Offset0x0000 0A10
Physical Address0x4A00 2A10InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_69RESERVEDDSP2_IRQ_68
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_69RW0x26
15:9RESERVEDR0x0
8:0DSP2_IRQ_68RW0x25
Table 18-329 CTRL_CORE_DSP2_IRQ_70_71
Address Offset0x0000 0A14
Physical Address0x4A00 2A14InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_71RESERVEDDSP2_IRQ_70
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_71RW0x28
15:9RESERVEDR0x0
8:0DSP2_IRQ_70RW0x27
Table 18-330 CTRL_CORE_DSP2_IRQ_72_73
Address Offset0x0000 0A18
Physical Address0x4A00 2A18InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_73RESERVEDDSP2_IRQ_72
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_73RW0x2A
15:9RESERVEDR0x0
8:0DSP2_IRQ_72RW0x29
Table 18-331 CTRL_CORE_DSP2_IRQ_74_75
Address Offset0x0000 0A1C
Physical Address0x4A00 2A1CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_75RESERVEDDSP2_IRQ_74
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_75RW0x2C
15:9RESERVEDR0x0
8:0DSP2_IRQ_74RW0x2B
Table 18-332 CTRL_CORE_DSP2_IRQ_76_77
Address Offset0x0000 0A20
Physical Address0x4A00 2A20InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_77RESERVEDDSP2_IRQ_76
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_77RW0x2E
15:9RESERVEDR0x0
8:0DSP2_IRQ_76RW0x2D
Table 18-333 CTRL_CORE_DSP2_IRQ_78_79
Address Offset0x0000 0A24
Physical Address0x4A00 2A24InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_79RESERVEDDSP2_IRQ_78
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_79RW0x30
15:9RESERVEDR0x0
8:0DSP2_IRQ_78RW0x2F
Table 18-334 CTRL_CORE_DSP2_IRQ_80_81
Address Offset0x0000 0A28
Physical Address0x4A00 2A28InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_81RESERVEDDSP2_IRQ_80
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_81RW0x32
15:9RESERVEDR0x0
8:0DSP2_IRQ_80RW0x31
Table 18-335 CTRL_CORE_DSP2_IRQ_82_83
Address Offset0x0000 0A2C
Physical Address0x4A00 2A2CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_83RESERVEDDSP2_IRQ_82
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_83RW0x34
15:9RESERVEDR0x0
8:0DSP2_IRQ_82RW0x33
Table 18-336 CTRL_CORE_DSP2_IRQ_84_85
Address Offset0x0000 0A30
Physical Address0x4A00 2A30InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_85RESERVEDDSP2_IRQ_84
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_85RW0x36
15:9RESERVEDR0x0
8:0DSP2_IRQ_84RW0x35
Table 18-337 CTRL_CORE_DSP2_IRQ_86_87
Address Offset0x0000 0A34
Physical Address0x4A00 2A34InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_87RESERVEDDSP2_IRQ_86
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_87RW0x38
15:9RESERVEDR0x0
8:0DSP2_IRQ_86RW0x37
Table 18-338 CTRL_CORE_DSP2_IRQ_88_89
Address Offset0x0000 0A38
Physical Address0x4A00 2A38InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_89RESERVEDDSP2_IRQ_88
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_89RW0x3A
15:9RESERVEDR0x0
8:0DSP2_IRQ_88RW0x39
Table 18-339 CTRL_CORE_DSP2_IRQ_90_91
Address Offset0x0000 0A3C
Physical Address0x4A00 2A3CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_91RESERVEDDSP2_IRQ_90
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_91RW0x3C
15:9RESERVEDR0x0
8:0DSP2_IRQ_90RW0x3B
Table 18-340 CTRL_CORE_DSP2_IRQ_92_93
Address Offset0x0000 0A40
Physical Address0x4A00 2A40InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_93RESERVEDDSP2_IRQ_92
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_93RW0x3E
15:9RESERVEDR0x0
8:0DSP2_IRQ_92RW0x3D
Table 18-341 CTRL_CORE_DSP2_IRQ_94_95
Address Offset0x0000 0A44
Physical Address0x4A00 2A44InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDSP2_IRQ_95RESERVEDDSP2_IRQ_94
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16DSP2_IRQ_95RW0x40
15:9RESERVEDR0x0
8:0DSP2_IRQ_94RW0x3F
Table 18-342 CTRL_CORE_MPU_IRQ_4_7
Address Offset0x0000 0A48
Physical Address0x4A00 2A48InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_7RESERVEDMPU_IRQ_4
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_7RW0x2
15:9RESERVEDR0x0
8:0MPU_IRQ_4RW0x1
Table 18-343 CTRL_CORE_MPU_IRQ_8_9
Address Offset0x0000 0A4C
Physical Address0x4A00 2A4CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_9RESERVEDMPU_IRQ_8
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_9RW0x4
15:9RESERVEDR0x0
8:0MPU_IRQ_8RW0x3
Table 18-344 CTRL_CORE_MPU_IRQ_10_11
Address Offset0x0000 0A50
Physical Address0x4A00 2A50InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_11RESERVEDMPU_IRQ_10
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_11RW0x6
15:9RESERVEDR0x0
8:0MPU_IRQ_10
Note: NOTE: This bit field is not functional
RW0x5
Table 18-345 CTRL_CORE_MPU_IRQ_12_13
Address Offset0x0000 0A54
Physical Address0x4A00 2A54InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_13RESERVEDMPU_IRQ_12
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_13RW0x8
15:9RESERVEDR0x0
8:0MPU_IRQ_12RW0x7
Table 18-346 CTRL_CORE_MPU_IRQ_14_15
Address Offset0x0000 0A58
Physical Address0x4A00 2A58InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_15RESERVEDMPU_IRQ_14
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_15RW0xA
15:9RESERVEDR0x0
8:0MPU_IRQ_14RW0x9
Table 18-347 CTRL_CORE_MPU_IRQ_16_17
Address Offset0x0000 0A5C
Physical Address0x4A00 2A5CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_17RESERVEDMPU_IRQ_16
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_17RW0xC
15:9RESERVEDR0x0
8:0MPU_IRQ_16RW0xB
Table 18-348 CTRL_CORE_MPU_IRQ_18_19
Address Offset0x0000 0A60
Physical Address0x4A00 2A60InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_19RESERVEDMPU_IRQ_18
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_19RW0xE
15:9RESERVEDR0x0
8:0MPU_IRQ_18RW0xD
Table 18-349 CTRL_CORE_MPU_IRQ_20_21
Address Offset0x0000 0A64
Physical Address0x4A00 2A64InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_21RESERVEDMPU_IRQ_20
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_21RW0x10
15:9RESERVEDR0x0
8:0MPU_IRQ_20RW0xF
Table 18-350 CTRL_CORE_MPU_IRQ_22_23
Address Offset0x0000 0A68
Physical Address0x4A00 2A68InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_23RESERVEDMPU_IRQ_22
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_23RW0x12
15:9RESERVEDR0x0
8:0MPU_IRQ_22RW0x11
Table 18-351 CTRL_CORE_MPU_IRQ_24_25
Address Offset0x0000 0A6C
Physical Address0x4A00 2A6CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_25RESERVEDMPU_IRQ_24
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_25RW0x14
15:9RESERVEDR0x0
8:0MPU_IRQ_24RW0x13
Table 18-352 CTRL_CORE_MPU_IRQ_26_27
Address Offset0x0000 0A70
Physical Address0x4A00 2A70InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_27RESERVEDMPU_IRQ_26
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_27RW0x16
15:9RESERVEDR0x0
8:0MPU_IRQ_26RW0x15
Table 18-353 CTRL_CORE_MPU_IRQ_28_29
Address Offset0x0000 0A74
Physical Address0x4A00 2A74InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_29RESERVEDMPU_IRQ_28
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_29RW0x18
15:9RESERVEDR0x0
8:0MPU_IRQ_28RW0x17
Table 18-354 CTRL_CORE_MPU_IRQ_30_31
Address Offset0x0000 0A78
Physical Address0x4A00 2A78InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_31RESERVEDMPU_IRQ_30
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_31RW0x1A
15:9RESERVEDR0x0
8:0MPU_IRQ_30RW0x19
Table 18-355 CTRL_CORE_MPU_IRQ_32_33
Address Offset0x0000 0A7C
Physical Address0x4A00 2A7CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_33RESERVEDMPU_IRQ_32
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_33RW0x1C
15:9RESERVEDR0x0
8:0MPU_IRQ_32RW0x1B
Table 18-356 CTRL_CORE_MPU_IRQ_34_35
Address Offset0x0000 0A80
Physical Address0x4A00 2A80InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_35RESERVEDMPU_IRQ_34
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_35RW0x1E
15:9RESERVEDR0x0
8:0MPU_IRQ_34RW0x1D
Table 18-357 CTRL_CORE_MPU_IRQ_36_37
Address Offset0x0000 0A84
Physical Address0x4A00 2A84InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_37RESERVEDMPU_IRQ_36
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_37RW0x20
15:9RESERVEDR0x0
8:0MPU_IRQ_36RW0x1F
Table 18-358 CTRL_CORE_MPU_IRQ_38_39
Address Offset0x0000 0A88
Physical Address0x4A00 2A88InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_39RESERVEDMPU_IRQ_38
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_39RW0x22
15:9RESERVEDR0x0
8:0MPU_IRQ_38RW0x21
Table 18-359 CTRL_CORE_MPU_IRQ_40_41
Address Offset0x0000 0A8C
Physical Address0x4A00 2A8CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_41RESERVEDMPU_IRQ_40
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_41RW0x24
15:9RESERVEDR0x0
8:0MPU_IRQ_40RW0x23
Table 18-360 CTRL_CORE_MPU_IRQ_42_43
Address Offset0x0000 0A90
Physical Address0x4A00 2A90InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_43RESERVEDMPU_IRQ_42
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_43RW0x26
15:9RESERVEDR0x0
8:0MPU_IRQ_42RW0x25
Table 18-361 CTRL_CORE_MPU_IRQ_44_45
Address Offset0x0000 0A94
Physical Address0x4A00 2A94InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_45RESERVEDMPU_IRQ_44
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_45RW0x28
15:9RESERVEDR0x0
8:0MPU_IRQ_44RW0x27
Table 18-362 CTRL_CORE_MPU_IRQ_46_47
Address Offset0x0000 0A98
Physical Address0x4A00 2A98InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_47RESERVEDMPU_IRQ_46
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_47RW0x2A
15:9RESERVEDR0x0
8:0MPU_IRQ_46RW0x29
Table 18-363 CTRL_CORE_MPU_IRQ_48_49
Address Offset0x0000 0A9C
Physical Address0x4A00 2A9CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_49RESERVEDMPU_IRQ_48
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_49RW0x2C
15:9RESERVEDR0x0
8:0MPU_IRQ_48RW0x2B
Table 18-364 CTRL_CORE_MPU_IRQ_50_51
Address Offset0x0000 0AA0
Physical Address0x4A00 2AA0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_51RESERVEDMPU_IRQ_50
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_51RW0x2E
15:9RESERVEDR0x0
8:0MPU_IRQ_50RW0x2D
Table 18-365 CTRL_CORE_MPU_IRQ_52_53
Address Offset0x0000 0AA4
Physical Address0x4A00 2AA4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_53RESERVEDMPU_IRQ_52
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_53RW0x30
15:9RESERVEDR0x0
8:0MPU_IRQ_52RW0x2F
Table 18-366 CTRL_CORE_MPU_IRQ_54_55
Address Offset0x0000 0AA8
Physical Address0x4A00 2AA8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_55RESERVEDMPU_IRQ_54
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_55RW0x32
15:9RESERVEDR0x0
8:0MPU_IRQ_54RW0x31
Table 18-367 CTRL_CORE_MPU_IRQ_56_57
Address Offset0x0000 0AAC
Physical Address0x4A00 2AACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_57RESERVEDMPU_IRQ_56
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_57RW0x34
15:9RESERVEDR0x0
8:0MPU_IRQ_56RW0x33
Table 18-368 CTRL_CORE_MPU_IRQ_58_59
Address Offset0x0000 0AB0
Physical Address0x4A00 2AB0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_59RESERVEDMPU_IRQ_58
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_59RW0x36
15:9RESERVEDR0x0
8:0MPU_IRQ_58RW0x35
Table 18-369 CTRL_CORE_MPU_IRQ_60_61
Address Offset0x0000 0AB4
Physical Address0x4A00 2AB4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_61RESERVEDMPU_IRQ_60
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_61RW0x38
15:9RESERVEDR0x0
8:0MPU_IRQ_60RW0x37
Table 18-370 CTRL_CORE_MPU_IRQ_62_63
Address Offset0x0000 0AB8
Physical Address0x4A00 2AB8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_63RESERVEDMPU_IRQ_62
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_63RW0x3A
15:9RESERVEDR0x0
8:0MPU_IRQ_62RW0x39
Table 18-371 CTRL_CORE_MPU_IRQ_64_65
Address Offset0x0000 0ABC
Physical Address0x4A00 2ABCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_65RESERVEDMPU_IRQ_64
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_65RW0x3C
15:9RESERVEDR0x0
8:0MPU_IRQ_64RW0x3B
Table 18-372 CTRL_CORE_MPU_IRQ_66_67
Address Offset0x0000 0AC0
Physical Address0x4A00 2AC0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_67RESERVEDMPU_IRQ_66
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_67RW0x3E
15:9RESERVEDR0x0
8:0MPU_IRQ_66RW0x3D
Table 18-373 CTRL_CORE_MPU_IRQ_68_69
Address Offset0x0000 0AC4
Physical Address0x4A00 2AC4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_69RESERVEDMPU_IRQ_68
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_69RW0x40
15:9RESERVEDR0x0
8:0MPU_IRQ_68RW0x3F
Table 18-374 CTRL_CORE_MPU_IRQ_70_71
Address Offset0x0000 0AC8
Physical Address0x4A00 2AC8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_71RESERVEDMPU_IRQ_70
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_71RW0x42
15:9RESERVEDR0x0
8:0MPU_IRQ_70RW0x41
Table 18-375 CTRL_CORE_MPU_IRQ_72_73
Address Offset0x0000 0ACC
Physical Address0x4A00 2ACCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_73RESERVEDMPU_IRQ_72
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_73RW0x44
15:9RESERVEDR0x0
8:0MPU_IRQ_72RW0x43
Table 18-376 CTRL_CORE_MPU_IRQ_74_75
Address Offset0x0000 0AD0
Physical Address0x4A00 2AD0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_75RESERVEDMPU_IRQ_74
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_75RW0x46
15:9RESERVEDR0x0
8:0MPU_IRQ_74RW0x45
Table 18-377 CTRL_CORE_MPU_IRQ_76_77
Address Offset0x0000 0AD4
Physical Address0x4A00 2AD4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_77RESERVEDMPU_IRQ_76
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_77RW0x48
15:9RESERVEDR0x0
8:0MPU_IRQ_76RW0x47
Table 18-378 CTRL_CORE_MPU_IRQ_78_79
Address Offset0x0000 0AD8
Physical Address0x4A00 2AD8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_79RESERVEDMPU_IRQ_78
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_79RW0x4A
15:9RESERVEDR0x0
8:0MPU_IRQ_78RW0x49
Table 18-379 CTRL_CORE_MPU_IRQ_80_81
Address Offset0x0000 0ADC
Physical Address0x4A00 2ADCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_81RESERVEDMPU_IRQ_80
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_81RW0x4C
15:9RESERVEDR0x0
8:0MPU_IRQ_80RW0x4B
Table 18-380 CTRL_CORE_MPU_IRQ_82_83
Address Offset0x0000 0AE0
Physical Address0x4A00 2AE0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_83RESERVEDMPU_IRQ_82
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_83RW0x4E
15:9RESERVEDR0x0
8:0MPU_IRQ_82RW0x4D
Table 18-381 CTRL_CORE_MPU_IRQ_84_85
Address Offset0x0000 0AE4
Physical Address0x4A00 2AE4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_85RESERVEDMPU_IRQ_84
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_85RW0x50
15:9RESERVEDR0x0
8:0MPU_IRQ_84RW0x4F
Table 18-382 CTRL_CORE_MPU_IRQ_86_87
Address Offset0x0000 0AE8
Physical Address0x4A00 2AE8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_87RESERVEDMPU_IRQ_86
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_87RW0x52
15:9RESERVEDR0x0
8:0MPU_IRQ_86RW0x51
Table 18-383 CTRL_CORE_MPU_IRQ_88_89
Address Offset0x0000 0AEC
Physical Address0x4A00 2AECInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_89RESERVEDMPU_IRQ_88
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_89RW0x54
15:9RESERVEDR0x0
8:0MPU_IRQ_88RW0x53
Table 18-384 CTRL_CORE_MPU_IRQ_90_91
Address Offset0x0000 0AF0
Physical Address0x4A00 2AF0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_91RESERVEDMPU_IRQ_90
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_91RW0x56
15:9RESERVEDR0x0
8:0MPU_IRQ_90RW0x55
Table 18-385 CTRL_CORE_MPU_IRQ_92_93
Address Offset0x0000 0AF4
Physical Address0x4A00 2AF4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_93RESERVEDMPU_IRQ_92
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_93RW0x58
15:9RESERVEDR0x0
8:0MPU_IRQ_92RW0x57
Table 18-386 CTRL_CORE_MPU_IRQ_94_95
Address Offset0x0000 0AF8
Physical Address0x4A00 2AF8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_95RESERVEDMPU_IRQ_94
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_95RW0x5A
15:9RESERVEDR0x0
8:0MPU_IRQ_94RW0x59
Table 18-387 CTRL_CORE_MPU_IRQ_96_97
Address Offset0x0000 0AFC
Physical Address0x4A00 2AFCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_97RESERVEDMPU_IRQ_96
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_97RW0x5C
15:9RESERVEDR0x0
8:0MPU_IRQ_96RW0x5B
Table 18-388 CTRL_CORE_MPU_IRQ_98_99
Address Offset0x0000 0B00
Physical Address0x4A00 2B00InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_99RESERVEDMPU_IRQ_98
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_99RW0x5E
15:9RESERVEDR0x0
8:0MPU_IRQ_98RW0x5D
Table 18-389 CTRL_CORE_MPU_IRQ_100_101
Address Offset0x0000 0B04
Physical Address0x4A00 2B04InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_101RESERVEDMPU_IRQ_100
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_101RW0x60
15:9RESERVEDR0x0
8:0MPU_IRQ_100RW0x18B
Table 18-390 CTRL_CORE_MPU_IRQ_102_103
Address Offset0x0000 0B08
Physical Address0x4A00 2B08InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_103RESERVEDMPU_IRQ_102
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_103RW0x62
15:9RESERVEDR0x0
8:0MPU_IRQ_102RW0x61
Table 18-391 CTRL_CORE_MPU_IRQ_104_105
Address Offset0x0000 0B0C
Physical Address0x4A00 2B0CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_105RESERVEDMPU_IRQ_104
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_105RW0x64
15:9RESERVEDR0x0
8:0MPU_IRQ_104RW0x63
Table 18-392 CTRL_CORE_MPU_IRQ_106_107
Address Offset0x0000 0B10
Physical Address0x4A00 2B10InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_107RESERVEDMPU_IRQ_106
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_107RW0x66
15:9RESERVEDR0x0
8:0MPU_IRQ_106RW0x65
Table 18-393 CTRL_CORE_MPU_IRQ_108_109
Address Offset0x0000 0B14
Physical Address0x4A00 2B14InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_109RESERVEDMPU_IRQ_108
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_109RW0x68
15:9RESERVEDR0x0
8:0MPU_IRQ_108RW0x67
Table 18-394 CTRL_CORE_MPU_IRQ_110_111
Address Offset0x0000 0B18
Physical Address0x4A00 2B18InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_111RESERVEDMPU_IRQ_110
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_111RW0x6A
15:9RESERVEDR0x0
8:0MPU_IRQ_110RW0x69
Table 18-395 CTRL_CORE_MPU_IRQ_112_113
Address Offset0x0000 0B1C
Physical Address0x4A00 2B1CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_113RESERVEDMPU_IRQ_112
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_113RW0x6C
15:9RESERVEDR0x0
8:0MPU_IRQ_112RW0x6B
Table 18-396 CTRL_CORE_MPU_IRQ_114_115
Address Offset0x0000 0B20
Physical Address0x4A00 2B20InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_115RESERVEDMPU_IRQ_114
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_115RW0x6E
15:9RESERVEDR0x0
8:0MPU_IRQ_114RW0x6D
Table 18-397 CTRL_CORE_MPU_IRQ_116_117
Address Offset0x0000 0B24
Physical Address0x4A00 2B24InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_117RESERVEDMPU_IRQ_116
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_117RW0x70
15:9RESERVEDR0x0
8:0MPU_IRQ_116RW0x6F
Table 18-398 CTRL_CORE_MPU_IRQ_118_119
Address Offset0x0000 0B28
Physical Address0x4A00 2B28InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_119RESERVEDMPU_IRQ_118
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_119RW0x72
15:9RESERVEDR0x0
8:0MPU_IRQ_118RW0x71
Table 18-399 CTRL_CORE_MPU_IRQ_120_121
Address Offset0x0000 0B2C
Physical Address0x4A00 2B2CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_121RESERVEDMPU_IRQ_120
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_121RW0x74
15:9RESERVEDR0x0
8:0MPU_IRQ_120RW0x73
Table 18-400 CTRL_CORE_MPU_IRQ_122_123
Address Offset0x0000 0B30
Physical Address0x4A00 2B30InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_123RESERVEDMPU_IRQ_122
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_123RW0x76
15:9RESERVEDR0x0
8:0MPU_IRQ_122RW0x75
Table 18-401 CTRL_CORE_MPU_IRQ_124_125
Address Offset0x0000 0B34
Physical Address0x4A00 2B34InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_125RESERVEDMPU_IRQ_124
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_125RW0x78
15:9RESERVEDR0x0
8:0MPU_IRQ_124RW0x77
Table 18-402 CTRL_CORE_MPU_IRQ_126_127
Address Offset0x0000 0B38
Physical Address0x4A00 2B38InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_127RESERVEDMPU_IRQ_126
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_127RW0x7A
15:9RESERVEDR0x0
8:0MPU_IRQ_126RW0x79
Table 18-403 CTRL_CORE_MPU_IRQ_128_129
Address Offset0x0000 0B3C
Physical Address0x4A00 2B3CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_129RESERVEDMPU_IRQ_128
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_129RW0x7C
15:9RESERVEDR0x0
8:0MPU_IRQ_128RW0x7B
Table 18-404 CTRL_CORE_MPU_IRQ_130_133
Address Offset0x0000 0B40
Physical Address0x4A00 2B40InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_133RESERVEDMPU_IRQ_130
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_133RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_130RW0x7D
Table 18-405 CTRL_CORE_MPU_IRQ_134_135
Address Offset0x0000 0B44
Physical Address0x4A00 2B44InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_135RESERVEDMPU_IRQ_134
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_135RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_134RW0x0
Table 18-406 CTRL_CORE_MPU_IRQ_136_137
Address Offset0x0000 0B48
Physical Address0x4A00 2B48InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_137RESERVEDMPU_IRQ_136
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_137RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_136RW0x0
Table 18-407 CTRL_CORE_MPU_IRQ_138_139
Address Offset0x0000 0B4C
Physical Address0x4A00 2B4CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_139RESERVEDMPU_IRQ_138
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_139RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_138RW0x0
Table 18-408 CTRL_CORE_MPU_IRQ_140_141
Address Offset0x0000 0B50
Physical Address0x4A00 2B50InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_141RESERVEDMPU_IRQ_140
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_141RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_140RW0x0
Table 18-409 CTRL_CORE_MPU_IRQ_142_143
Address Offset0x0000 0B54
Physical Address0x4A00 2B54InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_143RESERVEDMPU_IRQ_142
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_143RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_142RW0x0
Table 18-410 CTRL_CORE_MPU_IRQ_144_145
Address Offset0x0000 0B58
Physical Address0x4A00 2B58InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_145RESERVEDMPU_IRQ_144
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_145RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_144RW0x0
Table 18-411 CTRL_CORE_MPU_IRQ_146_147
Address Offset0x0000 0B5C
Physical Address0x4A00 2B5CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_147RESERVEDMPU_IRQ_146
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_147RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_146RW0x0
Table 18-412 CTRL_CORE_MPU_IRQ_148_149
Address Offset0x0000 0B60
Physical Address0x4A00 2B60InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_149RESERVEDMPU_IRQ_148
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_149RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_148RW0x0
Table 18-413 CTRL_CORE_MPU_IRQ_150_151
Address Offset0x0000 0B64
Physical Address0x4A00 2B64InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_151RESERVEDMPU_IRQ_150
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_151RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_150RW0x0
Table 18-414 CTRL_CORE_MPU_IRQ_152_153
Address Offset0x0000 0B68
Physical Address0x4A00 2B68InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_153RESERVEDMPU_IRQ_152
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_153RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_152RW0x0
Table 18-415 CTRL_CORE_MPU_IRQ_154_155
Address Offset0x0000 0B6C
Physical Address0x4A00 2B6CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_155RESERVEDMPU_IRQ_154
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_155RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_154RW0x0
Table 18-416 CTRL_CORE_MPU_IRQ_156_157
Address Offset0x0000 0B70
Physical Address0x4A00 2B70InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_157RESERVEDMPU_IRQ_156
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_157RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_156RW0x0
Table 18-417 CTRL_CORE_MPU_IRQ_158_159
Address Offset0x0000 0B74
Physical Address0x4A00 2B74InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMPU_IRQ_159RESERVEDMPU_IRQ_158
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16MPU_IRQ_159RW0x0
15:9RESERVEDR0x0
8:0MPU_IRQ_158RW0x0
Table 18-418 CTRL_CORE_DMA_SYSTEM_DREQ_0_1
Address Offset0x0000 0B78
Physical Address0x4A00 2B78InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_1_IRQ_1RESERVEDDMA_SYSTEM_DREQ_0_IRQ_0
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_1_IRQ_1RW0x2
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_0_IRQ_0RW0x1
Table 18-419 CTRL_CORE_DMA_SYSTEM_DREQ_2_3
Address Offset0x0000 0B7C
Physical Address0x4A00 2B7CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_3_IRQ_3RESERVEDDMA_SYSTEM_DREQ_2_IRQ_2
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_3_IRQ_3RW0x4
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_2_IRQ_2RW0x3
Table 18-420 CTRL_CORE_DMA_SYSTEM_DREQ_4_5
Address Offset0x0000 0B80
Physical Address0x4A00 2B80InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_5_IRQ_5RESERVEDDMA_SYSTEM_DREQ_4_IRQ_4
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_5_IRQ_5RW0x6
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_4_IRQ_4RW0x5
Table 18-421 CTRL_CORE_DMA_SYSTEM_DREQ_6_7
Address Offset0x0000 0B84
Physical Address0x4A00 2B84InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_7_IRQ_7RESERVEDDMA_SYSTEM_DREQ_6_IRQ_6
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_7_IRQ_7RW0x8
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_6_IRQ_6RW0x7
Table 18-422 CTRL_CORE_DMA_SYSTEM_DREQ_8_9
Address Offset0x0000 0B88
Physical Address0x4A00 2B88InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_9_IRQ_9RESERVEDDMA_SYSTEM_DREQ_8_IRQ_8
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_9_IRQ_9RW0xA
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_8_IRQ_8RW0x9
Table 18-423 CTRL_CORE_DMA_SYSTEM_DREQ_10_11
Address Offset0x0000 0B8C
Physical Address0x4A00 2B8CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_11_IRQ_11RESERVEDDMA_SYSTEM_DREQ_10_IRQ_10
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_11_IRQ_11RW0xC
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_10_IRQ_10RW0xB
Table 18-424 CTRL_CORE_DMA_SYSTEM_DREQ_12_13
Address Offset0x0000 0B90
Physical Address0x4A00 2B90InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_13_IRQ_13RESERVEDDMA_SYSTEM_DREQ_12_IRQ_12
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_13_IRQ_13RW0xE
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_12_IRQ_12RW0xD
Table 18-425 CTRL_CORE_DMA_SYSTEM_DREQ_14_15
Address Offset0x0000 0B94
Physical Address0x4A00 2B94InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_15_IRQ_15RESERVEDDMA_SYSTEM_DREQ_14_IRQ_14
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_15_IRQ_15RW0x10
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_14_IRQ_14RW0xF
Table 18-426 CTRL_CORE_DMA_SYSTEM_DREQ_16_17
Address Offset0x0000 0B98
Physical Address0x4A00 2B98InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_17_IRQ_17RESERVEDDMA_SYSTEM_DREQ_16_IRQ_16
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_17_IRQ_17RW0x12
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_16_IRQ_16RW0x11
Table 18-427 CTRL_CORE_DMA_SYSTEM_DREQ_18_19
Address Offset0x0000 0B9C
Physical Address0x4A00 2B9CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_19_IRQ_19RESERVEDDMA_SYSTEM_DREQ_18_IRQ_18
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_19_IRQ_19RW0x14
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_18_IRQ_18RW0x13
Table 18-428 CTRL_CORE_DMA_SYSTEM_DREQ_20_21
Address Offset0x0000 0BA0
Physical Address0x4A00 2BA0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_21_IRQ_21RESERVEDDMA_SYSTEM_DREQ_20_IRQ_20
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_21_IRQ_21RW0x16
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_20_IRQ_20RW0x15
Table 18-429 CTRL_CORE_DMA_SYSTEM_DREQ_22_23
Address Offset0x0000 0BA4
Physical Address0x4A00 2BA4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_23_IRQ_23RESERVEDDMA_SYSTEM_DREQ_22_IRQ_22
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_23_IRQ_23RW0x18
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_22_IRQ_22RW0x17
Table 18-430 CTRL_CORE_DMA_SYSTEM_DREQ_24_25
Address Offset0x0000 0BA8
Physical Address0x4A00 2BA8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_25_IRQ_25RESERVEDDMA_SYSTEM_DREQ_24_IRQ_24
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_25_IRQ_25RW0x1A
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_24_IRQ_24RW0x19
Table 18-431 CTRL_CORE_DMA_SYSTEM_DREQ_26_27
Address Offset0x0000 0BAC
Physical Address0x4A00 2BACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_27_IRQ_27RESERVEDDMA_SYSTEM_DREQ_26_IRQ_26
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_27_IRQ_27RW0x1C
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_26_IRQ_26RW0x1B
Table 18-432 CTRL_CORE_DMA_SYSTEM_DREQ_28_29
Address Offset0x0000 0BB0
Physical Address0x4A00 2BB0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_29_IRQ_29RESERVEDDMA_SYSTEM_DREQ_28_IRQ_28
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_29_IRQ_29RW0x1E
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_28_IRQ_28RW0x1D
Table 18-433 CTRL_CORE_DMA_SYSTEM_DREQ_30_31
Address Offset0x0000 0BB4
Physical Address0x4A00 2BB4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_31_IRQ_31RESERVEDDMA_SYSTEM_DREQ_30_IRQ_30
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_31_IRQ_31RW0x20
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_30_IRQ_30RW0x1F
Table 18-434 CTRL_CORE_DMA_SYSTEM_DREQ_32_33
Address Offset0x0000 0BB8
Physical Address0x4A00 2BB8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_33_IRQ_33RESERVEDDMA_SYSTEM_DREQ_32_IRQ_32
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_33_IRQ_33RW0x22
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_32_IRQ_32RW0x21
Table 18-435 CTRL_CORE_DMA_SYSTEM_DREQ_34_35
Address Offset0x0000 0BBC
Physical Address0x4A00 2BBCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_35_IRQ_35RESERVEDDMA_SYSTEM_DREQ_34_IRQ_34
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_35_IRQ_35RW0x24
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_34_IRQ_34RW0x23
Table 18-436 CTRL_CORE_DMA_SYSTEM_DREQ_36_37
Address Offset0x0000 0BC0
Physical Address0x4A00 2BC0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_37_IRQ_37RESERVEDDMA_SYSTEM_DREQ_36_IRQ_36
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_37_IRQ_37RW0x26
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_36_IRQ_36RW0x25
Table 18-437 CTRL_CORE_DMA_SYSTEM_DREQ_38_39
Address Offset0x0000 0BC4
Physical Address0x4A00 2BC4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_39_IRQ_39RESERVEDDMA_SYSTEM_DREQ_38_IRQ_38
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_39_IRQ_39RW0x28
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_38_IRQ_38RW0x27
Table 18-438 CTRL_CORE_DMA_SYSTEM_DREQ_40_41
Address Offset0x0000 0BC8
Physical Address0x4A00 2BC8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_41_IRQ_41RESERVEDDMA_SYSTEM_DREQ_40_IRQ_40
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_41_IRQ_41RW0x2A
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_40_IRQ_40RW0x29
Table 18-439 CTRL_CORE_DMA_SYSTEM_DREQ_42_43
Address Offset0x0000 0BCC
Physical Address0x4A00 2BCCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_43_IRQ_43RESERVEDDMA_SYSTEM_DREQ_42_IRQ_42
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_43_IRQ_43RW0x2C
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_42_IRQ_42RW0x2B
Table 18-440 CTRL_CORE_DMA_SYSTEM_DREQ_44_45
Address Offset0x0000 0BD0
Physical Address0x4A00 2BD0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_45_IRQ_45RESERVEDDMA_SYSTEM_DREQ_44_IRQ_44
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_45_IRQ_45RW0x2E
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_44_IRQ_44RW0x2D
Table 18-441 CTRL_CORE_DMA_SYSTEM_DREQ_46_47
Address Offset0x0000 0BD4
Physical Address0x4A00 2BD4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_47_IRQ_47RESERVEDDMA_SYSTEM_DREQ_46_IRQ_46
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_47_IRQ_47RW0x30
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_46_IRQ_46RW0x2F
Table 18-442 CTRL_CORE_DMA_SYSTEM_DREQ_48_49
Address Offset0x0000 0BD8
Physical Address0x4A00 2BD8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_49_IRQ_49RESERVEDDMA_SYSTEM_DREQ_48_IRQ_48
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_49_IRQ_49RW0x32
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_48_IRQ_48RW0x31
Table 18-443 CTRL_CORE_DMA_SYSTEM_DREQ_50_51
Address Offset0x0000 0BDC
Physical Address0x4A00 2BDCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_51_IRQ_51RESERVEDDMA_SYSTEM_DREQ_50_IRQ_50
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_51_IRQ_51RW0x34
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_50_IRQ_50RW0x33
Table 18-444 CTRL_CORE_DMA_SYSTEM_DREQ_52_53
Address Offset0x0000 0BE0
Physical Address0x4A00 2BE0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_53_IRQ_53RESERVEDDMA_SYSTEM_DREQ_52_IRQ_52
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_53_IRQ_53RW0x36
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_52_IRQ_52RW0x35
Table 18-445 CTRL_CORE_DMA_SYSTEM_DREQ_54_55
Address Offset0x0000 0BE4
Physical Address0x4A00 2BE4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_55_IRQ_55RESERVEDDMA_SYSTEM_DREQ_54_IRQ_54
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_55_IRQ_55RW0x38
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_54_IRQ_54RW0x37
Table 18-446 CTRL_CORE_DMA_SYSTEM_DREQ_56_57
Address Offset0x0000 0BE8
Physical Address0x4A00 2BE8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_57_IRQ_57RESERVEDDMA_SYSTEM_DREQ_56_IRQ_56
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_57_IRQ_57RW0x3A
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_56_IRQ_56RW0x39
Table 18-447 CTRL_CORE_DMA_SYSTEM_DREQ_58_59
Address Offset0x0000 0BEC
Physical Address0x4A00 2BECInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_59_IRQ_59RESERVEDDMA_SYSTEM_DREQ_58_IRQ_58
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_59_IRQ_59RW0x3C
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_58_IRQ_58RW0x3B
Table 18-448 CTRL_CORE_DMA_SYSTEM_DREQ_60_61
Address Offset0x0000 0BF0
Physical Address0x4A00 2BF0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_61_IRQ_61RESERVEDDMA_SYSTEM_DREQ_60_IRQ_60
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_61_IRQ_61RW0x3E
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_60_IRQ_60RW0x3D
Table 18-449 CTRL_CORE_DMA_SYSTEM_DREQ_62_63
Address Offset0x0000 0BF4
Physical Address0x4A00 2BF4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_63_IRQ_63RESERVEDDMA_SYSTEM_DREQ_62_IRQ_62
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_63_IRQ_63RW0x40
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_62_IRQ_62RW0x3F
Table 18-450 CTRL_CORE_DMA_SYSTEM_DREQ_64_65
Address Offset0x0000 0BF8
Physical Address0x4A00 2BF8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_65_IRQ_65RESERVEDDMA_SYSTEM_DREQ_64_IRQ_64
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_65_IRQ_65RW0x42
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_64_IRQ_64RW0x41
Table 18-451 CTRL_CORE_DMA_SYSTEM_DREQ_66_67
Address Offset0x0000 0BFC
Physical Address0x4A00 2BFCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_67_IRQ_67RESERVEDDMA_SYSTEM_DREQ_66_IRQ_66
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_67_IRQ_67RW0x44
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_66_IRQ_66RW0x43
Table 18-452 CTRL_CORE_DMA_SYSTEM_DREQ_68_69
Address Offset0x0000 0C00
Physical Address0x4A00 2C00InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_69_IRQ_69RESERVEDDMA_SYSTEM_DREQ_68_IRQ_68
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_69_IRQ_69RW0x46
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_68_IRQ_68RW0x45
Table 18-453 CTRL_CORE_DMA_SYSTEM_DREQ_70_71
Address Offset0x0000 0C04
Physical Address0x4A00 2C04InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_71_IRQ_71RESERVEDDMA_SYSTEM_DREQ_70_IRQ_70
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_71_IRQ_71RW0x48
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_70_IRQ_70RW0x47
Table 18-454 CTRL_CORE_DMA_SYSTEM_DREQ_72_73
Address Offset0x0000 0C08
Physical Address0x4A00 2C08InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_73_IRQ_73RESERVEDDMA_SYSTEM_DREQ_72_IRQ_72
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_73_IRQ_73RW0x4A
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_72_IRQ_72RW0x49
Table 18-455 CTRL_CORE_DMA_SYSTEM_DREQ_74_75
Address Offset0x0000 0C0C
Physical Address0x4A00 2C0CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_75_IRQ_75RESERVEDDMA_SYSTEM_DREQ_74_IRQ_74
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_75_IRQ_75RW0x4C
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_74_IRQ_74RW0x4B
Table 18-456 CTRL_CORE_DMA_SYSTEM_DREQ_76_77
Address Offset0x0000 0C10
Physical Address0x4A00 2C10InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_77_IRQ_77RESERVEDDMA_SYSTEM_DREQ_76_IRQ_76
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_77_IRQ_77RW0x4E
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_76_IRQ_76RW0x4D
Table 18-457 CTRL_CORE_DMA_SYSTEM_DREQ_78_79
Address Offset0x0000 0C14
Physical Address0x4A00 2C14InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_79_IRQ_79RESERVEDDMA_SYSTEM_DREQ_78_IRQ_78
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_79_IRQ_79RW0x50
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_78_IRQ_78RW0x4F
Table 18-458 CTRL_CORE_DMA_SYSTEM_DREQ_80_81
Address Offset0x0000 0C18
Physical Address0x4A00 2C18InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_81_IRQ_81RESERVEDDMA_SYSTEM_DREQ_80_IRQ_80
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_81_IRQ_81RW0x52
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_80_IRQ_80RW0x51
Table 18-459 CTRL_CORE_DMA_SYSTEM_DREQ_82_83
Address Offset0x0000 0C1C
Physical Address0x4A00 2C1CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_83_IRQ_83RESERVEDDMA_SYSTEM_DREQ_82_IRQ_82
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_83_IRQ_83RW0x54
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_82_IRQ_82RW0x53
Table 18-460 CTRL_CORE_DMA_SYSTEM_DREQ_84_85
Address Offset0x0000 0C20
Physical Address0x4A00 2C20InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_85_IRQ_85RESERVEDDMA_SYSTEM_DREQ_84_IRQ_84
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_85_IRQ_85RW0x56
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_84_IRQ_84RW0x55
Table 18-461 CTRL_CORE_DMA_SYSTEM_DREQ_86_87
Address Offset0x0000 0C24
Physical Address0x4A00 2C24InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_87_IRQ_87RESERVEDDMA_SYSTEM_DREQ_86_IRQ_86
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_87_IRQ_87RW0x58
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_86_IRQ_86RW0x57
Table 18-462 CTRL_CORE_DMA_SYSTEM_DREQ_88_89
Address Offset0x0000 0C28
Physical Address0x4A00 2C28InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_89_IRQ_89RESERVEDDMA_SYSTEM_DREQ_88_IRQ_88
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_89_IRQ_89RW0x5A
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_88_IRQ_88RW0x59
Table 18-463 CTRL_CORE_DMA_SYSTEM_DREQ_90_91
Address Offset0x0000 0C2C
Physical Address0x4A00 2C2CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_91_IRQ_91RESERVEDDMA_SYSTEM_DREQ_90_IRQ_90
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_91_IRQ_91RW0x5C
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_90_IRQ_90RW0x5B
Table 18-464 CTRL_CORE_DMA_SYSTEM_DREQ_92_93
Address Offset0x0000 0C30
Physical Address0x4A00 2C30InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_93_IRQ_93RESERVEDDMA_SYSTEM_DREQ_92_IRQ_92
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_93_IRQ_93RW0x5E
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_92_IRQ_92RW0x5D
Table 18-465 CTRL_CORE_DMA_SYSTEM_DREQ_94_95
Address Offset0x0000 0C34
Physical Address0x4A00 2C34InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_95_IRQ_95RESERVEDDMA_SYSTEM_DREQ_94_IRQ_94
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_95_IRQ_95RW0x60
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_94_IRQ_94RW0x5F
Table 18-466 CTRL_CORE_DMA_SYSTEM_DREQ_96_97
Address Offset0x0000 0C38
Physical Address0x4A00 2C38InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_97_IRQ_97RESERVEDDMA_SYSTEM_DREQ_96_IRQ_96
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_97_IRQ_97RW0x62
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_96_IRQ_96RW0x61
Table 18-467 CTRL_CORE_DMA_SYSTEM_DREQ_98_99
Address Offset0x0000 0C3C
Physical Address0x4A00 2C3CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_99_IRQ_99RESERVEDDMA_SYSTEM_DREQ_98_IRQ_98
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_99_IRQ_99RW0x64
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_98_IRQ_98RW0x63
Table 18-468 CTRL_CORE_DMA_SYSTEM_DREQ_100_101
Address Offset0x0000 0C40
Physical Address0x4A00 2C40InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_101_IRQ_101RESERVEDDMA_SYSTEM_DREQ_100_IRQ_100
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_101_IRQ_101RW0x66
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_100_IRQ_100RW0x65
Table 18-469 CTRL_CORE_DMA_SYSTEM_DREQ_102_103
Address Offset0x0000 0C44
Physical Address0x4A00 2C44InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_103_IRQ_103RESERVEDDMA_SYSTEM_DREQ_102_IRQ_102
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_103_IRQ_103RW0x68
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_102_IRQ_102RW0x67
Table 18-470 CTRL_CORE_DMA_SYSTEM_DREQ_104_105
Address Offset0x0000 0C48
Physical Address0x4A00 2C48InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_105_IRQ_105RESERVEDDMA_SYSTEM_DREQ_104_IRQ_104
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_105_IRQ_105RW0x6A
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_104_IRQ_104RW0x69
Table 18-471 CTRL_CORE_DMA_SYSTEM_DREQ_106_107
Address Offset0x0000 0C4C
Physical Address0x4A00 2C4CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_107_IRQ_107RESERVEDDMA_SYSTEM_DREQ_106_IRQ_106
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_107_IRQ_107RW0x6C
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_106_IRQ_106RW0x6B
Table 18-472 CTRL_CORE_DMA_SYSTEM_DREQ_108_109
Address Offset0x0000 0C50
Physical Address0x4A00 2C50InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_109_IRQ_109RESERVEDDMA_SYSTEM_DREQ_108_IRQ_108
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_109_IRQ_109RW0x6E
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_108_IRQ_108RW0x6D
Table 18-473 CTRL_CORE_DMA_SYSTEM_DREQ_110_111
Address Offset0x0000 0C54
Physical Address0x4A00 2C54InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_111_IRQ_111RESERVEDDMA_SYSTEM_DREQ_110_IRQ_110
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_111_IRQ_111RW0x70
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_110_IRQ_110RW0x6F
Table 18-474 CTRL_CORE_DMA_SYSTEM_DREQ_112_113
Address Offset0x0000 0C58
Physical Address0x4A00 2C58InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_113_IRQ_113RESERVEDDMA_SYSTEM_DREQ_112_IRQ_112
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_113_IRQ_113RW0x72
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_112_IRQ_112RW0x71
Table 18-475 CTRL_CORE_DMA_SYSTEM_DREQ_114_115
Address Offset0x0000 0C5C
Physical Address0x4A00 2C5CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_115_IRQ_115RESERVEDDMA_SYSTEM_DREQ_114_IRQ_114
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_115_IRQ_115RW0x74
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_114_IRQ_114RW0x73
Table 18-476 CTRL_CORE_DMA_SYSTEM_DREQ_116_117
Address Offset0x0000 0C60
Physical Address0x4A00 2C60InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_117_IRQ_117RESERVEDDMA_SYSTEM_DREQ_116_IRQ_116
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_117_IRQ_117RW0x76
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_116_IRQ_116RW0x75
Table 18-477 CTRL_CORE_DMA_SYSTEM_DREQ_118_119
Address Offset0x0000 0C64
Physical Address0x4A00 2C64InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_119_IRQ_119RESERVEDDMA_SYSTEM_DREQ_118_IRQ_118
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_119_IRQ_119RW0x78
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_118_IRQ_118RW0x77
Table 18-478 CTRL_CORE_DMA_SYSTEM_DREQ_120_121
Address Offset0x0000 0C68
Physical Address0x4A00 2C68InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_121_IRQ_121RESERVEDDMA_SYSTEM_DREQ_120_IRQ_120
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_121_IRQ_121RW0x7A
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_120_IRQ_120RW0x79
Table 18-479 CTRL_CORE_DMA_SYSTEM_DREQ_122_123
Address Offset0x0000 0C6C
Physical Address0x4A00 2C6CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_123_IRQ_123RESERVEDDMA_SYSTEM_DREQ_122_IRQ_122
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_123_IRQ_123RW0x7C
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_122_IRQ_122RW0x7B
Table 18-480 CTRL_CORE_DMA_SYSTEM_DREQ_124_125
Address Offset0x0000 0C70
Physical Address0x4A00 2C70InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_125_IRQ_125RESERVEDDMA_SYSTEM_DREQ_124_IRQ_124
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_SYSTEM_DREQ_125_IRQ_125RW0x7E
15:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_124_IRQ_124RW0x7D
Table 18-481 CTRL_CORE_DMA_SYSTEM_DREQ_126_127
Address Offset0x0000 0C74
Physical Address0x4A00 2C74InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_SYSTEM_DREQ_126_IRQ_126
BitsField NameDescriptionTypeReset
31:8RESERVEDR0x0
7:0DMA_SYSTEM_DREQ_126_IRQ_126RW0x7F
Table 18-482 CTRL_CORE_DMA_EDMA_DREQ_0_1
Address Offset0x0000 0C78
Physical Address0x4A00 2C78InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_1_IRQ_1RESERVEDDMA_EDMA_DREQ_0_IRQ_0
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_1_IRQ_1RW0x2
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_0_IRQ_0RW0x1
Table 18-483 CTRL_CORE_DMA_EDMA_DREQ_2_3
Address Offset0x0000 0C7C
Physical Address0x4A00 2C7CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_3_IRQ_3RESERVEDDMA_EDMA_DREQ_2_IRQ_2
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_3_IRQ_3RW0x4
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_2_IRQ_2RW0x3
Table 18-484 CTRL_CORE_DMA_EDMA_DREQ_4_5
Address Offset0x0000 0C80
Physical Address0x4A00 2C80InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_5_IRQ_5RESERVEDDMA_EDMA_DREQ_4_IRQ_4
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_5_IRQ_5RW0x6
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_4_IRQ_4RW0x5
Table 18-485 CTRL_CORE_DMA_EDMA_DREQ_6_7
Address Offset0x0000 0C84
Physical Address0x4A00 2C84InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_7_IRQ_7RESERVEDDMA_EDMA_DREQ_6_IRQ_6
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_7_IRQ_7RW0x8
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_6_IRQ_6RW0x7
Table 18-486 CTRL_CORE_DMA_EDMA_DREQ_8_9
Address Offset0x0000 0C88
Physical Address0x4A00 2C88InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_9_IRQ_9RESERVEDDMA_EDMA_DREQ_8_IRQ_8
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_9_IRQ_9RW0xA
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_8_IRQ_8RW0x9
Table 18-487 CTRL_CORE_DMA_EDMA_DREQ_10_11
Address Offset0x0000 0C8C
Physical Address0x4A00 2C8CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_11_IRQ_11RESERVEDDMA_EDMA_DREQ_10_IRQ_10
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_11_IRQ_11RW0xC
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_10_IRQ_10RW0xB
Table 18-488 CTRL_CORE_DMA_EDMA_DREQ_12_13
Address Offset0x0000 0C90
Physical Address0x4A00 2C90InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_13_IRQ_13RESERVEDDMA_EDMA_DREQ_12_IRQ_12
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_13_IRQ_13RW0xE
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_12_IRQ_12RW0xD
Table 18-489 CTRL_CORE_DMA_EDMA_DREQ_14_15
Address Offset0x0000 0C94
Physical Address0x4A00 2C94InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_15_IRQ_15RESERVEDDMA_EDMA_DREQ_14_IRQ_14
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_15_IRQ_15RW0x10
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_14_IRQ_14RW0xF
Table 18-490 CTRL_CORE_DMA_EDMA_DREQ_16_17
Address Offset0x0000 0C98
Physical Address0x4A00 2C98InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_17_IRQ_17RESERVEDDMA_EDMA_DREQ_16_IRQ_16
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_17_IRQ_17RW0x12
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_16_IRQ_16RW0x11
Table 18-491 CTRL_CORE_DMA_EDMA_DREQ_18_19
Address Offset0x0000 0C9C
Physical Address0x4A00 2C9CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_19_IRQ_19RESERVEDDMA_EDMA_DREQ_18_IRQ_18
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_19_IRQ_19RW0x14
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_18_IRQ_18RW0x13
Table 18-492 CTRL_CORE_DMA_EDMA_DREQ_20_21
Address Offset0x0000 0CA0
Physical Address0x4A00 2CA0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_21_IRQ_21RESERVEDDMA_EDMA_DREQ_20_IRQ_20
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_21_IRQ_21RW0x16
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_20_IRQ_20RW0x15
Table 18-493 CTRL_CORE_DMA_EDMA_DREQ_22_23
Address Offset0x0000 0CA4
Physical Address0x4A00 2CA4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_23_IRQ_23RESERVEDDMA_EDMA_DREQ_22_IRQ_22
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_23_IRQ_23RW0x18
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_22_IRQ_22RW0x17
Table 18-494 CTRL_CORE_DMA_EDMA_DREQ_24_25
Address Offset0x0000 0CA8
Physical Address0x4A00 2CA8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_25_IRQ_25RESERVEDDMA_EDMA_DREQ_24_IRQ_24
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_25_IRQ_25RW0x1A
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_24_IRQ_24RW0x19
Table 18-495 CTRL_CORE_DMA_EDMA_DREQ_26_27
Address Offset0x0000 0CAC
Physical Address0x4A00 2CACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_27_IRQ_27RESERVEDDMA_EDMA_DREQ_26_IRQ_26
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_27_IRQ_27RW0x1C
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_26_IRQ_26RW0x1B
Table 18-496 CTRL_CORE_DMA_EDMA_DREQ_28_29
Address Offset0x0000 0CB0
Physical Address0x4A00 2CB0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_29_IRQ_29RESERVEDDMA_EDMA_DREQ_28_IRQ_28
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_29_IRQ_29RW0x1E
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_28_IRQ_28RW0x1D
Table 18-497 CTRL_CORE_DMA_EDMA_DREQ_30_31
Address Offset0x0000 0CB4
Physical Address0x4A00 2CB4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_31_IRQ_31RESERVEDDMA_EDMA_DREQ_30_IRQ_30
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_31_IRQ_31RW0x20
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_30_IRQ_30RW0x1F
Table 18-498 CTRL_CORE_DMA_EDMA_DREQ_32_33
Address Offset0x0000 0CB8
Physical Address0x4A00 2CB8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_33_IRQ_33RESERVEDDMA_EDMA_DREQ_32_IRQ_32
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_33_IRQ_33RW0x22
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_32_IRQ_32RW0x21
Table 18-499 CTRL_CORE_DMA_EDMA_DREQ_34_35
Address Offset0x0000 0CBC
Physical Address0x4A00 2CBCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_35_IRQ_35RESERVEDDMA_EDMA_DREQ_34_IRQ_34
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_35_IRQ_35RW0x24
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_34_IRQ_34RW0x23
Table 18-500 CTRL_CORE_DMA_EDMA_DREQ_36_37
Address Offset0x0000 0CC0
Physical Address0x4A00 2CC0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_37_IRQ_37RESERVEDDMA_EDMA_DREQ_36_IRQ_36
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_37_IRQ_37RW0x26
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_36_IRQ_36RW0x25
Table 18-501 CTRL_CORE_DMA_EDMA_DREQ_38_39
Address Offset0x0000 0CC4
Physical Address0x4A00 2CC4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_39_IRQ_39RESERVEDDMA_EDMA_DREQ_38_IRQ_38
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_39_IRQ_39RW0x28
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_38_IRQ_38RW0x27
Table 18-502 CTRL_CORE_DMA_EDMA_DREQ_40_41
Address Offset0x0000 0CC8
Physical Address0x4A00 2CC8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_41_IRQ_41RESERVEDDMA_EDMA_DREQ_40_IRQ_40
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_41_IRQ_41RW0x2A
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_40_IRQ_40RW0x29
Table 18-503 CTRL_CORE_DMA_EDMA_DREQ_42_43
Address Offset0x0000 0CCC
Physical Address0x4A00 2CCCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_43_IRQ_43RESERVEDDMA_EDMA_DREQ_42_IRQ_42
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_43_IRQ_43RW0x2C
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_42_IRQ_42RW0x2B
Table 18-504 CTRL_CORE_DMA_EDMA_DREQ_44_45
Address Offset0x0000 0CD0
Physical Address0x4A00 2CD0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_45_IRQ_45RESERVEDDMA_EDMA_DREQ_44_IRQ_44
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_45_IRQ_45RW0x2E
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_44_IRQ_44RW0x2D
Table 18-505 CTRL_CORE_DMA_EDMA_DREQ_46_47
Address Offset0x0000 0CD4
Physical Address0x4A00 2CD4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_47_IRQ_47RESERVEDDMA_EDMA_DREQ_46_IRQ_46
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_47_IRQ_47RW0x30
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_46_IRQ_46RW0x2F
Table 18-506 CTRL_CORE_DMA_EDMA_DREQ_48_49
Address Offset0x0000 0CD8
Physical Address0x4A00 2CD8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_49_IRQ_49RESERVEDDMA_EDMA_DREQ_48_IRQ_48
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_49_IRQ_49RW0x32
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_48_IRQ_48RW0x31
Table 18-507 CTRL_CORE_DMA_EDMA_DREQ_50_51
Address Offset0x0000 0CDC
Physical Address0x4A00 2CDCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_51_IRQ_51RESERVEDDMA_EDMA_DREQ_50_IRQ_50
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_51_IRQ_51RW0x34
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_50_IRQ_50RW0x33
Table 18-508 CTRL_CORE_DMA_EDMA_DREQ_52_53
Address Offset0x0000 0CE0
Physical Address0x4A00 2CE0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_53_IRQ_53RESERVEDDMA_EDMA_DREQ_52_IRQ_52
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_53_IRQ_53RW0x36
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_52_IRQ_52RW0x35
Table 18-509 CTRL_CORE_DMA_EDMA_DREQ_54_55
Address Offset0x0000 0CE4
Physical Address0x4A00 2CE4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_55_IRQ_55RESERVEDDMA_EDMA_DREQ_54_IRQ_54
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_55_IRQ_55RW0x38
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_54_IRQ_54RW0x37
Table 18-510 CTRL_CORE_DMA_EDMA_DREQ_56_57
Address Offset0x0000 0CE8
Physical Address0x4A00 2CE8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_57_IRQ_57RESERVEDDMA_EDMA_DREQ_56_IRQ_56
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_57_IRQ_57RW0x3A
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_56_IRQ_56RW0x39
Table 18-511 CTRL_CORE_DMA_EDMA_DREQ_58_59
Address Offset0x0000 0CEC
Physical Address0x4A00 2CECInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_59_IRQ_59RESERVEDDMA_EDMA_DREQ_58_IRQ_58
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_59_IRQ_59RW0x3C
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_58_IRQ_58RW0x3B
Table 18-512 CTRL_CORE_DMA_EDMA_DREQ_60_61
Address Offset0x0000 0CF0
Physical Address0x4A00 2CF0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_61_IRQ_61RESERVEDDMA_EDMA_DREQ_60_IRQ_60
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_61_IRQ_61RW0x3E
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_60_IRQ_60RW0x3D
Table 18-513 CTRL_CORE_DMA_EDMA_DREQ_62_63
Address Offset0x0000 0CF4
Physical Address0x4A00 2CF4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_EDMA_DREQ_63_IRQ_63RESERVEDDMA_EDMA_DREQ_62_IRQ_62
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_EDMA_DREQ_63_IRQ_63RW0x40
15:8RESERVEDR0x0
7:0DMA_EDMA_DREQ_62_IRQ_62RW0x3F
Table 18-514 CTRL_CORE_DMA_DSP1_DREQ_0_1
Address Offset0x0000 0CF8
Physical Address0x4A00 2CF8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_1_IRQ_1RESERVEDDMA_DSP1_DREQ_0_IRQ_0
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_1_IRQ_1RW0x81
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_0_IRQ_0RW0x80
Table 18-515 CTRL_CORE_DMA_DSP1_DREQ_2_3
Address Offset0x0000 0CFC
Physical Address0x4A00 2CFCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_3_IRQ_3RESERVEDDMA_DSP1_DREQ_2_IRQ_2
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_3_IRQ_3RW0x83
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_2_IRQ_2RW0x82
Table 18-516 CTRL_CORE_DMA_DSP1_DREQ_4_5
Address Offset0x0000 0D00
Physical Address0x4A00 2D00InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_5_IRQ_5RESERVEDDMA_DSP1_DREQ_4_IRQ_4
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_5_IRQ_5RW0x85
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_4_IRQ_4RW0x84
Table 18-517 CTRL_CORE_DMA_DSP1_DREQ_6_7
Address Offset0x0000 0D04
Physical Address0x4A00 2D04InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_7_IRQ_7RESERVEDDMA_DSP1_DREQ_6_IRQ_6
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_7_IRQ_7RW0x87
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_6_IRQ_6RW0x86
Table 18-518 CTRL_CORE_DMA_DSP1_DREQ_8_9
Address Offset0x0000 0D08
Physical Address0x4A00 2D08InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_9_IRQ_9RESERVEDDMA_DSP1_DREQ_8_IRQ_8
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_9_IRQ_9RW0x89
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_8_IRQ_8RW0x88
Table 18-519 CTRL_CORE_DMA_DSP1_DREQ_10_11
Address Offset0x0000 0D0C
Physical Address0x4A00 2D0CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_11_IRQ_11RESERVEDDMA_DSP1_DREQ_10_IRQ_10
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_11_IRQ_11RW0x8B
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_10_IRQ_10RW0x8A
Table 18-520 CTRL_CORE_DMA_DSP1_DREQ_12_13
Address Offset0x0000 0D10
Physical Address0x4A00 2D10InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_13_IRQ_13RESERVEDDMA_DSP1_DREQ_12_IRQ_12
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_13_IRQ_13RW0x8D
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_12_IRQ_12RW0x8C
Table 18-521 CTRL_CORE_DMA_DSP1_DREQ_14_15
Address Offset0x0000 0D14
Physical Address0x4A00 2D14InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_15_IRQ_15RESERVEDDMA_DSP1_DREQ_14_IRQ_14
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_15_IRQ_15RW0x8F
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_14_IRQ_14RW0x8E
Table 18-522 CTRL_CORE_DMA_DSP1_DREQ_16_17
Address Offset0x0000 0D18
Physical Address0x4A00 2D18InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_17_IRQ_17RESERVEDDMA_DSP1_DREQ_16_IRQ_16
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_17_IRQ_17RW0x9B
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_16_IRQ_16RW0x9A
Table 18-523 CTRL_CORE_DMA_DSP1_DREQ_18_19
Address Offset0x0000 0D1C
Physical Address0x4A00 2D1CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP1_DREQ_19_IRQ_19RESERVEDDMA_DSP1_DREQ_18_IRQ_18
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP1_DREQ_19_IRQ_19RW0x9D
15:8RESERVEDR0x0
7:0DMA_DSP1_DREQ_18_IRQ_18RW0x9C
Table 18-524 CTRL_CORE_DMA_DSP2_DREQ_0_1
Address Offset0x0000 0D20
Physical Address0x4A00 2D20InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_1_IRQ_1RESERVEDDMA_DSP2_DREQ_0_IRQ_0
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_1_IRQ_1RW0x81
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_0_IRQ_0RW0x80
Table 18-525 CTRL_CORE_DMA_DSP2_DREQ_2_3
Address Offset0x0000 0D24
Physical Address0x4A00 2D24InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_3_IRQ_3RESERVEDDMA_DSP2_DREQ_2_IRQ_2
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_3_IRQ_3RW0x83
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_2_IRQ_2RW0x82
Table 18-526 CTRL_CORE_DMA_DSP2_DREQ_4_5
Address Offset0x0000 0D28
Physical Address0x4A00 2D28InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_5_IRQ_5RESERVEDDMA_DSP2_DREQ_4_IRQ_4
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_5_IRQ_5RW0x85
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_4_IRQ_4RW0x84
Table 18-527 CTRL_CORE_DMA_DSP2_DREQ_6_7
Address Offset0x0000 0D2C
Physical Address0x4A00 2D2CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_7_IRQ_7RESERVEDDMA_DSP2_DREQ_6_IRQ_6
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_7_IRQ_7RW0x87
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_6_IRQ_6RW0x86
Table 18-528 CTRL_CORE_DMA_DSP2_DREQ_8_9
Address Offset0x0000 0D30
Physical Address0x4A00 2D30InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_9_IRQ_9RESERVEDDMA_DSP2_DREQ_8_IRQ_8
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_9_IRQ_9RW0x89
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_8_IRQ_8RW0x88
Table 18-529 CTRL_CORE_DMA_DSP2_DREQ_10_11
Address Offset0x0000 0D34
Physical Address0x4A00 2D34InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_11_IRQ_11RESERVEDDMA_DSP2_DREQ_10_IRQ_10
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_11_IRQ_11RW0x8B
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_10_IRQ_10RW0x8A
Table 18-530 CTRL_CORE_DMA_DSP2_DREQ_12_13
Address Offset0x0000 0D38
Physical Address0x4A00 2D38InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_13_IRQ_13RESERVEDDMA_DSP2_DREQ_12_IRQ_12
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_13_IRQ_13RW0x8D
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_12_IRQ_12RW0x8C
Table 18-531 CTRL_CORE_DMA_DSP2_DREQ_14_15
Address Offset0x0000 0D3C
Physical Address0x4A00 2D3CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_15_IRQ_15RESERVEDDMA_DSP2_DREQ_14_IRQ_14
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_15_IRQ_15RW0x8F
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_14_IRQ_14RW0x8E
Table 18-532 CTRL_CORE_DMA_DSP2_DREQ_16_17
Address Offset0x0000 0D40
Physical Address0x4A00 2D40InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_17_IRQ_17RESERVEDDMA_DSP2_DREQ_16_IRQ_16
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_17_IRQ_17RW0x9B
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_16_IRQ_16RW0x9A
Table 18-533 CTRL_CORE_DMA_DSP2_DREQ_18_19
Address Offset0x0000 0D44
Physical Address0x4A00 2D44InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDMA_DSP2_DREQ_19_IRQ_19RESERVEDDMA_DSP2_DREQ_18_IRQ_18
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:16DMA_DSP2_DREQ_19_IRQ_19RW0x9D
15:8RESERVEDR0x0
7:0DMA_DSP2_DREQ_18_IRQ_18RW0x9C
Table 18-534 CTRL_CORE_OVS_DMARQ_IO_MUX
Address Offset0x0000 0D4C
Physical Address0x4A00 2D4CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDOVS_DMARQ_IO_MUX_2OVS_DMARQ_IO_MUX_1
BitsField NameDescriptionTypeReset
31:16RESERVEDR0x0
15:8OVS_DMARQ_IO_MUX_2RW0x0
7:0OVS_DMARQ_IO_MUX_1RW0x0
Table 18-535 CTRL_CORE_OVS_IRQ_IO_MUX
Address Offset0x0000 0D50
Physical Address0x4A00 2D50InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDOVS_IRQ_IO_MUX_2OVS_IRQ_IO_MUX_1
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17:9OVS_IRQ_IO_MUX_2RW0x0
8:0OVS_IRQ_IO_MUX_1RW0x0
Table 18-536 CTRL_CORE_CONTROL_PBIAS
Address Offset0x0000 0E00
Physical Address0x4A00 2E00InstanceCTRL_MODULE_CORE
DescriptionPBIASLITE control
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSDCARD_BIAS_PWRDNZSDCARD_IO_PWRDNZSDCARD_BIAS_HIZ_MODESDCARD_BIAS_SUPPLY_HI_OUTSDCARD_BIAS_VMODE_ERRORRESERVEDSDCARD_BIAS_VMODERESERVED
BitsField NameDescriptionTypeReset
31:28RESERVEDR0x0
27SDCARD_BIAS_PWRDNZ

PWRDNZ control to SDCARD BIAS

0x0 = This signal is used to protect SDCARD BIAS when VDDS is not stable

0x1 = SW keep this bit to 1'b1 after VDDS stabilizing

RW0x0
26SDCARD_IO_PWRDNZ

PWRDNZ control to SDCARD IO

0x0 = This signal is used to protect SDCARD IOs when VDDS is not stable

0x1 = SW keep this bit to 1'b1 after VDDS stabilizing

RW0x0
25SDCARD_BIAS_HIZ_MODE

HIZ_MODE from SDCARD PBIAS

0x0 = PBIAS in normal operation mode

0x1 = PBIAS output is in high impedance state

RW0x0
24SDCARD_BIAS_SUPPLY_HI_OUT

SUPPLY_HI_OUT from SDCARD PBIAS

0x0 = VDDS = 1.8V

0x1 = VDDS = 3.3V

R0x0
23SDCARD_BIAS_VMODE_ERROR

VMODE ERROR from SDCARD PBIAS

0x0 = VMODE level is same as SUPPLY_HI_OUT

0x1 = VMODE level is not same as SUPPLY_HI_OUT

R0x0
22RESERVEDR0x0
21SDCARD_BIAS_VMODE

VMODE control to SDCARD PBIAS

0x0 = VDDS = 1.8V

0x1 = VDDS = 3.3V

RW0x1
20:0RESERVEDR0x0
Table 18-537 CTRL_CORE_CONTROL_HDMI_TX_PHY
Address Offset0x0000 0E0C
Physical Address0x4A00 2E0CInstanceCTRL_MODULE_CORE
DescriptionHDMI TX PHY control
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDHDMITXPHY_TXVALIDHDMITXPHY_ENBYPASSCLKHDMITXPHY_PD_PULLUPDETRESERVED
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30HDMITXPHY_TXVALID

0x1= Valid data on the HDMI_TXPHY input data interface , sampled on the rising edge of TMDSCLK

RW0x0
29HDMITXPHY_ENBYPASSCLK

0x1 = Enables the HFBYPASSCLK to be used in place of the HFBITCLK

RW0x0
28HDMITXPHY_PD_PULLUPDET

0x0 = Set this bit to 0x0 if RX connection is required to be detected, even when HDMI_TXPHY is powered down

0x1 = Disables the low power RX detection functionality

RW0x1
27:0RESERVEDR0x0
Table 18-538 CTRL_CORE_CONTROL_USB2PHYCORE
Address Offset0x0000 0E1C
Physical Address0x4A00 2E1CInstanceCTRL_MODULE_CORE
DescriptionThis register is related to the USB2_PHY1.
TypeRW
313029282726252423222120191817161514131211109876543210
USB2PHY_AUTORESUME_ENUSB2PHY_DISCHGDETUSB2PHY_GPIOMODEUSB2PHY_CHG_DET_EXT_CTLUSB2PHY_RDM_PD_CHGDET_ENUSB2PHY_RDP_PU_CHGDET_ENUSB2PHY_CHG_VSRC_ENUSB2PHY_CHG_ISINK_ENUSB2PHY_CHG_DET_STATUSUSB2PHY_CHG_DET_DM_COMPUSB2PHY_CHG_DET_DP_COMPUSB2PHY_DATADETUSB2PHY_SINKONDPUSB2PHY_SRCONDMUSB2PHY_RESTARTCHGDETUSB2PHY_CHGDETDONEUSB2PHY_CHGDETECTEDUSB2PHY_MCPCPUENUSB2PHY_MCPCMODEENUSB2PHY_RESETDONEMCLKUSB2PHY_UTMIRESETDONERESERVEDUSB2PHY_DATAPOLARITYNUSBDPLL_FREQLOCKUSB2PHY_RESETDONETCLKRESERVED
BitsField NameDescriptionTypeReset
31USB2PHY_AUTORESUME_EN

Auto resume enable

0x0 = disable autoresume

0x1 = enable autoresume

RW0x0
30USB2PHY_DISCHGDET

Disable charger detect

0x0 = charger detect function enabled

0x1 = charger detect function disabled

RW0x1
29USB2PHY_GPIOMODE

GPIO mode

0x0 = USB mode enabled

0x1 = GPIO mode enabled

RW0x0
28USB2PHY_CHG_DET_EXT_CTL

Charge detect external control

0x0 = charger detect internal state machine used

0x1 = charge detect statemachine is bypassed

RW0x0
27USB2PHY_RDM_PD_CHGDET_EN

DM Pull down control

0x0 = PD disabled

0x1 = PD enabled

RW0x0
26USB2PHY_RDP_PU_CHGDET_EN

DP Pull up control

0x0 = PU disabled

0x1 = PU enabled

RW0x0
25USB2PHY_CHG_VSRC_EN

VSRC enable on DP line:Host charger case

0x0 = disable VSRC drive on DP

0x1 = drives VSRC 600mV on DP line

RW0x0
24USB2PHY_CHG_ISINK_EN

ISINK enable on DM line:Host charger case

0x0 = disable the isink on DM

0x1 = enables the ISINK (100uA) on DM line

RW0x0
23:21USB2PHY_CHG_DET_STATUS

Status of charger detection

0x0 = Wait state

0x1 = No contact

0x2 = PS/2

0x3 = Unknown error

0x4 = Dedicated charger

0x5 = HOST charger

0x6 = PC

0x7 = Interrupt

R0x0
20USB2PHY_CHG_DET_DM_COMP

Output of the comparator on DM during the resistor host detect protocol

0x0 = DM line is below 0.75V to 0.95V

0x1 = DM line is above 0.75V to 0.95V

R0x0
19USB2PHY_CHG_DET_DP_COMP

Output of the comparator on DP during the resistor host detect protocol

0x0 = DP line is below 0.75V to 0.95V

0x1 = DP line is above 0.75V to 0.95V

R0x0
18USB2PHY_DATADET

Output of the charger detect comparator

0x0 = DM line is below 0.25V to 0.4V

0x1 = DM line is above 0.25V to 0.4V

R0x0
17USB2PHY_SINKONDP

When '1' current sink is connected to DP instead of DM

0x0 = Default value

0x1 = enables the ISINK on DP instead of DM

RW0x0
16USB2PHY_SRCONDM

When '1' voltage source is connected to DP instead of DM

0x0 = Default value

0x1 = enable the VSRC on DM instead of DP

RW0x0
15USB2PHY_RESTARTCHGDET

restartchgdet = '1' for 1 msec cause the CD_START to reset

0x0 = Default value

0x1 = a high pulse of 1 msec causes the charger detect to restart on negative edge of restartchgdet

RW0x0
14USB2PHY_CHGDETDONE

Status indicates that charger detection protocol is over

0x0 = charger detection protocol is not over

0x1 = charger detection protocol is over

R0x0
13USB2PHY_CHGDETECTED

Output of the charger detection protocol

0x0 = charger not detected

0x1 = charger detected

R0x0
12USB2PHY_MCPCPUEN

MCPC Pull up enable

0x0 = disable the MCPC pull up

0x1 = enable the 4.7K to10K pull up on receive line DP when datapolarityn is 0 and DM when datapolarityn is 1

RW0x0
11USB2PHY_MCPCMODEEN

MCPC Mode enable

0x0 = disable MCPC mode

0x1 = enable MCPC mode

RW0x0
10USB2PHY_RESETDONEMCLK

OCP reset status

0x0 = OCP domain is in reset

0x1 = OCP domain is out of reset

R0x0
9USB2PHY_UTMIRESETDONE

UTMI FSM reset status

0x0 = UTMI FSMs are in reset

0x1 = UTMI FSMs are out of reset

R0x0
8RESERVEDR0x0
7USB2PHY_DATAPOLARITYN

Data polarity

0x0 = DP functionality is on DP and DM funcationality is on DM

0x1 = DP functionality is on DM and DM functionality is on DP

RW0x0
6USBDPLL_FREQLOCK

Status from USB DPLL

R0x0
5USB2PHY_RESETDONETCLK

resetdonetclk status from USB2PHY

R0x0
4:0RESERVEDR0x0
Table 18-539 CTRL_CORE_CONTROL_HDMI_1
Address Offset0x0000 0E20
Physical Address0x4A00 2E20InstanceCTRL_MODULE_CORE
DescriptionHDMI pads control 1
TypeRW
313029282726252423222120191817161514131211109876543210
HDMI_DDC_SDA_GLFENBHDMI_DDC_SDA_PULLUPRESXHDMI_DDC_SCL_GLFENBHDMI_DDC_SCL_PULLUPRESXHDMI_DDC_SDA_HSMODEHDMI_DDC_SCL_HSMODERESERVED
BitsField NameDescriptionTypeReset
31HDMI_DDC_SDA_GLFENBActive_high glitch free operation enable pin for hdmi_ddc_sda receiverRW0x0
0x0: Disabled
0x1: Enabled
30HDMI_DDC_SDA_PULLUPRESXActive_low internal pull_up resistor enabled for hdmi_ddc_sdaRW0x0
0x0: Enabled
0x1: Disabled
29HDMI_DDC_SCL_GLFENBActive_high glitch free operation enable pin for hdmi_ddc_scl receiverRW0x0
0x0: Disabled
0x1: Enabled
28HDMI_DDC_SCL_PULLUPRESXActive_low internal pull_up resistor enabled for hdmi_ddc_sclRW0x0
0x0: Enabled
0x1: Disabled
27HDMI_DDC_SDA_HSMODEActive-high selection for I2C High-Speed modeRW0x0
0x0: Disabled
0x1: Enabled
26HDMI_DDC_SCL_HSMODEActive-high selection for I2C High-Speed modeRW0x0
0x0: Disabled
0x1: Enabled
25:0RESERVEDR0x0
Table 18-540 CTRL_CORE_CONTROL_DDRCACH1_0
Address Offset0x0000 0E30
Physical Address0x4A00 2E30InstanceCTRL_MODULE_CORE
DescriptionddrcaCH1 control
TypeRW
313029282726252423222120191817161514131211109876543210
DDRCH1_PART0_IDDRCH1_PART0_SRDDRCH1_PART0_WDDDRCH1_PART5A_IDDRCH1_PART5A_SRDDRCH1_PART5A_WDDDRCH1_PART5B_IDDRCH1_PART5B_SRDDRCH1_PART5B_WDDDRCH1_PART6_IDDRCH1_PART6_SRDDRCH1_PART6_WD
BitsField NameDescriptionTypeReset
31:29DDRCH1_PART0_I

PART0 Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
28:26DDRCH1_PART0_SR

PART0 Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
25:24DDRCH1_PART0_WD

PART0 Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
23:21DDRCH1_PART5A_I

PART5A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
20:18DDRCH1_PART5A_SR

PART5A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
17:16DDRCH1_PART5A_WD

PART5A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
15:13DDRCH1_PART5B_I

PART5B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
12:10DDRCH1_PART5B_SR

PART5B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
9:8DDRCH1_PART5B_WD

PART5B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
7:5DDRCH1_PART6_I

PART6 Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
4:2DDRCH1_PART6_SR

PART6 Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
1:0DDRCH1_PART6_WD

PART6 Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
Table 18-541 CTRL_CORE_CONTROL_DDRCACH2_0
Address Offset0x0000 0E34
Physical Address0x4A00 2E34InstanceCTRL_MODULE_CORE
DescriptionddrcaCH2 control
TypeRW
313029282726252423222120191817161514131211109876543210
DDRCH2_PART0_IDDRCH2_PART0_SRDDRCH2_PART0_WDDDRCH2_PART5A_IDDRCH2_PART5A_SRDDRCH2_PART5A_WDDDRCH2_PART5B_IDDRCH2_PART5B_SRDDRCH2_PART5B_WDDDRCH2_PART6_IDDRCH2_PART6_SRDDRCH2_PART6_WD
BitsField NameDescriptionTypeReset
31:29DDRCH2_PART0_I

PART0 Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
28:26DDRCH2_PART0_SR

PART0 Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
25:24DDRCH2_PART0_WD

PART0 Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
23:21DDRCH2_PART5A_I

PART5A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
20:18DDRCH2_PART5A_SR

PART5A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
17:16DDRCH2_PART5A_WD

PART5A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
15:13DDRCH2_PART5B_I

PART5B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
12:10DDRCH2_PART5B_SR

PART5B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
9:8DDRCH2_PART5B_WD

PART5B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
7:5DDRCH2_PART6_I

PART6 Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
4:2DDRCH2_PART6_SR

PART6 Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
1:0DDRCH2_PART6_WD

PART6 Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
Table 18-542 CTRL_CORE_CONTROL_DDRCH1_0
Address Offset0x0000 0E38
Physical Address0x4A00 2E38InstanceCTRL_MODULE_CORE
DescriptionDDRCH1 control 0
TypeRW
313029282726252423222120191817161514131211109876543210
DDRCH1_PART1A_IDDRCH1_PART1A_SRDDRCH1_PART1A_WDDDRCH1_PART1B_IDDRCH1_PART1B_SRDDRCH1_PART1B_WDDDRCH1_PART2A_IDDRCH1_PART2A_SRDDRCH1_PART2A_WDDDRCH1_PART2B_IDDRCH1_PART2B_SRDDRCH1_PART2B_WD
BitsField NameDescriptionTypeReset
31:29DDRCH1_PART1A_I

PART1A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
28:26DDRCH1_PART1A_SR

PART1A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
25:24DDRCH1_PART1A_WD

PART1A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
23:21DDRCH1_PART1B_I

PART1B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
20:18DDRCH1_PART1B_SR

PART1B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
17:16DDRCH1_PART1B_WD

PART1B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
15:13DDRCH1_PART2A_I

PART2A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
12:10DDRCH1_PART2A_SR

PART2A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
9:8DDRCH1_PART2A_WD

PART2A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
7:5DDRCH1_PART2B_I

PART2B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
4:2DDRCH1_PART2B_SR

PART2B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
1:0DDRCH1_PART2B_WD

PART2B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
Table 18-543 CTRL_CORE_CONTROL_DDRCH1_1
Address Offset0x0000 0E3C
Physical Address0x4A00 2E3CInstanceCTRL_MODULE_CORE
DescriptionDDRCH1 control 1
TypeRW
313029282726252423222120191817161514131211109876543210
DDRCH1_PART3A_IDDRCH1_PART3A_SRDDRCH1_PART3A_WDDDRCH1_PART3B_IDDRCH1_PART3B_SRDDRCH1_PART3B_WDDDRCH1_PART4A_IDDRCH1_PART4A_SRDDRCH1_PART4A_WDDDRCH1_PART4B_IDDRCH1_PART4B_SRDDRCH1_PART4B_WD
BitsField NameDescriptionTypeReset
31:29DDRCH1_PART3A_I

PART3A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
28:26DDRCH1_PART3A_SR

PART3A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
25:24DDRCH1_PART3A_WD

PART3A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
23:21DDRCH1_PART3B_I

PART3B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
20:18DDRCH1_PART3B_SR

PART3B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
17:16DDRCH1_PART3B_WD

PART3B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
15:13DDRCH1_PART4A_I

PART4A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
12:10DDRCH1_PART4A_SR

PART4A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
9:8DDRCH1_PART4A_WD

PART4A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
7:5DDRCH1_PART4B_I

PART4B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
4:2DDRCH1_PART4B_SR

PART4B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
1:0DDRCH1_PART4B_WD

PART4B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
Table 18-544 CTRL_CORE_CONTROL_DDRCH2_0
Address Offset0x0000 0E40
Physical Address0x4A00 2E40InstanceCTRL_MODULE_CORE
DescriptionDDRCH2 control 0
TypeRW
313029282726252423222120191817161514131211109876543210
DDRCH2_PART1A_IDDRCH2_PART1A_SRDDRCH2_PART1A_WDDDRCH2_PART1B_IDDRCH2_PART1B_SRDDRCH2_PART1B_WDDDRCH2_PART2A_IDDRCH2_PART2A_SRDDRCH2_PART2A_WDDDRCH2_PART2B_IDDRCH2_PART2B_SRDDRCH2_PART2B_WD
BitsField NameDescriptionTypeReset
31:29DDRCH2_PART1A_I

PART1A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
28:26DDRCH2_PART1A_SR

PART1A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
25:24DDRCH2_PART1A_WD

PART1A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
23:21DDRCH2_PART1B_I

PART1B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
20:18DDRCH2_PART1B_SR

PART1B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
17:16DDRCH2_PART1B_WD

PART1B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
15:13DDRCH2_PART2A_I

PART2A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
12:10DDRCH2_PART2A_SR

PART2A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
9:8DDRCH2_PART2A_WD

PART2A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
7:5DDRCH2_PART2B_I

PART2B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
4:2DDRCH2_PART2B_SR

PART2B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
1:0DDRCH2_PART2B_WD

PART2B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
Table 18-545 CTRL_CORE_CONTROL_DDRCH2_1
Address Offset0x0000 0E44
Physical Address0x4A00 2E44InstanceCTRL_MODULE_CORE
DescriptionDDRCH2 control 1
TypeRW
313029282726252423222120191817161514131211109876543210
DDRCH2_PART3A_IDDRCH2_PART3A_SRDDRCH2_PART3A_WDDDRCH2_PART3B_IDDRCH2_PART3B_SRDDRCH2_PART3B_WDDDRCH2_PART4A_IDDRCH2_PART4A_SRDDRCH2_PART4A_WDDDRCH2_PART4B_IDDRCH2_PART4B_SRDDRCH2_PART4B_WD
BitsField NameDescriptionTypeReset
31:29DDRCH2_PART3A_I

PART3A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
28:26DDRCH2_PART3A_SR

PART3A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
25:24DDRCH2_PART3A_WD

PART3A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
23:21DDRCH2_PART3B_I

PART3B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
20:18DDRCH2_PART3B_SR

PART3B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
17:16DDRCH2_PART3B_WD

PART3B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
15:13DDRCH2_PART4A_I

PART4A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
12:10DDRCH2_PART4A_SR

PART4A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
9:8DDRCH2_PART4A_WD

PART4A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
7:5DDRCH2_PART4B_I

PART4B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
4:2DDRCH2_PART4B_SR

PART4B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
1:0DDRCH2_PART4B_WD

PART4B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
Table 18-546 CTRL_CORE_CONTROL_DDRCH1_2
Address Offset0x0000 0E48
Physical Address0x4A00 2E48InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDDRCH1_PART7A_IDDRCH1_PART7A_SRDDRCH1_PART7A_WDDDRCH1_PART7B_IDDRCH1_PART7B_SRDDRCH1_PART7B_WDRESERVED
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x0
23:21DDRCH1_PART7A_I

PART7A Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
20:18DDRCH1_PART7A_SR

PART7A Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
17:16DDRCH1_PART7A_WD

PART7A Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
15:13DDRCH1_PART7B_I

PART7B Impedence control I[2:0]

0x0: Imp80

0x1: Imp60

0x2: Imp48

0x3: Imp40

0x4: Imp34

0x5: Reserved

0x6: Reserved

0x7: Reserved

RW0x2
12:10DDRCH1_PART7B_SR

PART7B Slew Rate control SR[2:0]. All 8 values are valid.

0x0: Fastest

....

0x7: Slowest

RW0x2
9:8DDRCH1_PART7B_WD

PART7B Weak driver control WD[1:0]

-For single-ended operation:

0x0: Pull logic is disabled

0x1: Pull-up selected

0x2: Pull-down selected

0x3: Maintain the previous output value

-For differential pair operation:

0x0: Pull logic is disabled

0x1: Pull-up selected for padp, pull-down selected for padn

0x2: Pull-down selected for padp, pull-up selected for padn

0x3: Maintain the previous output value

RW0x2
7:0RESERVEDR0x0
Table 18-547 CTRL_CORE_CONTROL_DDRIO_0
Address Offset0x0000 0E50
Physical Address0x4A00 2E50InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDDRCH1_VREF_DQ0_INT_CCAP0DDRCH1_VREF_DQ0_INT_CCAP1DDRCH1_VREF_DQ0_INT_TAP0DDRCH1_VREF_DQ0_INT_TAP1DDRCH1_VREF_DQ0_INT_ENDDRCH1_VREF_DQ1_INT_CCAP0DDRCH1_VREF_DQ1_INT_CCAP1DDRCH1_VREF_DQ1_INT_TAP0DDRCH1_VREF_DQ1_INT_TAP1DDRCH1_VREF_DQ1_INT_ENRESERVED
BitsField NameDescriptionTypeReset
31:20RESERVEDR0x0
19DDRCH1_VREF_DQ0_INT_CCAP0Selection for coupling cap connectionRW0x1
0x0: Disabled
0x1: Enabled
18DDRCH1_VREF_DQ0_INT_CCAP1Selection for coupling cap connectionRW0x0
0x0: Disabled
0x1: Enabled
17DDRCH1_VREF_DQ0_INT_TAP0Selection for internal reference voltage driveRW0x0
0x0: Disabled
0x1: Enabled
16DDRCH1_VREF_DQ0_INT_TAP1Selection for internal reference voltage driveRW0x1
0x0: Disabled
0x1: Enabled
15DDRCH1_VREF_DQ0_INT_ENEnableRW0x1
0x0: Disabled
0x1: Enabled
14DDRCH1_VREF_DQ1_INT_CCAP0Selection for coupling cap connectionRW0x1
0x0: Disabled
0x1: Enabled
13DDRCH1_VREF_DQ1_INT_CCAP1Selection for coupling cap connectionRW0x0
0x0: Disabled
0x1: Enabled
12DDRCH1_VREF_DQ1_INT_TAP0Selection for internal reference voltage driveRW0x0
0x0: Disabled
0x1: Enabled
11DDRCH1_VREF_DQ1_INT_TAP1Selection for internal reference voltage driveRW0x1
0x0: Disabled
0x1: Enabled
10DDRCH1_VREF_DQ1_INT_ENEnableRW0x1
0x0: Disabled
0x1: Enabled
9:0RESERVEDR0x260
Table 18-548 CTRL_CORE_CONTROL_DDRIO_1
Address Offset0x0000 0E54
Physical Address0x4A00 2E54InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDDRCH2_VREF_DQ0_INT_CCAP0DDRCH2_VREF_DQ0_INT_CCAP1DDRCH2_VREF_DQ0_INT_TAP0DDRCH2_VREF_DQ0_INT_TAP1DDRCH2_VREF_DQ0_INT_ENDDRCH2_VREF_DQ1_INT_CCAP0DDRCH2_VREF_DQ1_INT_CCAP1DDRCH2_VREF_DQ1_INT_TAP0DDRCH2_VREF_DQ1_INT_TAP1DDRCH2_VREF_DQ1_INT_ENRESERVED
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26DDRCH2_VREF_DQ0_INT_CCAP0Selection for coupling cap connectionRW0x1
0x0: Disabled
0x1: Enabled
25DDRCH2_VREF_DQ0_INT_CCAP1Selection for coupling cap connectionRW0x0
0x0: Disabled
0x1: Enabled
24DDRCH2_VREF_DQ0_INT_TAP0Selection for internal reference voltage driveRW0x0
0x0: Disabled
0x1: Enabled
23DDRCH2_VREF_DQ0_INT_TAP1Selection for internal reference voltage driveRW0x1
0x0: Disabled
0x1: Enabled
22DDRCH2_VREF_DQ0_INT_ENEnableRW0x1
0x0: Disabled
0x1: Enabled
21DDRCH2_VREF_DQ1_INT_CCAP0Selection for coupling cap connectionRW0x1
0x0: Disabled
0x1: Enabled
20DDRCH2_VREF_DQ1_INT_CCAP1Selection for coupling cap connectionRW0x0
0x0: Disabled
0x1: Enabled
19DDRCH2_VREF_DQ1_INT_TAP0Selection for internal reference voltage driveRW0x0
0x0: Disabled
0x1: Enabled
18DDRCH2_VREF_DQ1_INT_TAP1Selection for internal reference voltage driveRW0x1
0x0: Disabled
0x1: Enabled
17DDRCH2_VREF_DQ1_INT_ENEnableRW0x1
0x0: Disabled
0x1: Enabled
16:0RESERVEDR0x13000
Table 18-549 CTRL_CORE_CONTROL_HYST_1
Address Offset0x0000 0E5C
Physical Address0x4A00 2E5CInstanceCTRL_MODULE_CORE
DescriptionRegister for hysteresis and impedance control of the MMC1 pads. Effective when corresponding MUXMODE field is not configured for MMC operation.
TypeRW
313029282726252423222120191817161514131211109876543210
SDCARD_HYSTSDCARD_ICRESERVED
BitsField NameDescriptionTypeReset
31SDCARD_HYST

hysteresis control for sdcard

0x0 = Disabled

0x1 = Enabled

RW0x1
30:29SDCARD_IC

Drive strength control for MMC1 pads

In 3.3V signaling mode:

0x0: 50 Ohms Drive Strength

0x1: 33 Ohms Drive Strength

0x2: 66 Ohms Drive Strength

0x3: Reserved

In 1.8V signaling mode:

0x0: 44 Ohms Drive Strength

0x1: 33 Ohms Drive Strength

0x2: 58 Ohms Drive Strength

0x3: 100 Ohms Drive Strength

RW0x0
28:0RESERVEDR0x0
Table 18-550 CTRL_CORE_CONTROL_SPARE_RW
Address Offset0x0000 0E68
Physical Address0x4A00 2E68InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
CORE_CONTROL_SPARE_RWCORE_CONTROL_SPARE_RW_MMC2_LOOPBACKCORE_CONTROL_SPARE_RW_MMC1_LOOPBACK
BitsField NameDescriptionTypeReset
31:2CORE_CONTROL_SPARE_RWSpare bitsRW0x0
1CORE_CONTROL_SPARE_RW_MMC2_LOOPBACKSelects the source of loopback clock for mmc2_clk.
0x0: Loopback clock from the I/O pad is selected
0x1: Internal loopback clock is selected		RW0x0
0CORE_CONTROL_SPARE_RW_MMC1_LOOPBACKSelects the source of loopback clock for mmc1_clk.
0x0: Loopback clock from the I/O pad is selected
0x1: Internal loopback clock is selected		RW0x0
Table 18-551 CTRL_CORE_SRCOMP_NORTH_SIDE
Address Offset0x0000 0E74
Physical Address0x4A00 2E74InstanceCTRL_MODULE_CORE
DescriptionThis register is related to the USB2_PHY2.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUSB2PHY_AUTORESUME_ENUSB2PHY_DISCHGDETUSB2PHY_PDRESERVEDUSB2PHY_CHG_DET_DM_COMPUSB2PHY_CHG_DET_DP_COMPUSB2PHY_DATADETUSB2PHY_CHGDETDONEUSB2PHY_CHGDETECTEDUSB2PHY_RESETDONEMCLKUSB2PHY_UTMIRESETDONEUSBDPLL_FREQLOCKUSB2PHY_RESETDONETCLKUSB2PHY_GPIOMODEUSB2PHY_CHG_DET_EXT_CTLUSB2PHY_RDM_PD_CHGDET_ENUSB2PHY_RDP_PU_CHGDET_ENUSB2PHY_CHG_VSRC_ENUSB2PHY_CHG_ISINK_ENUSB2PHY_SINKONDPUSB2PHY_SRCONDMUSB2PHY_RESTARTCHGDETUSB2PHY_MCPCPUENUSB2PHY_MCPCMODEENUSB2PHY_DATAPOLARITYN
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30USB2PHY_AUTORESUME_ENAuto resume enable
0x0: disable autoresume
0x1: enable autoresume		RW0x0
29USB2PHY_DISCHGDETDisable charger detect
0x0: charger detect function enabled
0x1: charger detect function disabled		RW0x1
28USB2PHY_PDPower down the entire USB2_PHY2 (data, common module and UTMI).
0x0: Normal operation
0x1: Power down the USB2_PHY2		RW0x0
27:21RESERVEDR0x0
20USB2PHY_CHG_DET_DM_COMPOutput of the comparator on DM during the resistor host detect protocol.
0x0: DM line is below 0.75V to 0.95V
0x1: DM line is above 0.75V to 0.95V		R0x0
19USB2PHY_CHG_DET_DP_COMPOutput of the comparator on DP during the resistor host detect protocol
0x0: DP line is below 0.75V to 0.95V
0x1: DP line is above 0.75V to 0.95V		R0x0
18USB2PHY_DATADETOutput of the charger detect comparator
0x0: DM line is below 0.25V to 0.4V
0x1: DM line is above 0.25V to 0.4V		R0x0
17USB2PHY_CHGDETDONEStatus indicates that charger detection protocol is over
0x0: charger detection protocol is not over
0x1: charger detection protocol is over		R0x0
16USB2PHY_CHGDETECTEDOutput of the charger detection protocol
0x0: charger not detected
0x1: charger detected		R0x0
15USB2PHY_RESETDONEMCLKOCP reset status
0x0: OCP domain is in reset
0x1: OCP domain is out of reset		R0x0
14USB2PHY_UTMIRESETDONEUTMI FSM reset status
0x0: UTMI FSMs are in reset
0x1: UTMI FSMs are out of reset		R0x0
13USBDPLL_FREQLOCKStatus from USB DPLLR0x0
12USB2PHY_RESETDONETCLKresetdonetclk status from USB2_PHY2R0x0
11USB2PHY_GPIOMODEGPIO mode
0x0: USB mode enabled
0x1: GPIO mode enabled		RW0x0
10USB2PHY_CHG_DET_EXT_CTLCharge detect external control
0x0: charger detect internal state machine used
0x1: charge detect statemachine is bypassed		RW0x0
9USB2PHY_RDM_PD_CHGDET_ENDM Pull down control
0x0: PD disabled
0x1: PD enabled		RW0x0
8USB2PHY_RDP_PU_CHGDET_ENDP Pull up control
0x0: PU disabled
0x1: PU enabled		RW0x0
7USB2PHY_CHG_VSRC_ENVSRC enable on DP line: Host charger case
0x0: disable VSRC drive on DP
0x1: drives VSRC 600mV on DP line		RW0x0
6USB2PHY_CHG_ISINK_ENISINK enable on DM line: Host charger case
0x0: disable the ISINK on DM
0x1: enables the ISINK (100µA) on DM line		RW0x0
5USB2PHY_SINKONDPWhen '1' current sink is connected to DP instead of DM
0x0: Default value
0x1: enables the ISINK on DP instead of DM		RW0x0
4USB2PHY_SRCONDMWhen '1' voltage source is connected to DP instead of DM
0x0: Default value
0x1: enable the VSRC on DM instead of DP		RW0x0
3USB2PHY_RESTARTCHGDETrestartchgdet: '1' for 1 msec cause the CD_START to reset
0x0: Default value
0x1: a high pulse of 1 msec causes the charger detect to restart on negative edge of restartchgdet		RW0x0
2USB2PHY_MCPCPUENMCPC Pull up enable
0x0: disable the MCPC pull up
0x1: enable the 4.7K to10K pull up on receive line DP when datapolarityn is 0 and DM when datapolarityn is 1		RW0x0
1USB2PHY_MCPCMODEENMCPC Mode enable
0x0: disable MCPC mode
0x1: enable MCPC mode		RW0x0
0USB2PHY_DATAPOLARITYNData polarity
0x0: DP functionality is on DP and DM funcationality is on DM
0x1: DP functionality is on DM and DM functionality is on DP		RW0x0
Table 18-552 CTRL_CORE_SRCOMP_SOUTH_SIDE
Address Offset0x0000 0E78
Physical Address0x4A00 2E78InstanceCTRL_MODULE_CORE
DescriptionThis register is related to the USB2_PHY2.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDUSB2PHY_CHG_DET_STATUSRESERVED
BitsField NameDescriptionTypeReset
31:15RESERVEDR0x0
14:12USB2PHY_CHG_DET_STATUSStatus of charger detection
0x0: Wait state
0x1: No contact
0x2: PS/2
0x3: Unknown error
0x4: Dedicated charger
0x5: HOST charger
0x6: PC
0x7: Interrupt		R0x0
11:0RESERVEDR0x0
Table 18-553 CTRL_CORE_PAD_GPMC_AD0
Address Offset0x0000 1400
Physical Address0x4A00 3400InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD0_WAKEUPEVENTGPMC_AD0_WAKEUPENABLERESERVEDGPMC_AD0_SLEWCONTROLGPMC_AD0_INPUTENABLEGPMC_AD0_PULLTYPESELECTGPMC_AD0_PULLUDENABLERESERVEDGPMC_AD0_MODESELECTGPMC_AD0_DELAYMODEGPMC_AD0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD0_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD0_MUXMODERW0xF
0x0: gpmc_ad0
0x2: vin3a_d0
0x3: vout3_d0
0xE: gpio1_6
0xF: sysboot0
Table 18-554 CTRL_CORE_PAD_GPMC_AD1
Address Offset0x0000 1404
Physical Address0x4A00 3404InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD1_WAKEUPEVENTGPMC_AD1_WAKEUPENABLERESERVEDGPMC_AD1_SLEWCONTROLGPMC_AD1_INPUTENABLEGPMC_AD1_PULLTYPESELECTGPMC_AD1_PULLUDENABLERESERVEDGPMC_AD1_MODESELECTGPMC_AD1_DELAYMODEGPMC_AD1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD1_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD1_MUXMODERW0xF
0x0: gpmc_ad1
0x2: vin3a_d1
0x3: vout3_d1
0xE: gpio1_7
0xF: sysboot1
Table 18-555 CTRL_CORE_PAD_GPMC_AD2
Address Offset0x0000 1408
Physical Address0x4A00 3408InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD2_WAKEUPEVENTGPMC_AD2_WAKEUPENABLERESERVEDGPMC_AD2_SLEWCONTROLGPMC_AD2_INPUTENABLEGPMC_AD2_PULLTYPESELECTGPMC_AD2_PULLUDENABLERESERVEDGPMC_AD2_MODESELECTGPMC_AD2_DELAYMODEGPMC_AD2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD2_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD2_MUXMODERW0xF
0x0: gpmc_ad2
0x2: vin3a_d2
0x3: vout3_d2
0xE: gpio1_8
0xF: sysboot2
Table 18-556 CTRL_CORE_PAD_GPMC_AD3
Address Offset0x0000 140C
Physical Address0x4A00 340CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD3_WAKEUPEVENTGPMC_AD3_WAKEUPENABLERESERVEDGPMC_AD3_SLEWCONTROLGPMC_AD3_INPUTENABLEGPMC_AD3_PULLTYPESELECTGPMC_AD3_PULLUDENABLERESERVEDGPMC_AD3_MODESELECTGPMC_AD3_DELAYMODEGPMC_AD3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD3_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD3_MUXMODERW0xF
0x0: gpmc_ad3
0x2: vin3a_d3
0x3: vout3_d3
0xE: gpio1_9
0xF: sysboot3
Table 18-557 CTRL_CORE_PAD_GPMC_AD4
Address Offset0x0000 1410
Physical Address0x4A00 3410InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD4_WAKEUPEVENTGPMC_AD4_WAKEUPENABLERESERVEDGPMC_AD4_SLEWCONTROLGPMC_AD4_INPUTENABLEGPMC_AD4_PULLTYPESELECTGPMC_AD4_PULLUDENABLERESERVEDGPMC_AD4_MODESELECTGPMC_AD4_DELAYMODEGPMC_AD4_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD4_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD4_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD4_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD4_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD4_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD4_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD4_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD4_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD4_MUXMODERW0xF
0x0: gpmc_ad4
0x2: vin3a_d4
0x3: vout3_d4
0xE: gpio1_10
0xF: sysboot4
Table 18-558 CTRL_CORE_PAD_GPMC_AD5
Address Offset0x0000 1414
Physical Address0x4A00 3414InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD5_WAKEUPEVENTGPMC_AD5_WAKEUPENABLERESERVEDGPMC_AD5_SLEWCONTROLGPMC_AD5_INPUTENABLEGPMC_AD5_PULLTYPESELECTGPMC_AD5_PULLUDENABLERESERVEDGPMC_AD5_MODESELECTGPMC_AD5_DELAYMODEGPMC_AD5_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD5_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD5_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD5_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD5_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD5_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD5_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD5_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD5_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD5_MUXMODERW0xF
0x0: gpmc_ad5
0x2: vin3a_d5
0x3: vout3_d5
0xE: gpio1_11
0xF: sysboot5
Table 18-559 CTRL_CORE_PAD_GPMC_AD6
Address Offset0x0000 1418
Physical Address0x4A00 3418InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD6_WAKEUPEVENTGPMC_AD6_WAKEUPENABLERESERVEDGPMC_AD6_SLEWCONTROLGPMC_AD6_INPUTENABLEGPMC_AD6_PULLTYPESELECTGPMC_AD6_PULLUDENABLERESERVEDGPMC_AD6_MODESELECTGPMC_AD6_DELAYMODEGPMC_AD6_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD6_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD6_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD6_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD6_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD6_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD6_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD6_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD6_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD6_MUXMODERW0xF
0x0: gpmc_ad6
0x2: vin3a_d6
0x3: vout3_d6
0xE: gpio1_12
0xF: sysboot6
Table 18-560 CTRL_CORE_PAD_GPMC_AD7
Address Offset0x0000 141C
Physical Address0x4A00 341CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD7_WAKEUPEVENTGPMC_AD7_WAKEUPENABLERESERVEDGPMC_AD7_SLEWCONTROLGPMC_AD7_INPUTENABLEGPMC_AD7_PULLTYPESELECTGPMC_AD7_PULLUDENABLERESERVEDGPMC_AD7_MODESELECTGPMC_AD7_DELAYMODEGPMC_AD7_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD7_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD7_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD7_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD7_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD7_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD7_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD7_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD7_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD7_MUXMODERW0xF
0x0: gpmc_ad7
0x2: vin3a_d7
0x3: vout3_d7
0xE: gpio1_13
0xF: sysboot7
Table 18-561 CTRL_CORE_PAD_GPMC_AD8
Address Offset0x0000 1420
Physical Address0x4A00 3420InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD8_WAKEUPEVENTGPMC_AD8_WAKEUPENABLERESERVEDGPMC_AD8_SLEWCONTROLGPMC_AD8_INPUTENABLEGPMC_AD8_PULLTYPESELECTGPMC_AD8_PULLUDENABLERESERVEDGPMC_AD8_MODESELECTGPMC_AD8_DELAYMODEGPMC_AD8_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD8_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD8_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD8_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD8_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD8_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD8_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD8_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD8_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD8_MUXMODERW0xF
0x0: gpmc_ad8
0x2: vin3a_d8
0x3: vout3_d8
0xE: gpio7_18
0xF: sysboot8
Table 18-562 CTRL_CORE_PAD_GPMC_AD9
Address Offset0x0000 1424
Physical Address0x4A00 3424InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD9_WAKEUPEVENTGPMC_AD9_WAKEUPENABLERESERVEDGPMC_AD9_SLEWCONTROLGPMC_AD9_INPUTENABLEGPMC_AD9_PULLTYPESELECTGPMC_AD9_PULLUDENABLERESERVEDGPMC_AD9_MODESELECTGPMC_AD9_DELAYMODEGPMC_AD9_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD9_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD9_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD9_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD9_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD9_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD9_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD9_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD9_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD9_MUXMODERW0xF
0x0: gpmc_ad9
0x2: vin3a_d9
0x3: vout3_d9
0xE: gpio7_19
0xF: sysboot9
Table 18-563 CTRL_CORE_PAD_GPMC_AD10
Address Offset0x0000 1428
Physical Address0x4A00 3428InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD10_WAKEUPEVENTGPMC_AD10_WAKEUPENABLERESERVEDGPMC_AD10_SLEWCONTROLGPMC_AD10_INPUTENABLEGPMC_AD10_PULLTYPESELECTGPMC_AD10_PULLUDENABLERESERVEDGPMC_AD10_MODESELECTGPMC_AD10_DELAYMODEGPMC_AD10_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD10_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD10_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD10_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD10_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD10_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD10_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD10_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD10_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD10_MUXMODERW0xF
0x0: gpmc_ad10
0x2: vin3a_d10
0x3: vout3_d10
0xE: gpio7_28
0xF: sysboot10
Table 18-564 CTRL_CORE_PAD_GPMC_AD11
Address Offset0x0000 142C
Physical Address0x4A00 342CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD11_WAKEUPEVENTGPMC_AD11_WAKEUPENABLERESERVEDGPMC_AD11_SLEWCONTROLGPMC_AD11_INPUTENABLEGPMC_AD11_PULLTYPESELECTGPMC_AD11_PULLUDENABLERESERVEDGPMC_AD11_MODESELECTGPMC_AD11_DELAYMODEGPMC_AD11_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD11_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD11_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD11_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD11_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD11_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD11_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD11_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD11_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD11_MUXMODERW0xF
0x0: gpmc_ad11
0x2: vin3a_d11
0x3: vout3_d11
0xE: gpio7_29
0xF: sysboot11
Table 18-565 CTRL_CORE_PAD_GPMC_AD12
Address Offset0x0000 1430
Physical Address0x4A00 3430InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD12_WAKEUPEVENTGPMC_AD12_WAKEUPENABLERESERVEDGPMC_AD12_SLEWCONTROLGPMC_AD12_INPUTENABLEGPMC_AD12_PULLTYPESELECTGPMC_AD12_PULLUDENABLERESERVEDGPMC_AD12_MODESELECTGPMC_AD12_DELAYMODEGPMC_AD12_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD12_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD12_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD12_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD12_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD12_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD12_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD12_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD12_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD12_MUXMODERW0xF
0x0: gpmc_ad12
0x2: vin3a_d12
0x3: vout3_d12
0xE: gpio1_18
0xF: sysboot12
Table 18-566 CTRL_CORE_PAD_GPMC_AD13
Address Offset0x0000 1434
Physical Address0x4A00 3434InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD13_WAKEUPEVENTGPMC_AD13_WAKEUPENABLERESERVEDGPMC_AD13_SLEWCONTROLGPMC_AD13_INPUTENABLEGPMC_AD13_PULLTYPESELECTGPMC_AD13_PULLUDENABLERESERVEDGPMC_AD13_MODESELECTGPMC_AD13_DELAYMODEGPMC_AD13_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD13_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD13_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD13_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD13_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD13_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD13_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD13_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD13_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD13_MUXMODERW0xF
0x0: gpmc_ad13
0x2: vin3a_d13
0x3: vout3_d13
0xE: gpio1_19
0xF: sysboot13
Table 18-567 CTRL_CORE_PAD_GPMC_AD14
Address Offset0x0000 1438
Physical Address0x4A00 3438InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD14_WAKEUPEVENTGPMC_AD14_WAKEUPENABLERESERVEDGPMC_AD14_SLEWCONTROLGPMC_AD14_INPUTENABLEGPMC_AD14_PULLTYPESELECTGPMC_AD14_PULLUDENABLERESERVEDGPMC_AD14_MODESELECTGPMC_AD14_DELAYMODEGPMC_AD14_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD14_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD14_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD14_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD14_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD14_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD14_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD14_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD14_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD14_MUXMODERW0xF
0x0: gpmc_ad14
0x2: vin3a_d14
0x3: vout3_d14
0xE: gpio1_20
0xF: sysboot14
Table 18-568 CTRL_CORE_PAD_GPMC_AD15
Address Offset0x0000 143C
Physical Address0x4A00 343CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_AD15_WAKEUPEVENTGPMC_AD15_WAKEUPENABLERESERVEDGPMC_AD15_SLEWCONTROLGPMC_AD15_INPUTENABLEGPMC_AD15_PULLTYPESELECTGPMC_AD15_PULLUDENABLERESERVEDGPMC_AD15_MODESELECTGPMC_AD15_DELAYMODEGPMC_AD15_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_AD15_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_AD15_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_AD15_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_AD15_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_AD15_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_AD15_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_AD15_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_AD15_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_AD15_MUXMODERW0xF
0x0: gpmc_ad15
0x2: vin3a_d15
0x3: vout3_d15
0xE: gpio1_21
0xF: sysboot15
Table 18-569 CTRL_CORE_PAD_GPMC_A0
Address Offset0x0000 1440
Physical Address0x4A00 3440InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A0_WAKEUPEVENTGPMC_A0_WAKEUPENABLERESERVEDGPMC_A0_SLEWCONTROLGPMC_A0_INPUTENABLEGPMC_A0_PULLTYPESELECTGPMC_A0_PULLUDENABLERESERVEDGPMC_A0_MODESELECTGPMC_A0_DELAYMODEGPMC_A0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A0_MUXMODERW0xF
0x0: gpmc_a0
0x2: vin3a_d16
0x3: vout3_d16
0x4: vin4a_d0
0x6: vin4b_d0
0x7: i2c4_scl
0x8: uart5_rxd
0xE: gpio7_3
0xF: Driver off
Table 18-570 CTRL_CORE_PAD_GPMC_A1
Address Offset0x0000 1444
Physical Address0x4A00 3444InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A1_WAKEUPEVENTGPMC_A1_WAKEUPENABLERESERVEDGPMC_A1_SLEWCONTROLGPMC_A1_INPUTENABLEGPMC_A1_PULLTYPESELECTGPMC_A1_PULLUDENABLERESERVEDGPMC_A1_MODESELECTGPMC_A1_DELAYMODEGPMC_A1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A1_MUXMODERW0xF
0x0: gpmc_a1
0x2: vin3a_d17
0x3: vout3_d17
0x4: vin4a_d1
0x6: vin4b_d1
0x7: i2c4_sda
0x8: uart5_txd
0xE: gpio7_4
0xF: Driver off
Table 18-571 CTRL_CORE_PAD_GPMC_A2
Address Offset0x0000 1448
Physical Address0x4A00 3448InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A2_WAKEUPEVENTGPMC_A2_WAKEUPENABLERESERVEDGPMC_A2_SLEWCONTROLGPMC_A2_INPUTENABLEGPMC_A2_PULLTYPESELECTGPMC_A2_PULLUDENABLERESERVEDGPMC_A2_MODESELECTGPMC_A2_DELAYMODEGPMC_A2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A2_MUXMODERW0xF
0x0: gpmc_a2
0x2: vin3a_d18
0x3: vout3_d18
0x4: vin4a_d2
0x6: vin4b_d2
0x7: uart7_rxd
0x8: uart5_ctsn
0xE: gpio7_5
0xF: Driver off
Table 18-572 CTRL_CORE_PAD_GPMC_A3
Address Offset0x0000 144C
Physical Address0x4A00 344CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A3_WAKEUPEVENTGPMC_A3_WAKEUPENABLERESERVEDGPMC_A3_SLEWCONTROLGPMC_A3_INPUTENABLEGPMC_A3_PULLTYPESELECTGPMC_A3_PULLUDENABLERESERVEDGPMC_A3_MODESELECTGPMC_A3_DELAYMODEGPMC_A3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A3_MUXMODERW0xF
0x0: gpmc_a3
0x1: qspi1_cs2
0x2: vin3a_d19
0x3: vout3_d19
0x4: vin4a_d3
0x6: vin4b_d3
0x7: uart7_txd
0x8: uart5_rtsn
0xE: gpio7_6
0xF: Driver off
Table 18-573 CTRL_CORE_PAD_GPMC_A4
Address Offset0x0000 1450
Physical Address0x4A00 3450InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A4_WAKEUPEVENTGPMC_A4_WAKEUPENABLERESERVEDGPMC_A4_SLEWCONTROLGPMC_A4_INPUTENABLEGPMC_A4_PULLTYPESELECTGPMC_A4_PULLUDENABLERESERVEDGPMC_A4_MODESELECTGPMC_A4_DELAYMODEGPMC_A4_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A4_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A4_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A4_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A4_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A4_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A4_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A4_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A4_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A4_MUXMODERW0xF
0x0: gpmc_a4
0x1: qspi1_cs3
0x2: vin3a_d20
0x3: vout3_d20
0x4: vin4a_d4
0x6: vin4b_d4
0x7: i2c5_scl
0x8: uart6_rxd
0xE: gpio1_26
0xF: Driver off
Table 18-574 CTRL_CORE_PAD_GPMC_A5
Address Offset0x0000 1454
Physical Address0x4A00 3454InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A5_WAKEUPEVENTGPMC_A5_WAKEUPENABLERESERVEDGPMC_A5_SLEWCONTROLGPMC_A5_INPUTENABLEGPMC_A5_PULLTYPESELECTGPMC_A5_PULLUDENABLERESERVEDGPMC_A5_MODESELECTGPMC_A5_DELAYMODEGPMC_A5_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A5_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A5_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A5_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A5_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A5_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A5_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A5_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A5_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A5_MUXMODERW0xF
0x0: gpmc_a5
0x2: vin3a_d21
0x3: vout3_d21
0x4: vin4a_d5
0x6: vin4b_d5
0x7: i2c5_sda
0x8: uart6_txd
0xE: gpio1_27
0xF: Driver off
Table 18-575 CTRL_CORE_PAD_GPMC_A6
Address Offset0x0000 1458
Physical Address0x4A00 3458InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A6_WAKEUPEVENTGPMC_A6_WAKEUPENABLERESERVEDGPMC_A6_SLEWCONTROLGPMC_A6_INPUTENABLEGPMC_A6_PULLTYPESELECTGPMC_A6_PULLUDENABLERESERVEDGPMC_A6_MODESELECTGPMC_A6_DELAYMODEGPMC_A6_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A6_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A6_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A6_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A6_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A6_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A6_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A6_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A6_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A6_MUXMODERW0xF
0x0: gpmc_a6
0x2: vin3a_d22
0x3: vout3_d22
0x4: vin4a_d6
0x6: vin4b_d6
0x7: uart8_rxd
0x8: uart6_ctsn
0xE: gpio1_28
0xF: Driver off
Table 18-576 CTRL_CORE_PAD_GPMC_A7
Address Offset0x0000 145C
Physical Address0x4A00 345CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A7_WAKEUPEVENTGPMC_A7_WAKEUPENABLERESERVEDGPMC_A7_SLEWCONTROLGPMC_A7_INPUTENABLEGPMC_A7_PULLTYPESELECTGPMC_A7_PULLUDENABLERESERVEDGPMC_A7_MODESELECTGPMC_A7_DELAYMODEGPMC_A7_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A7_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A7_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A7_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A7_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A7_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A7_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A7_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A7_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A7_MUXMODERW0xF
0x0: gpmc_a7
0x2: vin3a_d23
0x3: vout3_d23
0x4: vin4a_d7
0x6: vin4b_d7
0x7: uart8_txd
0x8: uart6_rtsn
0xE: gpio1_29
0xF: Driver off
Table 18-577 CTRL_CORE_PAD_GPMC_A8
Address Offset0x0000 1460
Physical Address0x4A00 3460InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A8_WAKEUPEVENTGPMC_A8_WAKEUPENABLERESERVEDGPMC_A8_SLEWCONTROLGPMC_A8_INPUTENABLEGPMC_A8_PULLTYPESELECTGPMC_A8_PULLUDENABLERESERVEDGPMC_A8_MODESELECTGPMC_A8_DELAYMODEGPMC_A8_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A8_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A8_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A8_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A8_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A8_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A8_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A8_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A8_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A8_MUXMODERW0xF
0x0: gpmc_a8
0x2: vin3a_hsync0
0x3: vout3_hsync
0x6: vin4b_hsync1
0x7: timer12
0x8: spi4_sclk
0xE: gpio1_30
0xF: Driver off
Table 18-578 CTRL_CORE_PAD_GPMC_A9
Address Offset0x0000 1464
Physical Address0x4A00 3464InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A9_WAKEUPEVENTGPMC_A9_WAKEUPENABLERESERVEDGPMC_A9_SLEWCONTROLGPMC_A9_INPUTENABLEGPMC_A9_PULLTYPESELECTGPMC_A9_PULLUDENABLERESERVEDGPMC_A9_MODESELECTGPMC_A9_DELAYMODEGPMC_A9_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A9_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A9_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A9_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A9_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A9_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A9_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A9_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A9_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A9_MUXMODERW0xF
0x0: gpmc_a9
0x2: vin3a_vsync0
0x3: vout3_vsync
0x6: vin4b_vsync1
0x7: timer11
0x8: spi4_d1
0xE: gpio1_31
0xF: Driver off
Table 18-579 CTRL_CORE_PAD_GPMC_A10
Address Offset0x0000 1468
Physical Address0x4A00 3468InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A10_WAKEUPEVENTGPMC_A10_WAKEUPENABLERESERVEDGPMC_A10_SLEWCONTROLGPMC_A10_INPUTENABLEGPMC_A10_PULLTYPESELECTGPMC_A10_PULLUDENABLERESERVEDGPMC_A10_MODESELECTGPMC_A10_DELAYMODEGPMC_A10_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A10_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A10_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A10_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A10_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A10_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A10_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A10_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A10_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A10_MUXMODERW0xF
0x0: gpmc_a10
0x2: vin3a_de0
0x3: vout3_de
0x6: vin4b_clk1
0x7: timer10
0x8: spi4_d0
0xE: gpio2_0
0xF: Driver off
Table 18-580 CTRL_CORE_PAD_GPMC_A11
Address Offset0x0000 146C
Physical Address0x4A00 346CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A11_WAKEUPEVENTGPMC_A11_WAKEUPENABLERESERVEDGPMC_A11_SLEWCONTROLGPMC_A11_INPUTENABLEGPMC_A11_PULLTYPESELECTGPMC_A11_PULLUDENABLERESERVEDGPMC_A11_MODESELECTGPMC_A11_DELAYMODEGPMC_A11_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A11_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A11_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A11_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A11_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A11_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A11_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A11_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A11_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A11_MUXMODERW0xF
0x0: gpmc_a11
0x2: vin3a_fld0
0x3: vout3_fld
0x4: vin4a_fld0
0x6: vin4b_de1
0x7: timer9
0x8: spi4_cs0
0xE: gpio2_1
0xF: Driver off
Table 18-581 CTRL_CORE_PAD_GPMC_A12
Address Offset0x0000 1470
Physical Address0x4A00 3470InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A12_WAKEUPEVENTGPMC_A12_WAKEUPENABLERESERVEDGPMC_A12_SLEWCONTROLGPMC_A12_INPUTENABLEGPMC_A12_PULLTYPESELECTGPMC_A12_PULLUDENABLERESERVEDGPMC_A12_MODESELECTGPMC_A12_DELAYMODEGPMC_A12_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A12_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A12_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A12_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A12_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A12_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A12_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A12_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A12_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A12_MUXMODERW0xF
0x0: gpmc_a12
0x4: vin4a_clk0
0x5: gpmc_a0
0x6: vin4b_fld1
0x7: timer8
0x8: spi4_cs1
0x9: dma_evt1
0xE: gpio2_2
0xF: Driver off
Table 18-582 CTRL_CORE_PAD_GPMC_A13
Address Offset0x0000 1474
Physical Address0x4A00 3474InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A13_WAKEUPEVENTGPMC_A13_WAKEUPENABLERESERVEDGPMC_A13_SLEWCONTROLGPMC_A13_INPUTENABLEGPMC_A13_PULLTYPESELECTGPMC_A13_PULLUDENABLERESERVEDGPMC_A13_MODESELECTGPMC_A13_DELAYMODEGPMC_A13_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A13_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A13_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A13_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A13_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A13_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A13_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A13_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A13_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A13_MUXMODERW0xF
0x0: gpmc_a13
0x1: qspi1_rtclk
0x4: vin4a_hsync0
0x7: timer7
0x8: spi4_cs2
0x9: dma_evt2
0xE: gpio2_3
0xF: Driver off
Table 18-583 CTRL_CORE_PAD_GPMC_A14
Address Offset0x0000 1478
Physical Address0x4A00 3478InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A14_WAKEUPEVENTGPMC_A14_WAKEUPENABLERESERVEDGPMC_A14_SLEWCONTROLGPMC_A14_INPUTENABLEGPMC_A14_PULLTYPESELECTGPMC_A14_PULLUDENABLERESERVEDGPMC_A14_MODESELECTGPMC_A14_DELAYMODEGPMC_A14_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A14_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A14_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A14_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A14_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A14_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A14_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A14_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A14_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A14_MUXMODERW0xF
0x0: gpmc_a14
0x1: qspi1_d3
0x4: vin4a_vsync0
0x7: timer6
0x8: spi4_cs3
0xE: gpio2_4
0xF: Driver off
Table 18-584 CTRL_CORE_PAD_GPMC_A15
Address Offset0x0000 147C
Physical Address0x4A00 347CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A15_WAKEUPEVENTGPMC_A15_WAKEUPENABLERESERVEDGPMC_A15_SLEWCONTROLGPMC_A15_INPUTENABLEGPMC_A15_PULLTYPESELECTGPMC_A15_PULLUDENABLERESERVEDGPMC_A15_MODESELECTGPMC_A15_DELAYMODEGPMC_A15_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A15_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A15_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A15_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A15_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A15_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A15_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A15_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A15_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A15_MUXMODERW0xF
0x0: gpmc_a15
0x1: qspi1_d2
0x4: vin4a_d8
0x7: timer5
0xE: gpio2_5
0xF: Driver off
Table 18-585 CTRL_CORE_PAD_GPMC_A16
Address Offset0x0000 1480
Physical Address0x4A00 3480InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A16_WAKEUPEVENTGPMC_A16_WAKEUPENABLERESERVEDGPMC_A16_SLEWCONTROLGPMC_A16_INPUTENABLEGPMC_A16_PULLTYPESELECTGPMC_A16_PULLUDENABLERESERVEDGPMC_A16_MODESELECTGPMC_A16_DELAYMODEGPMC_A16_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A16_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A16_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A16_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A16_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A16_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A16_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A16_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A16_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A16_MUXMODERW0xF
0x0: gpmc_a16
0x1: qspi1_d0
0x4: vin4a_d9
0xE: gpio2_6
0xF: Driver off
Table 18-586 CTRL_CORE_PAD_GPMC_A17
Address Offset0x0000 1484
Physical Address0x4A00 3484InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A17_WAKEUPEVENTGPMC_A17_WAKEUPENABLERESERVEDGPMC_A17_SLEWCONTROLGPMC_A17_INPUTENABLEGPMC_A17_PULLTYPESELECTGPMC_A17_PULLUDENABLERESERVEDGPMC_A17_MODESELECTGPMC_A17_DELAYMODEGPMC_A17_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A17_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A17_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A17_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A17_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A17_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A17_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A17_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A17_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A17_MUXMODERW0xF
0x0: gpmc_a17
0x1: qspi1_d1
0x4: vin4a_d10
0xE: gpio2_7
0xF: Driver off
Table 18-587 CTRL_CORE_PAD_GPMC_A18
Address Offset0x0000 1488
Physical Address0x4A00 3488InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A18_WAKEUPEVENTGPMC_A18_WAKEUPENABLERESERVEDGPMC_A18_SLEWCONTROLGPMC_A18_INPUTENABLEGPMC_A18_PULLTYPESELECTGPMC_A18_PULLUDENABLERESERVEDGPMC_A18_MODESELECTGPMC_A18_DELAYMODEGPMC_A18_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A18_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A18_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A18_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A18_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A18_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A18_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A18_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A18_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A18_MUXMODERW0xF
0x0: gpmc_a18
0x1: qspi1_sclk
0x4: vin4a_d11
0xE: gpio2_8
0xF: Driver off
Table 18-588 CTRL_CORE_PAD_GPMC_A19
Address Offset0x0000 148C
Physical Address0x4A00 348CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A19_WAKEUPEVENTGPMC_A19_WAKEUPENABLERESERVEDGPMC_A19_SLEWCONTROLGPMC_A19_INPUTENABLEGPMC_A19_PULLTYPESELECTGPMC_A19_PULLUDENABLERESERVEDGPMC_A19_MODESELECTGPMC_A19_DELAYMODEGPMC_A19_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A19_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A19_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A19_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A19_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A19_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A19_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A19_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A19_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A19_MUXMODERW0xF
0x0: gpmc_a19
0x1: mmc2_dat4
0x2: gpmc_a13
0x4: vin4a_d12
0x6: vin3b_d0
0xE: gpio2_9
0xF: Driver off
Table 18-589 CTRL_CORE_PAD_GPMC_A20
Address Offset0x0000 1490
Physical Address0x4A00 3490InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A20_WAKEUPEVENTGPMC_A20_WAKEUPENABLERESERVEDGPMC_A20_SLEWCONTROLGPMC_A20_INPUTENABLEGPMC_A20_PULLTYPESELECTGPMC_A20_PULLUDENABLERESERVEDGPMC_A20_MODESELECTGPMC_A20_DELAYMODEGPMC_A20_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A20_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A20_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A20_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A20_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A20_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A20_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A20_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A20_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A20_MUXMODERW0xF
0x0: gpmc_a20
0x1: mmc2_dat5
0x2: gpmc_a14
0x4: vin4a_d13
0x6: vin3b_d1
0xE: gpio2_10
0xF: Driver off
Table 18-590 CTRL_CORE_PAD_GPMC_A21
Address Offset0x0000 1494
Physical Address0x4A00 3494InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A21_WAKEUPEVENTGPMC_A21_WAKEUPENABLERESERVEDGPMC_A21_SLEWCONTROLGPMC_A21_INPUTENABLEGPMC_A21_PULLTYPESELECTGPMC_A21_PULLUDENABLERESERVEDGPMC_A21_MODESELECTGPMC_A21_DELAYMODEGPMC_A21_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A21_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A21_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A21_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A21_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A21_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A21_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A21_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A21_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A21_MUXMODERW0xF
0x0: gpmc_a21
0x1: mmc2_dat6
0x2: gpmc_a15
0x4: vin4a_d14
0x6: vin3b_d2
0xE: gpio2_11
0xF: Driver off
Table 18-591 CTRL_CORE_PAD_GPMC_A22
Address Offset0x0000 1498
Physical Address0x4A00 3498InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A22_WAKEUPEVENTGPMC_A22_WAKEUPENABLERESERVEDGPMC_A22_SLEWCONTROLGPMC_A22_INPUTENABLEGPMC_A22_PULLTYPESELECTGPMC_A22_PULLUDENABLERESERVEDGPMC_A22_MODESELECTGPMC_A22_DELAYMODEGPMC_A22_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A22_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A22_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A22_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A22_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A22_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A22_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A22_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A22_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A22_MUXMODERW0xF
0x0: gpmc_a22
0x1: mmc2_dat7
0x2: gpmc_a16
0x4: vin4a_d15
0x6: vin3b_d3
0xE: gpio2_12
0xF: Driver off
Table 18-592 CTRL_CORE_PAD_GPMC_A23
Address Offset0x0000 149C
Physical Address0x4A00 349CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A23_WAKEUPEVENTGPMC_A23_WAKEUPENABLERESERVEDGPMC_A23_SLEWCONTROLGPMC_A23_INPUTENABLEGPMC_A23_PULLTYPESELECTGPMC_A23_PULLUDENABLERESERVEDGPMC_A23_MODESELECTGPMC_A23_DELAYMODEGPMC_A23_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A23_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A23_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A23_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A23_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A23_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A23_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A23_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A23_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A23_MUXMODERW0xF
0x0: gpmc_a23
0x1: mmc2_clk
0x2: gpmc_a17
0x4: vin4a_fld0
0x6: vin3b_d4
0xE: gpio2_13
0xF: Driver off
Table 18-593 CTRL_CORE_PAD_GPMC_A24
Address Offset0x0000 14A0
Physical Address0x4A00 34A0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A24_WAKEUPEVENTGPMC_A24_WAKEUPENABLERESERVEDGPMC_A24_SLEWCONTROLGPMC_A24_INPUTENABLEGPMC_A24_PULLTYPESELECTGPMC_A24_PULLUDENABLERESERVEDGPMC_A24_MODESELECTGPMC_A24_DELAYMODEGPMC_A24_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A24_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A24_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A24_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A24_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A24_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A24_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A24_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A24_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A24_MUXMODERW0xF
0x0: gpmc_a24
0x1: mmc2_dat0
0x2: gpmc_a18
0x6: vin3b_d5
0xE: gpio2_14
0xF: Driver off
Table 18-594 CTRL_CORE_PAD_GPMC_A25
Address Offset0x0000 14A4
Physical Address0x4A00 34A4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A25_WAKEUPEVENTGPMC_A25_WAKEUPENABLERESERVEDGPMC_A25_SLEWCONTROLGPMC_A25_INPUTENABLEGPMC_A25_PULLTYPESELECTGPMC_A25_PULLUDENABLERESERVEDGPMC_A25_MODESELECTGPMC_A25_DELAYMODEGPMC_A25_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A25_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A25_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A25_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A25_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A25_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A25_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A25_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A25_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A25_MUXMODERW0xF
0x0: gpmc_a25
0x1: mmc2_dat1
0x2: gpmc_a19
0x6: vin3b_d6
0xE: gpio2_15
0xF: Driver off
Table 18-595 CTRL_CORE_PAD_GPMC_A26
Address Offset0x0000 14A8
Physical Address0x4A00 34A8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A26_WAKEUPEVENTGPMC_A26_WAKEUPENABLERESERVEDGPMC_A26_SLEWCONTROLGPMC_A26_INPUTENABLEGPMC_A26_PULLTYPESELECTGPMC_A26_PULLUDENABLERESERVEDGPMC_A26_MODESELECTGPMC_A26_DELAYMODEGPMC_A26_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A26_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A26_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A26_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A26_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A26_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A26_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A26_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A26_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A26_MUXMODERW0xF
0x0: gpmc_a26
0x1: mmc2_dat2
0x2: gpmc_a20
0x6: vin3b_d7
0xE: gpio2_16
0xF: Driver off
Table 18-596 CTRL_CORE_PAD_GPMC_A27
Address Offset0x0000 14AC
Physical Address0x4A00 34ACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_A27_WAKEUPEVENTGPMC_A27_WAKEUPENABLERESERVEDGPMC_A27_SLEWCONTROLGPMC_A27_INPUTENABLEGPMC_A27_PULLTYPESELECTGPMC_A27_PULLUDENABLERESERVEDGPMC_A27_MODESELECTGPMC_A27_DELAYMODEGPMC_A27_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_A27_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_A27_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_A27_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_A27_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_A27_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_A27_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_A27_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_A27_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_A27_MUXMODERW0xF
0x0: gpmc_a27
0x1: mmc2_dat3
0x2: gpmc_a21
0x6: vin3b_hsync1
0xE: gpio2_17
0xF: Driver off
Table 18-597 CTRL_CORE_PAD_GPMC_CS1
Address Offset0x0000 14B0
Physical Address0x4A00 34B0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_CS1_WAKEUPEVENTGPMC_CS1_WAKEUPENABLERESERVEDGPMC_CS1_SLEWCONTROLGPMC_CS1_INPUTENABLEGPMC_CS1_PULLTYPESELECTGPMC_CS1_PULLUDENABLERESERVEDGPMC_CS1_MODESELECTGPMC_CS1_DELAYMODEGPMC_CS1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_CS1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_CS1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_CS1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_CS1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_CS1_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_CS1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_CS1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_CS1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_CS1_MUXMODERW0xF
0x0: gpmc_cs1
0x1: mmc2_cmd
0x2: gpmc_a22
0x4: vin4a_de0
0x6: vin3b_vsync1
0xE: gpio2_18
0xF: Driver off
Table 18-598 CTRL_CORE_PAD_GPMC_CS0
Address Offset0x0000 14B4
Physical Address0x4A00 34B4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_CS0_WAKEUPEVENTGPMC_CS0_WAKEUPENABLERESERVEDGPMC_CS0_SLEWCONTROLGPMC_CS0_INPUTENABLEGPMC_CS0_PULLTYPESELECTGPMC_CS0_PULLUDENABLERESERVEDGPMC_CS0_MODESELECTGPMC_CS0_DELAYMODEGPMC_CS0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_CS0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_CS0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_CS0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_CS0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_CS0_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_CS0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_CS0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_CS0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_CS0_MUXMODERW0xF
0x0: gpmc_cs0
0xE: gpio2_19
0xF: Driver off
Table 18-599 CTRL_CORE_PAD_GPMC_CS2
Address Offset0x0000 14B8
Physical Address0x4A00 34B8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_CS2_WAKEUPEVENTGPMC_CS2_WAKEUPENABLERESERVEDGPMC_CS2_SLEWCONTROLGPMC_CS2_INPUTENABLEGPMC_CS2_PULLTYPESELECTGPMC_CS2_PULLUDENABLERESERVEDGPMC_CS2_MODESELECTGPMC_CS2_DELAYMODEGPMC_CS2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_CS2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_CS2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_CS2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_CS2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_CS2_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_CS2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_CS2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_CS2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_CS2_MUXMODERW0xF
0x0: gpmc_cs2
0x1: qspi1_cs0
0xE: gpio2_20
0xF: Driver off
Table 18-600 CTRL_CORE_PAD_GPMC_CS3
Address Offset0x0000 14BC
Physical Address0x4A00 34BCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_CS3_WAKEUPEVENTGPMC_CS3_WAKEUPENABLERESERVEDGPMC_CS3_SLEWCONTROLGPMC_CS3_INPUTENABLEGPMC_CS3_PULLTYPESELECTGPMC_CS3_PULLUDENABLERESERVEDGPMC_CS3_MODESELECTGPMC_CS3_DELAYMODEGPMC_CS3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_CS3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_CS3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_CS3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_CS3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_CS3_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_CS3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_CS3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_CS3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_CS3_MUXMODERW0xF
0x0: gpmc_cs3
0x1: qspi1_cs1
0x2: vin3a_clk0
0x3: vout3_clk
0x5: gpmc_a1
0xE: gpio2_21
0xF: Driver off
Table 18-601 CTRL_CORE_PAD_GPMC_CLK
Address Offset0x0000 14C0
Physical Address0x4A00 34C0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_CLK_WAKEUPEVENTGPMC_CLK_WAKEUPENABLERESERVEDGPMC_CLK_SLEWCONTROLGPMC_CLK_INPUTENABLEGPMC_CLK_PULLTYPESELECTGPMC_CLK_PULLUDENABLERESERVEDGPMC_CLK_MODESELECTGPMC_CLK_DELAYMODEGPMC_CLK_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_CLK_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_CLK_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_CLK_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_CLK_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_CLK_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_CLK_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_CLK_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_CLK_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_CLK_MUXMODERW0xF
0x0: gpmc_clk
0x1: gpmc_cs7
0x2: clkout1
0x3: gpmc_wait1
0x4: vin4a_hsync0
0x5: vin4a_de0
0x6: vin3b_clk1
0x7: timer4
0x8: i2c3_scl
0x9: dma_evt1
0xE: gpio2_22
0xF: Driver off
Table 18-602 CTRL_CORE_PAD_GPMC_ADVN_ALE
Address Offset0x0000 14C4
Physical Address0x4A00 34C4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_ADVN_ALE_WAKEUPEVENTGPMC_ADVN_ALE_WAKEUPENABLERESERVEDGPMC_ADVN_ALE_SLEWCONTROLGPMC_ADVN_ALE_INPUTENABLEGPMC_ADVN_ALE_PULLTYPESELECTGPMC_ADVN_ALE_PULLUDENABLERESERVEDGPMC_ADVN_ALE_MODESELECTGPMC_ADVN_ALE_DELAYMODEGPMC_ADVN_ALE_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_ADVN_ALE_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_ADVN_ALE_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_ADVN_ALE_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_ADVN_ALE_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_ADVN_ALE_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_ADVN_ALE_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_ADVN_ALE_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_ADVN_ALE_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_ADVN_ALE_MUXMODERW0xF
0x0: gpmc_advn_ale
0x1: gpmc_cs6
0x2: clkout2
0x3: gpmc_wait1
0x4: vin4a_vsync0
0x5: gpmc_a2
0x6: gpmc_a23
0x7: timer3
0x8: i2c3_sda
0x9: dma_evt2
0xE: gpio2_23
0xF: Driver off
Table 18-603 CTRL_CORE_PAD_GPMC_OEN_REN
Address Offset0x0000 14C8
Physical Address0x4A00 34C8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_OEN_REN_WAKEUPEVENTGPMC_OEN_REN_WAKEUPENABLERESERVEDGPMC_OEN_REN_SLEWCONTROLGPMC_OEN_REN_INPUTENABLEGPMC_OEN_REN_PULLTYPESELECTGPMC_OEN_REN_PULLUDENABLERESERVEDGPMC_OEN_REN_MODESELECTGPMC_OEN_REN_DELAYMODEGPMC_OEN_REN_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_OEN_REN_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_OEN_REN_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_OEN_REN_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_OEN_REN_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_OEN_REN_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_OEN_REN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_OEN_REN_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_OEN_REN_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_OEN_REN_MUXMODERW0xF
0x0: gpmc_oen_ren
0xE: gpio2_24
0xF: Driver off
Table 18-604 CTRL_CORE_PAD_GPMC_WEN
Address Offset0x0000 14CC
Physical Address0x4A00 34CCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_WEN_WAKEUPEVENTGPMC_WEN_WAKEUPENABLERESERVEDGPMC_WEN_SLEWCONTROLGPMC_WEN_INPUTENABLEGPMC_WEN_PULLTYPESELECTGPMC_WEN_PULLUDENABLERESERVEDGPMC_WEN_MODESELECTGPMC_WEN_DELAYMODEGPMC_WEN_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_WEN_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_WEN_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_WEN_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_WEN_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_WEN_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_WEN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_WEN_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_WEN_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_WEN_MUXMODERW0xF
0x0: gpmc_wen
0xE: gpio2_25
0xF: Driver off
Table 18-605 CTRL_CORE_PAD_GPMC_BEN0
Address Offset0x0000 14D0
Physical Address0x4A00 34D0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_BEN0_WAKEUPEVENTGPMC_BEN0_WAKEUPENABLERESERVEDGPMC_BEN0_SLEWCONTROLGPMC_BEN0_INPUTENABLEGPMC_BEN0_PULLTYPESELECTGPMC_BEN0_PULLUDENABLERESERVEDGPMC_BEN0_MODESELECTGPMC_BEN0_DELAYMODEGPMC_BEN0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_BEN0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_BEN0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_BEN0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_BEN0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_BEN0_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_BEN0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_BEN0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_BEN0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_BEN0_MUXMODERW0xF
0x0: gpmc_ben0
0x1: gpmc_cs4
0x3: vin1b_hsync1
0x6: vin3b_de1
0x7: timer2
0x9: dma_evt3
0xE: gpio2_26
0xF: Driver off
Table 18-606 CTRL_CORE_PAD_GPMC_BEN1
Address Offset0x0000 14D4
Physical Address0x4A00 34D4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_BEN1_WAKEUPEVENTGPMC_BEN1_WAKEUPENABLERESERVEDGPMC_BEN1_SLEWCONTROLGPMC_BEN1_INPUTENABLEGPMC_BEN1_PULLTYPESELECTGPMC_BEN1_PULLUDENABLERESERVEDGPMC_BEN1_MODESELECTGPMC_BEN1_DELAYMODEGPMC_BEN1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_BEN1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_BEN1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_BEN1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_BEN1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_BEN1_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_BEN1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_BEN1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_BEN1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_BEN1_MUXMODERW0xF
0x0: gpmc_ben1
0x1: gpmc_cs5
0x3: vin1b_de1
0x4: vin3b_clk1
0x5: gpmc_a3
0x6: vin3b_fld1
0x7: timer1
0x9: dma_evt4
0xE: gpio2_27
0xF: Driver off
Table 18-607 CTRL_CORE_PAD_GPMC_WAIT0
Address Offset0x0000 14D8
Physical Address0x4A00 34D8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPMC_WAIT0_WAKEUPEVENTGPMC_WAIT0_WAKEUPENABLERESERVEDGPMC_WAIT0_SLEWCONTROLGPMC_WAIT0_INPUTENABLEGPMC_WAIT0_PULLTYPESELECTGPMC_WAIT0_PULLUDENABLERESERVEDGPMC_WAIT0_MODESELECTGPMC_WAIT0_DELAYMODEGPMC_WAIT0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPMC_WAIT0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPMC_WAIT0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPMC_WAIT0_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPMC_WAIT0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPMC_WAIT0_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPMC_WAIT0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPMC_WAIT0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPMC_WAIT0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPMC_WAIT0_MUXMODERW0xF
0x0: gpmc_wait0
0xE: gpio2_28
0xF: Driver off
Table 18-608 CTRL_CORE_PAD_VIN1A_CLK0
Address Offset0x0000 14DC
Physical Address0x4A00 34DCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_CLK0_WAKEUPEVENTVIN1A_CLK0_WAKEUPENABLERESERVEDVIN1A_CLK0_SLEWCONTROLVIN1A_CLK0_INPUTENABLEVIN1A_CLK0_PULLTYPESELECTVIN1A_CLK0_PULLUDENABLERESERVEDVIN1A_CLK0_MODESELECTVIN1A_CLK0_DELAYMODEVIN1A_CLK0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_CLK0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_CLK0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_CLK0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_CLK0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_CLK0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_CLK0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_CLK0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_CLK0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_CLK0_MUXMODERW0xF
0x0: vin1a_clk0
0x3: vout3_d16
0x4: vout3_fld
0xE: gpio2_30
0xF: Driver off
Table 18-609 CTRL_CORE_PAD_VIN1B_CLK1
Address Offset0x0000 14E0
Physical Address0x4A00 34E0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1B_CLK1_WAKEUPEVENTVIN1B_CLK1_WAKEUPENABLERESERVEDVIN1B_CLK1_SLEWCONTROLVIN1B_CLK1_INPUTENABLEVIN1B_CLK1_PULLTYPESELECTVIN1B_CLK1_PULLUDENABLERESERVEDVIN1B_CLK1_MODESELECTVIN1B_CLK1_DELAYMODEVIN1B_CLK1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1B_CLK1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1B_CLK1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1B_CLK1_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1B_CLK1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1B_CLK1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1B_CLK1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1B_CLK1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1B_CLK1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1B_CLK1_MUXMODERW0xF
0x0: vin1b_clk1
0x6: vin3a_clk0
0xE: gpio2_31
0xF: Driver off
Table 18-610 CTRL_CORE_PAD_VIN1A_DE0
Address Offset0x0000 14E4
Physical Address0x4A00 34E4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_DE0_WAKEUPEVENTVIN1A_DE0_WAKEUPENABLERESERVEDVIN1A_DE0_SLEWCONTROLVIN1A_DE0_INPUTENABLEVIN1A_DE0_PULLTYPESELECTVIN1A_DE0_PULLUDENABLERESERVEDVIN1A_DE0_MODESELECTVIN1A_DE0_DELAYMODEVIN1A_DE0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_DE0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_DE0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_DE0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_DE0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_DE0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_DE0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_DE0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_DE0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_DE0_MUXMODERW0xF
0x0: vin1a_de0
0x1: vin1b_hsync1
0x3: vout3_d17
0x4: vout3_de
0x5: uart7_rxd
0x7: timer16
0x8: spi3_sclk
0x9: kbd_row0
0xA: eQEP1A_in
0xE: gpio3_0
0xF: Driver off
Table 18-611 CTRL_CORE_PAD_VIN1A_FLD0
Address Offset0x0000 14E8
Physical Address0x4A00 34E8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_FLD0_WAKEUPEVENTVIN1A_FLD0_WAKEUPENABLERESERVEDVIN1A_FLD0_SLEWCONTROLVIN1A_FLD0_INPUTENABLEVIN1A_FLD0_PULLTYPESELECTVIN1A_FLD0_PULLUDENABLERESERVEDVIN1A_FLD0_MODESELECTVIN1A_FLD0_DELAYMODEVIN1A_FLD0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_FLD0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_FLD0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_FLD0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_FLD0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_FLD0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_FLD0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_FLD0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_FLD0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_FLD0_MUXMODERW0xF
0x0: vin1a_fld0
0x1: vin1b_vsync1
0x4: vout3_clk
0x5: uart7_txd
0x7: timer15
0x8: spi3_d1
0x9: kbd_row1
0xA: eQEP1B_in
0xE: gpio3_1
0xF: Driver off
Table 18-612 CTRL_CORE_PAD_VIN1A_HSYNC0
Address Offset0x0000 14EC
Physical Address0x4A00 34ECInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_HSYNC0_WAKEUPEVENTVIN1A_HSYNC0_WAKEUPENABLERESERVEDVIN1A_HSYNC0_SLEWCONTROLVIN1A_HSYNC0_INPUTENABLEVIN1A_HSYNC0_PULLTYPESELECTVIN1A_HSYNC0_PULLUDENABLERESERVEDVIN1A_HSYNC0_MODESELECTVIN1A_HSYNC0_DELAYMODEVIN1A_HSYNC0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_HSYNC0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_HSYNC0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_HSYNC0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_HSYNC0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_HSYNC0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_HSYNC0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_HSYNC0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_HSYNC0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_HSYNC0_MUXMODERW0xF
0x0: vin1a_hsync0
0x1: vin1b_fld1
0x4: vout3_hsync
0x5: uart7_ctsn
0x7: timer14
0x8: spi3_d0
0xA: eQEP1_index
0xE: gpio3_2
0xF: Driver off
Table 18-613 CTRL_CORE_PAD_VIN1A_VSYNC0
Address Offset0x0000 14F0
Physical Address0x4A00 34F0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_VSYNC0_WAKEUPEVENTVIN1A_VSYNC0_WAKEUPENABLERESERVEDVIN1A_VSYNC0_SLEWCONTROLVIN1A_VSYNC0_INPUTENABLEVIN1A_VSYNC0_PULLTYPESELECTVIN1A_VSYNC0_PULLUDENABLERESERVEDVIN1A_VSYNC0_MODESELECTVIN1A_VSYNC0_DELAYMODEVIN1A_VSYNC0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_VSYNC0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_VSYNC0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_VSYNC0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_VSYNC0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_VSYNC0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_VSYNC0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_VSYNC0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_VSYNC0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_VSYNC0_MUXMODERW0xF
0x0: vin1a_vsync0
0x1: vin1b_de1
0x4: vout3_vsync
0x5: uart7_rtsn
0x7: timer13
0x8: spi3_cs0
0xA: eQEP1_strobe
0xE: gpio3_3
0xF: Driver off
Table 18-614 CTRL_CORE_PAD_VIN1A_D0
Address Offset0x0000 14F4
Physical Address0x4A00 34F4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D0_WAKEUPEVENTVIN1A_D0_WAKEUPENABLERESERVEDVIN1A_D0_SLEWCONTROLVIN1A_D0_INPUTENABLEVIN1A_D0_PULLTYPESELECTVIN1A_D0_PULLUDENABLERESERVEDVIN1A_D0_MODESELECTVIN1A_D0_DELAYMODEVIN1A_D0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D0_MUXMODERW0xF
0x0: vin1a_d0
0x3: vout3_d7
0x4: vout3_d23
0x5: uart8_rxd
0xA: ehrpwm1A
0xE: gpio3_4
0xF: Driver off
Table 18-615 CTRL_CORE_PAD_VIN1A_D1
Address Offset0x0000 14F8
Physical Address0x4A00 34F8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D1_WAKEUPEVENTVIN1A_D1_WAKEUPENABLERESERVEDVIN1A_D1_SLEWCONTROLVIN1A_D1_INPUTENABLEVIN1A_D1_PULLTYPESELECTVIN1A_D1_PULLUDENABLERESERVEDVIN1A_D1_MODESELECTVIN1A_D1_DELAYMODEVIN1A_D1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D1_MUXMODERW0xF
0x0: vin1a_d1
0x3: vout3_d6
0x4: vout3_d22
0x5: uart8_txd
0xA: ehrpwm1B
0xE: gpio3_5
0xF: Driver off
Table 18-616 CTRL_CORE_PAD_VIN1A_D2
Address Offset0x0000 14FC
Physical Address0x4A00 34FCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D2_WAKEUPEVENTVIN1A_D2_WAKEUPENABLERESERVEDVIN1A_D2_SLEWCONTROLVIN1A_D2_INPUTENABLEVIN1A_D2_PULLTYPESELECTVIN1A_D2_PULLUDENABLERESERVEDVIN1A_D2_MODESELECTVIN1A_D2_DELAYMODEVIN1A_D2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D2_MUXMODERW0xF
0x0: vin1a_d2
0x3: vout3_d5
0x4: vout3_d21
0x5: uart8_ctsn
0xA: ehrpwm1_tripzone_input
0xE: gpio3_6
0xF: Driver off
Table 18-617 CTRL_CORE_PAD_VIN1A_D3
Address Offset0x0000 1500
Physical Address0x4A00 3500InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D3_WAKEUPEVENTVIN1A_D3_WAKEUPENABLERESERVEDVIN1A_D3_SLEWCONTROLVIN1A_D3_INPUTENABLEVIN1A_D3_PULLTYPESELECTVIN1A_D3_PULLUDENABLERESERVEDVIN1A_D3_MODESELECTVIN1A_D3_DELAYMODEVIN1A_D3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D3_MUXMODERW0xF
0x0: vin1a_d3
0x3: vout3_d4
0x4: vout3_d20
0x5: uart8_rtsn
0xA: eCAP1_in_PWM1_out
0xE: gpio3_7
0xF: Driver off
Table 18-618 CTRL_CORE_PAD_VIN1A_D4
Address Offset0x0000 1504
Physical Address0x4A00 3504InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D4_WAKEUPEVENTVIN1A_D4_WAKEUPENABLERESERVEDVIN1A_D4_SLEWCONTROLVIN1A_D4_INPUTENABLEVIN1A_D4_PULLTYPESELECTVIN1A_D4_PULLUDENABLERESERVEDVIN1A_D4_MODESELECTVIN1A_D4_DELAYMODEVIN1A_D4_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D4_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D4_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D4_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D4_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D4_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D4_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D4_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D4_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D4_MUXMODERW0xF
0x0: vin1a_d4
0x3: vout3_d3
0x4: vout3_d19
0xA: ehrpwm1_synci
0xE: gpio3_8
0xF: Driver off
Table 18-619 CTRL_CORE_PAD_VIN1A_D5
Address Offset0x0000 1508
Physical Address0x4A00 3508InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D5_WAKEUPEVENTVIN1A_D5_WAKEUPENABLERESERVEDVIN1A_D5_SLEWCONTROLVIN1A_D5_INPUTENABLEVIN1A_D5_PULLTYPESELECTVIN1A_D5_PULLUDENABLERESERVEDVIN1A_D5_MODESELECTVIN1A_D5_DELAYMODEVIN1A_D5_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D5_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D5_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D5_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D5_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D5_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D5_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D5_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D5_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D5_MUXMODERW0xF
0x0: vin1a_d5
0x3: vout3_d2
0x4: vout3_d18
0xA: ehrpwm1_synco
0xE: gpio3_9
0xF: Driver off
Table 18-620 CTRL_CORE_PAD_VIN1A_D6
Address Offset0x0000 150C
Physical Address0x4A00 350CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D6_WAKEUPEVENTVIN1A_D6_WAKEUPENABLERESERVEDVIN1A_D6_SLEWCONTROLVIN1A_D6_INPUTENABLEVIN1A_D6_PULLTYPESELECTVIN1A_D6_PULLUDENABLERESERVEDVIN1A_D6_MODESELECTVIN1A_D6_DELAYMODEVIN1A_D6_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D6_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D6_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D6_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D6_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D6_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D6_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D6_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D6_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D6_MUXMODERW0xF
0x0: vin1a_d6
0x3: vout3_d1
0x4: vout3_d17
0xA: eQEP2A_in
0xE: gpio3_10
0xF: Driver off
Table 18-621 CTRL_CORE_PAD_VIN1A_D7
Address Offset0x0000 1510
Physical Address0x4A00 3510InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D7_WAKEUPEVENTVIN1A_D7_WAKEUPENABLERESERVEDVIN1A_D7_SLEWCONTROLVIN1A_D7_INPUTENABLEVIN1A_D7_PULLTYPESELECTVIN1A_D7_PULLUDENABLERESERVEDVIN1A_D7_MODESELECTVIN1A_D7_DELAYMODEVIN1A_D7_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D7_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D7_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D7_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D7_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D7_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D7_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D7_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D7_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D7_MUXMODERW0xF
0x0: vin1a_d7
0x3: vout3_d0
0x4: vout3_d16
0xA: eQEP2B_in
0xE: gpio3_11
0xF: Driver off
Table 18-622 CTRL_CORE_PAD_VIN1A_D8
Address Offset0x0000 1514
Physical Address0x4A00 3514InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D8_WAKEUPEVENTVIN1A_D8_WAKEUPENABLERESERVEDVIN1A_D8_SLEWCONTROLVIN1A_D8_INPUTENABLEVIN1A_D8_PULLTYPESELECTVIN1A_D8_PULLUDENABLERESERVEDVIN1A_D8_MODESELECTVIN1A_D8_DELAYMODEVIN1A_D8_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D8_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D8_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D8_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D8_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D8_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D8_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D8_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D8_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D8_MUXMODERW0xF
0x0: vin1a_d8
0x1: vin1b_d7
0x4: vout3_d15
0x9: kbd_row2
0xA: eQEP2_index
0xE: gpio3_12
0xF: Driver off
Table 18-623 CTRL_CORE_PAD_VIN1A_D9
Address Offset0x0000 1518
Physical Address0x4A00 3518InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D9_WAKEUPEVENTVIN1A_D9_WAKEUPENABLERESERVEDVIN1A_D9_SLEWCONTROLVIN1A_D9_INPUTENABLEVIN1A_D9_PULLTYPESELECTVIN1A_D9_PULLUDENABLERESERVEDVIN1A_D9_MODESELECTVIN1A_D9_DELAYMODEVIN1A_D9_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D9_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D9_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D9_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D9_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D9_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D9_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D9_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D9_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D9_MUXMODERW0xF
0x0: vin1a_d9
0x1: vin1b_d6
0x4: vout3_d14
0x9: kbd_row3
0xA: eQEP2_strobe
0xE: gpio3_13
0xF: Driver off
Table 18-624 CTRL_CORE_PAD_VIN1A_D10
Address Offset0x0000 151C
Physical Address0x4A00 351CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D10_WAKEUPEVENTVIN1A_D10_WAKEUPENABLERESERVEDVIN1A_D10_SLEWCONTROLVIN1A_D10_INPUTENABLEVIN1A_D10_PULLTYPESELECTVIN1A_D10_PULLUDENABLERESERVEDVIN1A_D10_MODESELECTVIN1A_D10_DELAYMODEVIN1A_D10_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D10_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D10_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D10_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D10_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D10_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D10_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D10_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D10_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D10_MUXMODERW0xF
0x0: vin1a_d10
0x1: vin1b_d5
0x4: vout3_d13
0x9: kbd_row4
0xE: gpio3_14
0xF: Driver off
Table 18-625 CTRL_CORE_PAD_VIN1A_D11
Address Offset0x0000 1520
Physical Address0x4A00 3520InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D11_WAKEUPEVENTVIN1A_D11_WAKEUPENABLERESERVEDVIN1A_D11_SLEWCONTROLVIN1A_D11_INPUTENABLEVIN1A_D11_PULLTYPESELECTVIN1A_D11_PULLUDENABLERESERVEDVIN1A_D11_MODESELECTVIN1A_D11_DELAYMODEVIN1A_D11_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D11_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D11_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D11_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D11_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D11_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D11_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D11_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D11_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D11_MUXMODERW0xF
0x0: vin1a_d11
0x1: vin1b_d4
0x4: vout3_d12
0x5: gpmc_a23
0x9: kbd_row5
0xE: gpio3_15
0xF: Driver off
Table 18-626 CTRL_CORE_PAD_VIN1A_D12
Address Offset0x0000 1524
Physical Address0x4A00 3524InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D12_WAKEUPEVENTVIN1A_D12_WAKEUPENABLERESERVEDVIN1A_D12_SLEWCONTROLVIN1A_D12_INPUTENABLEVIN1A_D12_PULLTYPESELECTVIN1A_D12_PULLUDENABLERESERVEDVIN1A_D12_MODESELECTVIN1A_D12_DELAYMODEVIN1A_D12_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D12_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D12_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D12_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D12_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D12_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D12_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D12_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D12_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D12_MUXMODERW0xF
0x0: vin1a_d12
0x1: vin1b_d3
0x2: usb3_ulpi_d7
0x4: vout3_d11
0x5: gpmc_a24
0x9: kbd_row6
0xE: gpio3_16
0xF: Driver off
Table 18-627 CTRL_CORE_PAD_VIN1A_D13
Address Offset0x0000 1528
Physical Address0x4A00 3528InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D13_WAKEUPEVENTVIN1A_D13_WAKEUPENABLERESERVEDVIN1A_D13_SLEWCONTROLVIN1A_D13_INPUTENABLEVIN1A_D13_PULLTYPESELECTVIN1A_D13_PULLUDENABLERESERVEDVIN1A_D13_MODESELECTVIN1A_D13_DELAYMODEVIN1A_D13_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D13_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D13_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D13_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D13_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D13_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D13_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D13_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D13_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D13_MUXMODERW0xF
0x0: vin1a_d13
0x1: vin1b_d2
0x2: usb3_ulpi_d6
0x4: vout3_d10
0x5: gpmc_a25
0x9: kbd_row7
0xE: gpio3_17
0xF: Driver off
Table 18-628 CTRL_CORE_PAD_VIN1A_D14
Address Offset0x0000 152C
Physical Address0x4A00 352CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D14_WAKEUPEVENTVIN1A_D14_WAKEUPENABLERESERVEDVIN1A_D14_SLEWCONTROLVIN1A_D14_INPUTENABLEVIN1A_D14_PULLTYPESELECTVIN1A_D14_PULLUDENABLERESERVEDVIN1A_D14_MODESELECTVIN1A_D14_DELAYMODEVIN1A_D14_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D14_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D14_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D14_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D14_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D14_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D14_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D14_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D14_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D14_MUXMODERW0xF
0x0: vin1a_d14
0x1: vin1b_d1
0x2: usb3_ulpi_d5
0x4: vout3_d9
0x5: gpmc_a26
0x9: kbd_row8
0xE: gpio3_18
0xF: Driver off
Table 18-629 CTRL_CORE_PAD_VIN1A_D15
Address Offset0x0000 1530
Physical Address0x4A00 3530InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D15_WAKEUPEVENTVIN1A_D15_WAKEUPENABLERESERVEDVIN1A_D15_SLEWCONTROLVIN1A_D15_INPUTENABLEVIN1A_D15_PULLTYPESELECTVIN1A_D15_PULLUDENABLERESERVEDVIN1A_D15_MODESELECTVIN1A_D15_DELAYMODEVIN1A_D15_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D15_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D15_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D15_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D15_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D15_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D15_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D15_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D15_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D15_MUXMODERW0xF
0x0: vin1a_d15
0x1: vin1b_d0
0x2: usb3_ulpi_d4
0x4: vout3_d8
0x5: gpmc_a27
0x9: kbd_col0
0xE: gpio3_19
0xF: Driver off
Table 18-630 CTRL_CORE_PAD_VIN1A_D16
Address Offset0x0000 1534
Physical Address0x4A00 3534InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D16_WAKEUPEVENTVIN1A_D16_WAKEUPENABLERESERVEDVIN1A_D16_SLEWCONTROLVIN1A_D16_INPUTENABLEVIN1A_D16_PULLTYPESELECTVIN1A_D16_PULLUDENABLERESERVEDVIN1A_D16_MODESELECTVIN1A_D16_DELAYMODEVIN1A_D16_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D16_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D16_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D16_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D16_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D16_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D16_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D16_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D16_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D16_MUXMODERW0xF
0x0: vin1a_d16
0x1: vin1b_d7
0x2: usb3_ulpi_d3
0x4: vout3_d7
0x6: vin3a_d0
0x9: kbd_col1
0xE: gpio3_20
0xF: Driver off
Table 18-631 CTRL_CORE_PAD_VIN1A_D17
Address Offset0x0000 1538
Physical Address0x4A00 3538InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D17_WAKEUPEVENTVIN1A_D17_WAKEUPENABLERESERVEDVIN1A_D17_SLEWCONTROLVIN1A_D17_INPUTENABLEVIN1A_D17_PULLTYPESELECTVIN1A_D17_PULLUDENABLERESERVEDVIN1A_D17_MODESELECTVIN1A_D17_DELAYMODEVIN1A_D17_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D17_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D17_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D17_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D17_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D17_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D17_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D17_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D17_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D17_MUXMODERW0xF
0x0: vin1a_d17
0x1: vin1b_d6
0x2: usb3_ulpi_d2
0x4: vout3_d6
0x6: vin3a_d1
0x9: kbd_col2
0xE: gpio3_21
0xF: Driver off
Table 18-632 CTRL_CORE_PAD_VIN1A_D18
Address Offset0x0000 153C
Physical Address0x4A00 353CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D18_WAKEUPEVENTVIN1A_D18_WAKEUPENABLERESERVEDVIN1A_D18_SLEWCONTROLVIN1A_D18_INPUTENABLEVIN1A_D18_PULLTYPESELECTVIN1A_D18_PULLUDENABLERESERVEDVIN1A_D18_MODESELECTVIN1A_D18_DELAYMODEVIN1A_D18_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D18_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D18_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D18_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D18_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D18_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D18_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D18_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D18_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D18_MUXMODERW0xF
0x0: vin1a_d18
0x1: vin1b_d5
0x2: usb3_ulpi_d1
0x4: vout3_d5
0x6: vin3a_d2
0x9: kbd_col3
0xE: gpio3_22
0xF: Driver off
Table 18-633 CTRL_CORE_PAD_VIN1A_D19
Address Offset0x0000 1540
Physical Address0x4A00 3540InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D19_WAKEUPEVENTVIN1A_D19_WAKEUPENABLERESERVEDVIN1A_D19_SLEWCONTROLVIN1A_D19_INPUTENABLEVIN1A_D19_PULLTYPESELECTVIN1A_D19_PULLUDENABLERESERVEDVIN1A_D19_MODESELECTVIN1A_D19_DELAYMODEVIN1A_D19_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D19_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D19_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D19_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D19_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D19_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D19_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D19_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D19_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D19_MUXMODERW0xF
0x0: vin1a_d19
0x1: vin1b_d4
0x2: usb3_ulpi_d0
0x4: vout3_d4
0x6: vin3a_d3
0x9: kbd_col4
0xE: gpio3_23
0xF: Driver off
Table 18-634 CTRL_CORE_PAD_VIN1A_D20
Address Offset0x0000 1544
Physical Address0x4A00 3544InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D20_WAKEUPEVENTVIN1A_D20_WAKEUPENABLERESERVEDVIN1A_D20_SLEWCONTROLVIN1A_D20_INPUTENABLEVIN1A_D20_PULLTYPESELECTVIN1A_D20_PULLUDENABLERESERVEDVIN1A_D20_MODESELECTVIN1A_D20_DELAYMODEVIN1A_D20_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D20_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D20_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D20_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D20_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D20_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D20_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D20_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D20_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D20_MUXMODERW0xF
0x0: vin1a_d20
0x1: vin1b_d3
0x2: usb3_ulpi_nxt
0x4: vout3_d3
0x6: vin3a_d4
0x9: kbd_col5
0xE: gpio3_24
0xF: Driver off
Table 18-635 CTRL_CORE_PAD_VIN1A_D21
Address Offset0x0000 1548
Physical Address0x4A00 3548InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D21_WAKEUPEVENTVIN1A_D21_WAKEUPENABLERESERVEDVIN1A_D21_SLEWCONTROLVIN1A_D21_INPUTENABLEVIN1A_D21_PULLTYPESELECTVIN1A_D21_PULLUDENABLERESERVEDVIN1A_D21_MODESELECTVIN1A_D21_DELAYMODEVIN1A_D21_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D21_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D21_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D21_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D21_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D21_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D21_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D21_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D21_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D21_MUXMODERW0xF
0x0: vin1a_d21
0x1: vin1b_d2
0x2: usb3_ulpi_dir
0x4: vout3_d2
0x6: vin3a_d5
0x9: kbd_col6
0xE: gpio3_25
0xF: Driver off
Table 18-636 CTRL_CORE_PAD_VIN1A_D22
Address Offset0x0000 154C
Physical Address0x4A00 354CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D22_WAKEUPEVENTVIN1A_D22_WAKEUPENABLERESERVEDVIN1A_D22_SLEWCONTROLVIN1A_D22_INPUTENABLEVIN1A_D22_PULLTYPESELECTVIN1A_D22_PULLUDENABLERESERVEDVIN1A_D22_MODESELECTVIN1A_D22_DELAYMODEVIN1A_D22_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D22_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D22_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D22_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D22_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D22_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D22_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D22_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D22_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D22_MUXMODERW0xF
0x0: vin1a_d22
0x1: vin1b_d1
0x2: usb3_ulpi_stp
0x4: vout3_d1
0x6: vin3a_d6
0x9: kbd_col7
0xE: gpio3_26
0xF: Driver off
Table 18-637 CTRL_CORE_PAD_VIN1A_D23
Address Offset0x0000 1550
Physical Address0x4A00 3550InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN1A_D23_WAKEUPEVENTVIN1A_D23_WAKEUPENABLERESERVEDVIN1A_D23_SLEWCONTROLVIN1A_D23_INPUTENABLEVIN1A_D23_PULLTYPESELECTVIN1A_D23_PULLUDENABLERESERVEDVIN1A_D23_MODESELECTVIN1A_D23_DELAYMODEVIN1A_D23_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN1A_D23_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN1A_D23_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN1A_D23_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN1A_D23_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN1A_D23_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN1A_D23_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN1A_D23_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN1A_D23_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN1A_D23_MUXMODERW0xF
0x0: vin1a_d23
0x1: vin1b_d0
0x2: usb3_ulpi_clk
0x4: vout3_d0
0x6: vin3a_d7
0x9: kbd_col8
0xE: gpio3_27
0xF: Driver off
Table 18-638 CTRL_CORE_PAD_VIN2A_CLK0
Address Offset0x0000 1554
Physical Address0x4A00 3554InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_CLK0_WAKEUPEVENTVIN2A_CLK0_WAKEUPENABLERESERVEDVIN2A_CLK0_SLEWCONTROLVIN2A_CLK0_INPUTENABLEVIN2A_CLK0_PULLTYPESELECTVIN2A_CLK0_PULLUDENABLERESERVEDVIN2A_CLK0_MODESELECTVIN2A_CLK0_DELAYMODEVIN2A_CLK0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_CLK0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_CLK0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_CLK0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_CLK0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_CLK0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_CLK0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_CLK0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_CLK0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_CLK0_MUXMODERW0xF
0x0: vin2a_clk0
0x4: vout2_fld
0x5: emu5
0x9: kbd_row0
0xA: eQEP1A_in
0xE: gpio3_28
0xF: Driver off
Table 18-639 CTRL_CORE_PAD_VIN2A_DE0
Address Offset0x0000 1558
Physical Address0x4A00 3558InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_DE0_WAKEUPEVENTVIN2A_DE0_WAKEUPENABLERESERVEDVIN2A_DE0_SLEWCONTROLVIN2A_DE0_INPUTENABLEVIN2A_DE0_PULLTYPESELECTVIN2A_DE0_PULLUDENABLERESERVEDVIN2A_DE0_MODESELECTVIN2A_DE0_DELAYMODEVIN2A_DE0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_DE0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_DE0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_DE0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_DE0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_DE0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_DE0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_DE0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_DE0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_DE0_MUXMODERW0xF
0x0: vin2a_de0
0x1: vin2a_fld0
0x2: vin2b_fld1
0x3: vin2b_de1
0x4: vout2_de
0x5: emu6
0x9: kbd_row1
0xA: eQEP1B_in
0xE: gpio3_29
0xF: Driver off
Table 18-640 CTRL_CORE_PAD_VIN2A_FLD0
Address Offset0x0000 155C
Physical Address0x4A00 355CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_FLD0_WAKEUPEVENTVIN2A_FLD0_WAKEUPENABLERESERVEDVIN2A_FLD0_SLEWCONTROLVIN2A_FLD0_INPUTENABLEVIN2A_FLD0_PULLTYPESELECTVIN2A_FLD0_PULLUDENABLERESERVEDVIN2A_FLD0_MODESELECTVIN2A_FLD0_DELAYMODEVIN2A_FLD0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_FLD0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_FLD0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_FLD0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_FLD0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_FLD0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_FLD0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_FLD0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_FLD0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_FLD0_MUXMODERW0xF
0x0: vin2a_fld0
0x2: vin2b_clk1
0x4: vout2_clk
0x5: emu7
0xA: eQEP1_index
0xE: gpio3_30
0xF: Driver off
Table 18-641 CTRL_CORE_PAD_VIN2A_HSYNC0
Address Offset0x0000 1560
Physical Address0x4A00 3560InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_HSYNC0_WAKEUPEVENTVIN2A_HSYNC0_WAKEUPENABLERESERVEDVIN2A_HSYNC0_SLEWCONTROLVIN2A_HSYNC0_INPUTENABLEVIN2A_HSYNC0_PULLTYPESELECTVIN2A_HSYNC0_PULLUDENABLERESERVEDVIN2A_HSYNC0_MODESELECTVIN2A_HSYNC0_DELAYMODEVIN2A_HSYNC0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_HSYNC0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_HSYNC0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_HSYNC0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_HSYNC0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_HSYNC0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_HSYNC0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_HSYNC0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_HSYNC0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_HSYNC0_MUXMODERW0xF
0x0: vin2a_hsync0
0x3: vin2b_hsync1
0x4: vout2_hsync
0x5: emu8
0x7: uart9_rxd
0x8: spi4_sclk
0x9: kbd_row2
0xA: eQEP1_strobe
0xE: gpio3_31
0xF: Driver off
Table 18-642 CTRL_CORE_PAD_VIN2A_VSYNC0
Address Offset0x0000 1564
Physical Address0x4A00 3564InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_VSYNC0_WAKEUPEVENTVIN2A_VSYNC0_WAKEUPENABLERESERVEDVIN2A_VSYNC0_SLEWCONTROLVIN2A_VSYNC0_INPUTENABLEVIN2A_VSYNC0_PULLTYPESELECTVIN2A_VSYNC0_PULLUDENABLERESERVEDVIN2A_VSYNC0_MODESELECTVIN2A_VSYNC0_DELAYMODEVIN2A_VSYNC0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_VSYNC0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_VSYNC0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_VSYNC0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_VSYNC0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_VSYNC0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_VSYNC0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_VSYNC0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_VSYNC0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_VSYNC0_MUXMODERW0xF
0x0: vin2a_vsync0
0x3: vin2b_vsync1
0x4: vout2_vsync
0x5: emu9
0x7: uart9_txd
0x8: spi4_d1
0x9: kbd_row3
0xA: ehrpwm1A
0xE: gpio4_0
0xF: Driver off
Table 18-643 CTRL_CORE_PAD_VIN2A_D0
Address Offset0x0000 1568
Physical Address0x4A00 3568InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D0_WAKEUPEVENTVIN2A_D0_WAKEUPENABLERESERVEDVIN2A_D0_SLEWCONTROLVIN2A_D0_INPUTENABLEVIN2A_D0_PULLTYPESELECTVIN2A_D0_PULLUDENABLERESERVEDVIN2A_D0_MODESELECTVIN2A_D0_DELAYMODEVIN2A_D0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D0_MUXMODERW0xF
0x0: vin2a_d0
0x4: vout2_d23
0x5: emu10
0x7: uart9_ctsn
0x8: spi4_d0
0x9: kbd_row4
0xA: ehrpwm1B
0xE: gpio4_1
0xF: Driver off
Table 18-644 CTRL_CORE_PAD_VIN2A_D1
Address Offset0x0000 156C
Physical Address0x4A00 356CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D1_WAKEUPEVENTVIN2A_D1_WAKEUPENABLERESERVEDVIN2A_D1_SLEWCONTROLVIN2A_D1_INPUTENABLEVIN2A_D1_PULLTYPESELECTVIN2A_D1_PULLUDENABLERESERVEDVIN2A_D1_MODESELECTVIN2A_D1_DELAYMODEVIN2A_D1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D1_MUXMODERW0xF
0x0: vin2a_d1
0x4: vout2_d22
0x5: emu11
0x7: uart9_rtsn
0x8: spi4_cs0
0x9: kbd_row5
0xA: ehrpwm1_tripzone_input
0xE: gpio4_2
0xF: Driver off
Table 18-645 CTRL_CORE_PAD_VIN2A_D2
Address Offset0x0000 1570
Physical Address0x4A00 3570InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D2_WAKEUPEVENTVIN2A_D2_WAKEUPENABLERESERVEDVIN2A_D2_SLEWCONTROLVIN2A_D2_INPUTENABLEVIN2A_D2_PULLTYPESELECTVIN2A_D2_PULLUDENABLERESERVEDVIN2A_D2_MODESELECTVIN2A_D2_DELAYMODEVIN2A_D2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D2_MUXMODERW0xF
0x0: vin2a_d2
0x4: vout2_d21
0x5: emu12
0x8: uart10_rxd
0x9: kbd_row6
0xA: eCAP1_in_PWM1_out
0xE: gpio4_3
0xF: Driver off
Table 18-646 CTRL_CORE_PAD_VIN2A_D3
Address Offset0x0000 1574
Physical Address0x4A00 3574InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D3_WAKEUPEVENTVIN2A_D3_WAKEUPENABLERESERVEDVIN2A_D3_SLEWCONTROLVIN2A_D3_INPUTENABLEVIN2A_D3_PULLTYPESELECTVIN2A_D3_PULLUDENABLERESERVEDVIN2A_D3_MODESELECTVIN2A_D3_DELAYMODEVIN2A_D3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D3_MUXMODERW0xF
0x0: vin2a_d3
0x4: vout2_d20
0x5: emu13
0x8: uart10_txd
0x9: kbd_col0
0xA: ehrpwm1_synci
0xE: gpio4_4
0xF: Driver off
Table 18-647 CTRL_CORE_PAD_VIN2A_D4
Address Offset0x0000 1578
Physical Address0x4A00 3578InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D4_WAKEUPEVENTVIN2A_D4_WAKEUPENABLERESERVEDVIN2A_D4_SLEWCONTROLVIN2A_D4_INPUTENABLEVIN2A_D4_PULLTYPESELECTVIN2A_D4_PULLUDENABLERESERVEDVIN2A_D4_MODESELECTVIN2A_D4_DELAYMODEVIN2A_D4_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D4_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D4_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D4_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D4_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D4_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D4_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D4_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D4_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D4_MUXMODERW0xF
0x0: vin2a_d4
0x4: vout2_d19
0x5: emu14
0x8: uart10_ctsn
0x9: kbd_col1
0xA: ehrpwm1_synco
0xE: gpio4_5
0xF: Driver off
Table 18-648 CTRL_CORE_PAD_VIN2A_D5
Address Offset0x0000 157C
Physical Address0x4A00 357CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D5_WAKEUPEVENTVIN2A_D5_WAKEUPENABLERESERVEDVIN2A_D5_SLEWCONTROLVIN2A_D5_INPUTENABLEVIN2A_D5_PULLTYPESELECTVIN2A_D5_PULLUDENABLERESERVEDVIN2A_D5_MODESELECTVIN2A_D5_DELAYMODEVIN2A_D5_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D5_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D5_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D5_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D5_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D5_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D5_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D5_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D5_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D5_MUXMODERW0xF
0x0: vin2a_d5
0x4: vout2_d18
0x5: emu15
0x8: uart10_rtsn
0x9: kbd_col2
0xA: eQEP2A_in
0xE: gpio4_6
0xF: Driver off
Table 18-649 CTRL_CORE_PAD_VIN2A_D6
Address Offset0x0000 1580
Physical Address0x4A00 3580InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D6_WAKEUPEVENTVIN2A_D6_WAKEUPENABLERESERVEDVIN2A_D6_SLEWCONTROLVIN2A_D6_INPUTENABLEVIN2A_D6_PULLTYPESELECTVIN2A_D6_PULLUDENABLERESERVEDVIN2A_D6_MODESELECTVIN2A_D6_DELAYMODEVIN2A_D6_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D6_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D6_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D6_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D6_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D6_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D6_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D6_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D6_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D6_MUXMODERW0xF
0x0: vin2a_d6
0x4: vout2_d17
0x5: emu16
0x8: mii1_rxd1
0x9: kbd_col3
0xA: eQEP2B_in
0xE: gpio4_7
0xF: Driver off
Table 18-650 CTRL_CORE_PAD_VIN2A_D7
Address Offset0x0000 1584
Physical Address0x4A00 3584InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D7_WAKEUPEVENTVIN2A_D7_WAKEUPENABLERESERVEDVIN2A_D7_SLEWCONTROLVIN2A_D7_INPUTENABLEVIN2A_D7_PULLTYPESELECTVIN2A_D7_PULLUDENABLERESERVEDVIN2A_D7_MODESELECTVIN2A_D7_DELAYMODEVIN2A_D7_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D7_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D7_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D7_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D7_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D7_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D7_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D7_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D7_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D7_MUXMODERW0xF
0x0: vin2a_d7
0x4: vout2_d16
0x5: emu17
0x8: mii1_rxd2
0x9: kbd_col4
0xA: eQEP2_index
0xE: gpio4_8
0xF: Driver off
Table 18-651 CTRL_CORE_PAD_VIN2A_D8
Address Offset0x0000 1588
Physical Address0x4A00 3588InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D8_WAKEUPEVENTVIN2A_D8_WAKEUPENABLERESERVEDVIN2A_D8_SLEWCONTROLVIN2A_D8_INPUTENABLEVIN2A_D8_PULLTYPESELECTVIN2A_D8_PULLUDENABLERESERVEDVIN2A_D8_MODESELECTVIN2A_D8_DELAYMODEVIN2A_D8_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D8_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D8_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D8_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D8_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D8_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D8_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D8_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D8_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D8_MUXMODERW0xF
0x0: vin2a_d8
0x4: vout2_d15
0x5: emu18
0x8: mii1_rxd3
0x9: kbd_col5
0xA: eQEP2_strobe
0xE: gpio4_9
0xF: Driver off
Table 18-652 CTRL_CORE_PAD_VIN2A_D9
Address Offset0x0000 158C
Physical Address0x4A00 358CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D9_WAKEUPEVENTVIN2A_D9_WAKEUPENABLERESERVEDVIN2A_D9_SLEWCONTROLVIN2A_D9_INPUTENABLEVIN2A_D9_PULLTYPESELECTVIN2A_D9_PULLUDENABLERESERVEDVIN2A_D9_MODESELECTVIN2A_D9_DELAYMODEVIN2A_D9_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D9_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D9_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D9_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D9_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D9_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D9_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D9_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D9_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D9_MUXMODERW0xF
0x0: vin2a_d9
0x4: vout2_d14
0x5: emu19
0x8: mii1_rxd0
0x9: kbd_col6
0xA: ehrpwm2A
0xE: gpio4_10
0xF: Driver off
Table 18-653 CTRL_CORE_PAD_VIN2A_D10
Address Offset0x0000 1590
Physical Address0x4A00 3590InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D10_WAKEUPEVENTVIN2A_D10_WAKEUPENABLERESERVEDVIN2A_D10_SLEWCONTROLVIN2A_D10_INPUTENABLEVIN2A_D10_PULLTYPESELECTVIN2A_D10_PULLUDENABLERESERVEDVIN2A_D10_MODESELECTVIN2A_D10_DELAYMODEVIN2A_D10_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D10_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D10_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D10_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D10_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D10_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D10_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D10_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D10_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D10_MUXMODERW0xF
0x0: vin2a_d10
0x3: mdio_mclk
0x4: vout2_d13
0x9: kbd_col7
0xA: ehrpwm2B
0xE: gpio4_11
0xF: Driver off
Table 18-654 CTRL_CORE_PAD_VIN2A_D11
Address Offset0x0000 1594
Physical Address0x4A00 3594InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D11_WAKEUPEVENTVIN2A_D11_WAKEUPENABLERESERVEDVIN2A_D11_SLEWCONTROLVIN2A_D11_INPUTENABLEVIN2A_D11_PULLTYPESELECTVIN2A_D11_PULLUDENABLERESERVEDVIN2A_D11_MODESELECTVIN2A_D11_DELAYMODEVIN2A_D11_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D11_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D11_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D11_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D11_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D11_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D11_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D11_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D11_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D11_MUXMODERW0xF
0x0: vin2a_d11
0x3: mdio_d
0x4: vout2_d12
0x9: kbd_row7
0xA: ehrpwm2_tripzone_input
0xE: gpio4_12
0xF: Driver off
Table 18-655 CTRL_CORE_PAD_VIN2A_D12
Address Offset0x0000 1598
Physical Address0x4A00 3598InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D12_WAKEUPEVENTVIN2A_D12_WAKEUPENABLERESERVEDVIN2A_D12_SLEWCONTROLVIN2A_D12_INPUTENABLEVIN2A_D12_PULLTYPESELECTVIN2A_D12_PULLUDENABLERESERVEDVIN2A_D12_MODESELECTVIN2A_D12_DELAYMODEVIN2A_D12_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D12_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D12_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D12_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D12_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D12_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D12_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D12_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D12_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D12_MUXMODERW0xF
0x0: vin2a_d12
0x3: rgmii1_txc
0x4: vout2_d11
0x8: mii1_rxclk
0x9: kbd_col8
0xA: eCAP2_in_PWM2_out
0xE: gpio4_13
0xF: Driver off
Table 18-656 CTRL_CORE_PAD_VIN2A_D13
Address Offset0x0000 159C
Physical Address0x4A00 359CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D13_WAKEUPEVENTVIN2A_D13_WAKEUPENABLERESERVEDVIN2A_D13_SLEWCONTROLVIN2A_D13_INPUTENABLEVIN2A_D13_PULLTYPESELECTVIN2A_D13_PULLUDENABLERESERVEDVIN2A_D13_MODESELECTVIN2A_D13_DELAYMODEVIN2A_D13_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D13_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D13_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D13_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D13_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D13_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D13_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D13_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D13_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D13_MUXMODERW0xF
0x0: vin2a_d13
0x3: rgmii1_txctl
0x4: vout2_d10
0x8: mii1_rxdv
0x9: kbd_row8
0xA: eQEP3A_in
0xE: gpio4_14
0xF: Driver off
Table 18-657 CTRL_CORE_PAD_VIN2A_D14
Address Offset0x0000 15A0
Physical Address0x4A00 35A0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D14_WAKEUPEVENTVIN2A_D14_WAKEUPENABLERESERVEDVIN2A_D14_SLEWCONTROLVIN2A_D14_INPUTENABLEVIN2A_D14_PULLTYPESELECTVIN2A_D14_PULLUDENABLERESERVEDVIN2A_D14_MODESELECTVIN2A_D14_DELAYMODEVIN2A_D14_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D14_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D14_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D14_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D14_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D14_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D14_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D14_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D14_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D14_MUXMODERW0xF
0x0: vin2a_d14
0x3: rgmii1_txd3
0x4: vout2_d9
0x8: mii1_txclk
0xA: eQEP3B_in
0xE: gpio4_15
0xF: Driver off
Table 18-658 CTRL_CORE_PAD_VIN2A_D15
Address Offset0x0000 15A4
Physical Address0x4A00 35A4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D15_WAKEUPEVENTVIN2A_D15_WAKEUPENABLERESERVEDVIN2A_D15_SLEWCONTROLVIN2A_D15_INPUTENABLEVIN2A_D15_PULLTYPESELECTVIN2A_D15_PULLUDENABLERESERVEDVIN2A_D15_MODESELECTVIN2A_D15_DELAYMODEVIN2A_D15_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D15_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D15_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D15_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D15_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D15_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D15_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D15_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D15_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D15_MUXMODERW0xF
0x0: vin2a_d15
0x3: rgmii1_txd2
0x4: vout2_d8
0x8: mii1_txd0
0xA: eQEP3_index
0xE: gpio4_16
0xF: Driver off
Table 18-659 CTRL_CORE_PAD_VIN2A_D16
Address Offset0x0000 15A8
Physical Address0x4A00 35A8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D16_WAKEUPEVENTVIN2A_D16_WAKEUPENABLERESERVEDVIN2A_D16_SLEWCONTROLVIN2A_D16_INPUTENABLEVIN2A_D16_PULLTYPESELECTVIN2A_D16_PULLUDENABLERESERVEDVIN2A_D16_MODESELECTVIN2A_D16_DELAYMODEVIN2A_D16_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D16_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D16_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D16_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D16_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D16_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D16_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D16_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D16_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D16_MUXMODERW0xF
0x0: vin2a_d16
0x2: vin2b_d7
0x3: rgmii1_txd1
0x4: vout2_d7
0x6: vin3a_d8
0x8: mii1_txd1
0xA: eQEP3_strobe
0xE: gpio4_24
0xF: Driver off
Table 18-660 CTRL_CORE_PAD_VIN2A_D17
Address Offset0x0000 15AC
Physical Address0x4A00 35ACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D17_WAKEUPEVENTVIN2A_D17_WAKEUPENABLERESERVEDVIN2A_D17_SLEWCONTROLVIN2A_D17_INPUTENABLEVIN2A_D17_PULLTYPESELECTVIN2A_D17_PULLUDENABLERESERVEDVIN2A_D17_MODESELECTVIN2A_D17_DELAYMODEVIN2A_D17_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D17_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D17_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D17_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D17_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D17_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D17_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D17_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D17_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D17_MUXMODERW0xF
0x0: vin2a_d17
0x2: vin2b_d6
0x3: rgmii1_txd0
0x4: vout2_d6
0x6: vin3a_d9
0x8: mii1_txd2
0xA: ehrpwm3A
0xE: gpio4_25
0xF: Driver off
Table 18-661 CTRL_CORE_PAD_VIN2A_D18
Address Offset0x0000 15B0
Physical Address0x4A00 35B0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D18_WAKEUPEVENTVIN2A_D18_WAKEUPENABLERESERVEDVIN2A_D18_SLEWCONTROLVIN2A_D18_INPUTENABLEVIN2A_D18_PULLTYPESELECTVIN2A_D18_PULLUDENABLERESERVEDVIN2A_D18_MODESELECTVIN2A_D18_DELAYMODEVIN2A_D18_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D18_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D18_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D18_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D18_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D18_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D18_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D18_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D18_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D18_MUXMODERW0xF
0x0: vin2a_d18
0x2: vin2b_d5
0x3: rgmii1_rxc
0x4: vout2_d5
0x6: vin3a_d10
0x8: mii1_txd3
0xA: ehrpwm3B
0xE: gpio4_26
0xF: Driver off
Table 18-662 CTRL_CORE_PAD_VIN2A_D19
Address Offset0x0000 15B4
Physical Address0x4A00 35B4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D19_WAKEUPEVENTVIN2A_D19_WAKEUPENABLERESERVEDVIN2A_D19_SLEWCONTROLVIN2A_D19_INPUTENABLEVIN2A_D19_PULLTYPESELECTVIN2A_D19_PULLUDENABLERESERVEDVIN2A_D19_MODESELECTVIN2A_D19_DELAYMODEVIN2A_D19_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D19_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D19_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D19_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D19_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D19_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D19_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D19_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D19_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D19_MUXMODERW0xF
0x0: vin2a_d19
0x2: vin2b_d4
0x3: rgmii1_rxctl
0x4: vout2_d4
0x6: vin3a_d11
0x8: mii1_txer
0xA: ehrpwm3_tripzone_input
0xE: gpio4_27
0xF: Driver off
Table 18-663 CTRL_CORE_PAD_VIN2A_D20
Address Offset0x0000 15B8
Physical Address0x4A00 35B8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D20_WAKEUPEVENTVIN2A_D20_WAKEUPENABLERESERVEDVIN2A_D20_SLEWCONTROLVIN2A_D20_INPUTENABLEVIN2A_D20_PULLTYPESELECTVIN2A_D20_PULLUDENABLERESERVEDVIN2A_D20_MODESELECTVIN2A_D20_DELAYMODEVIN2A_D20_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D20_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D20_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D20_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D20_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D20_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D20_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D20_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D20_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D20_MUXMODERW0xF
0x0: vin2a_d20
0x2: vin2b_d3
0x3: rgmii1_rxd3
0x4: vout2_d3
0x5: vin3a_de0
0x6: vin3a_d12
0x8: mii1_rxer
0xA: eCAP3_in_PWM3_out
0xE: gpio4_28
0xF: Driver off
Table 18-664 CTRL_CORE_PAD_VIN2A_D21
Address Offset0x0000 15BC
Physical Address0x4A00 35BCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D21_WAKEUPEVENTVIN2A_D21_WAKEUPENABLERESERVEDVIN2A_D21_SLEWCONTROLVIN2A_D21_INPUTENABLEVIN2A_D21_PULLTYPESELECTVIN2A_D21_PULLUDENABLERESERVEDVIN2A_D21_MODESELECTVIN2A_D21_DELAYMODEVIN2A_D21_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D21_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D21_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D21_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D21_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D21_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D21_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D21_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D21_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D21_MUXMODERW0xF
0x0: vin2a_d21
0x2: vin2b_d2
0x3: rgmii1_rxd2
0x4: vout2_d2
0x5: vin3a_fld0
0x6: vin3a_d13
0x8: mii1_col
0xE: gpio4_29
0xF: Driver off
Table 18-665 CTRL_CORE_PAD_VIN2A_D22
Address Offset0x0000 15C0
Physical Address0x4A00 35C0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D22_WAKEUPEVENTVIN2A_D22_WAKEUPENABLERESERVEDVIN2A_D22_SLEWCONTROLVIN2A_D22_INPUTENABLEVIN2A_D22_PULLTYPESELECTVIN2A_D22_PULLUDENABLERESERVEDVIN2A_D22_MODESELECTVIN2A_D22_DELAYMODEVIN2A_D22_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D22_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D22_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D22_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D22_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D22_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D22_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D22_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D22_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D22_MUXMODERW0xF
0x0: vin2a_d22
0x2: vin2b_d1
0x3: rgmii1_rxd1
0x4: vout2_d1
0x5: vin3a_hsync0
0x6: vin3a_d14
0x8: mii1_crs
0xE: gpio4_30
0xF: Driver off
Table 18-666 CTRL_CORE_PAD_VIN2A_D23
Address Offset0x0000 15C4
Physical Address0x4A00 35C4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVIN2A_D23_WAKEUPEVENTVIN2A_D23_WAKEUPENABLERESERVEDVIN2A_D23_SLEWCONTROLVIN2A_D23_INPUTENABLEVIN2A_D23_PULLTYPESELECTVIN2A_D23_PULLUDENABLERESERVEDVIN2A_D23_MODESELECTVIN2A_D23_DELAYMODEVIN2A_D23_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VIN2A_D23_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VIN2A_D23_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VIN2A_D23_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VIN2A_D23_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VIN2A_D23_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VIN2A_D23_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VIN2A_D23_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VIN2A_D23_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VIN2A_D23_MUXMODERW0xF
0x0: vin2a_d23
0x2: vin2b_d0
0x3: rgmii1_rxd0
0x4: vout2_d0
0x5: vin3a_vsync0
0x6: vin3a_d15
0x8: mii1_txen
0xE: gpio4_31
0xF: Driver off
Table 18-667 CTRL_CORE_PAD_VOUT1_CLK
Address Offset0x0000 15C8
Physical Address0x4A00 35C8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_CLK_WAKEUPEVENTVOUT1_CLK_WAKEUPENABLERESERVEDVOUT1_CLK_SLEWCONTROLVOUT1_CLK_INPUTENABLEVOUT1_CLK_PULLTYPESELECTVOUT1_CLK_PULLUDENABLERESERVEDVOUT1_CLK_MODESELECTVOUT1_CLK_DELAYMODEVOUT1_CLK_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_CLK_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_CLK_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_CLK_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_CLK_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_CLK_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_CLK_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_CLK_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_CLK_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_CLK_MUXMODERW0xF
0x0: vout1_clk
0x3: vin4a_fld0
0x4: vin3a_fld0
0x8: spi3_cs0
0xE: gpio4_19
0xF: Driver off
Table 18-668 CTRL_CORE_PAD_VOUT1_DE
Address Offset0x0000 15CC
Physical Address0x4A00 35CCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_DE_WAKEUPEVENTVOUT1_DE_WAKEUPENABLERESERVEDVOUT1_DE_SLEWCONTROLVOUT1_DE_INPUTENABLEVOUT1_DE_PULLTYPESELECTVOUT1_DE_PULLUDENABLERESERVEDVOUT1_DE_MODESELECTVOUT1_DE_DELAYMODEVOUT1_DE_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_DE_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_DE_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_DE_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_DE_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_DE_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_DE_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_DE_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_DE_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_DE_MUXMODERW0xF
0x0: vout1_de
0x3: vin4a_de0
0x4: vin3a_de0
0x8: spi3_d1
0xE: gpio4_20
0xF: Driver off
Table 18-669 CTRL_CORE_PAD_VOUT1_FLD
Address Offset0x0000 15D0
Physical Address0x4A00 35D0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_FLD_WAKEUPEVENTVOUT1_FLD_WAKEUPENABLERESERVEDVOUT1_FLD_SLEWCONTROLVOUT1_FLD_INPUTENABLEVOUT1_FLD_PULLTYPESELECTVOUT1_FLD_PULLUDENABLERESERVEDVOUT1_FLD_MODESELECTVOUT1_FLD_DELAYMODEVOUT1_FLD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_FLD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_FLD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_FLD_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_FLD_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_FLD_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_FLD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_FLD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_FLD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_FLD_MUXMODERW0xF
0x0: vout1_fld
0x3: vin4a_clk0
0x4: vin3a_clk0
0x8: spi3_cs1
0xE: gpio4_21
0xF: Driver off
Table 18-670 CTRL_CORE_PAD_VOUT1_HSYNC
Address Offset0x0000 15D4
Physical Address0x4A00 35D4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_HSYNC_WAKEUPEVENTVOUT1_HSYNC_WAKEUPENABLERESERVEDVOUT1_HSYNC_SLEWCONTROLVOUT1_HSYNC_INPUTENABLEVOUT1_HSYNC_PULLTYPESELECTVOUT1_HSYNC_PULLUDENABLERESERVEDVOUT1_HSYNC_MODESELECTVOUT1_HSYNC_DELAYMODEVOUT1_HSYNC_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_HSYNC_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_HSYNC_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_HSYNC_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_HSYNC_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_HSYNC_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_HSYNC_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_HSYNC_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_HSYNC_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_HSYNC_MUXMODERW0xF
0x0: vout1_hsync
0x3: vin4a_hsync0
0x4: vin3a_hsync0
0x8: spi3_d0
0xE: gpio4_22
0xF: Driver off
Table 18-671 CTRL_CORE_PAD_VOUT1_VSYNC
Address Offset0x0000 15D8
Physical Address0x4A00 35D8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_VSYNC_WAKEUPEVENTVOUT1_VSYNC_WAKEUPENABLERESERVEDVOUT1_VSYNC_SLEWCONTROLVOUT1_VSYNC_INPUTENABLEVOUT1_VSYNC_PULLTYPESELECTVOUT1_VSYNC_PULLUDENABLERESERVEDVOUT1_VSYNC_MODESELECTVOUT1_VSYNC_DELAYMODEVOUT1_VSYNC_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_VSYNC_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_VSYNC_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_VSYNC_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_VSYNC_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_VSYNC_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_VSYNC_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_VSYNC_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_VSYNC_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_VSYNC_MUXMODERW0xF
0x0: vout1_vsync
0x3: vin4a_vsync0
0x4: vin3a_vsync0
0x8: spi3_sclk
0xE: gpio4_23
0xF: Driver off
Table 18-672 CTRL_CORE_PAD_VOUT1_D0
Address Offset0x0000 15DC
Physical Address0x4A00 35DCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D0_WAKEUPEVENTVOUT1_D0_WAKEUPENABLERESERVEDVOUT1_D0_SLEWCONTROLVOUT1_D0_INPUTENABLEVOUT1_D0_PULLTYPESELECTVOUT1_D0_PULLUDENABLERESERVEDVOUT1_D0_MODESELECTVOUT1_D0_DELAYMODEVOUT1_D0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D0_MUXMODERW0xF
0x0: vout1_d0
0x2: uart5_rxd
0x3: vin4a_d16
0x4: vin3a_d16
0x8: spi3_cs2
0xE: gpio8_0
0xF: Driver off
Table 18-673 CTRL_CORE_PAD_VOUT1_D1
Address Offset0x0000 15E0
Physical Address0x4A00 35E0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D1_WAKEUPEVENTVOUT1_D1_WAKEUPENABLERESERVEDVOUT1_D1_SLEWCONTROLVOUT1_D1_INPUTENABLEVOUT1_D1_PULLTYPESELECTVOUT1_D1_PULLUDENABLERESERVEDVOUT1_D1_MODESELECTVOUT1_D1_DELAYMODEVOUT1_D1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D1_MUXMODERW0xF
0x0: vout1_d1
0x2: uart5_txd
0x3: vin4a_d17
0x4: vin3a_d17
0xE: gpio8_1
0xF: Driver off
Table 18-674 CTRL_CORE_PAD_VOUT1_D2
Address Offset0x0000 15E4
Physical Address0x4A00 35E4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D2_WAKEUPEVENTVOUT1_D2_WAKEUPENABLERESERVEDVOUT1_D2_SLEWCONTROLVOUT1_D2_INPUTENABLEVOUT1_D2_PULLTYPESELECTVOUT1_D2_PULLUDENABLERESERVEDVOUT1_D2_MODESELECTVOUT1_D2_DELAYMODEVOUT1_D2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D2_MUXMODERW0xF
0x0: vout1_d2
0x2: emu2
0x3: vin4a_d18
0x4: vin3a_d18
0x5: obs0
0x6: obs16
0x7: obs_irq1
0xE: gpio8_2
0xF: Driver off
Table 18-675 CTRL_CORE_PAD_VOUT1_D3
Address Offset0x0000 15E8
Physical Address0x4A00 35E8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D3_WAKEUPEVENTVOUT1_D3_WAKEUPENABLERESERVEDVOUT1_D3_SLEWCONTROLVOUT1_D3_INPUTENABLEVOUT1_D3_PULLTYPESELECTVOUT1_D3_PULLUDENABLERESERVEDVOUT1_D3_MODESELECTVOUT1_D3_DELAYMODEVOUT1_D3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D3_MUXMODERW0xF
0x0: vout1_d3
0x2: emu5
0x3: vin4a_d19
0x4: vin3a_d19
0x5: obs1
0x6: obs17
0x7: obs_dmarq1
0xE: gpio8_3
0xF: Driver off
Table 18-676 CTRL_CORE_PAD_VOUT1_D4
Address Offset0x0000 15EC
Physical Address0x4A00 35ECInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D4_WAKEUPEVENTVOUT1_D4_WAKEUPENABLERESERVEDVOUT1_D4_SLEWCONTROLVOUT1_D4_INPUTENABLEVOUT1_D4_PULLTYPESELECTVOUT1_D4_PULLUDENABLERESERVEDVOUT1_D4_MODESELECTVOUT1_D4_DELAYMODEVOUT1_D4_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D4_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D4_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D4_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D4_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D4_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D4_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D4_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D4_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D4_MUXMODERW0xF
0x0: vout1_d4
0x2: emu6
0x3: vin4a_d20
0x4: vin3a_d20
0x5: obs2
0x6: obs18
0xE: gpio8_4
0xF: Driver off
Table 18-677 CTRL_CORE_PAD_VOUT1_D5
Address Offset0x0000 15F0
Physical Address0x4A00 35F0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D5_WAKEUPEVENTVOUT1_D5_WAKEUPENABLERESERVEDVOUT1_D5_SLEWCONTROLVOUT1_D5_INPUTENABLEVOUT1_D5_PULLTYPESELECTVOUT1_D5_PULLUDENABLERESERVEDVOUT1_D5_MODESELECTVOUT1_D5_DELAYMODEVOUT1_D5_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D5_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D5_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D5_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D5_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D5_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D5_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D5_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D5_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D5_MUXMODERW0xF
0x0: vout1_d5
0x2: emu7
0x3: vin4a_d21
0x4: vin3a_d21
0x5: obs3
0x6: obs19
0xE: gpio8_5
0xF: Driver off
Table 18-678 CTRL_CORE_PAD_VOUT1_D6
Address Offset0x0000 15F4
Physical Address0x4A00 35F4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D6_WAKEUPEVENTVOUT1_D6_WAKEUPENABLERESERVEDVOUT1_D6_SLEWCONTROLVOUT1_D6_INPUTENABLEVOUT1_D6_PULLTYPESELECTVOUT1_D6_PULLUDENABLERESERVEDVOUT1_D6_MODESELECTVOUT1_D6_DELAYMODEVOUT1_D6_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D6_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D6_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D6_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D6_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D6_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D6_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D6_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D6_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D6_MUXMODERW0xF
0x0: vout1_d6
0x2: emu8
0x3: vin4a_d22
0x4: vin3a_d22
0x5: obs4
0x6: obs20
0xE: gpio8_6
0xF: Driver off
Table 18-679 CTRL_CORE_PAD_VOUT1_D7
Address Offset0x0000 15F8
Physical Address0x4A00 35F8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D7_WAKEUPEVENTVOUT1_D7_WAKEUPENABLERESERVEDVOUT1_D7_SLEWCONTROLVOUT1_D7_INPUTENABLEVOUT1_D7_PULLTYPESELECTVOUT1_D7_PULLUDENABLERESERVEDVOUT1_D7_MODESELECTVOUT1_D7_DELAYMODEVOUT1_D7_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D7_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D7_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D7_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D7_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D7_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D7_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D7_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D7_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D7_MUXMODERW0xF
0x0: vout1_d7
0x2: emu9
0x3: vin4a_d23
0x4: vin3a_d23
0xE: gpio8_7
0xF: Driver off
Table 18-680 CTRL_CORE_PAD_VOUT1_D8
Address Offset0x0000 15FC
Physical Address0x4A00 35FCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D8_WAKEUPEVENTVOUT1_D8_WAKEUPENABLERESERVEDVOUT1_D8_SLEWCONTROLVOUT1_D8_INPUTENABLEVOUT1_D8_PULLTYPESELECTVOUT1_D8_PULLUDENABLERESERVEDVOUT1_D8_MODESELECTVOUT1_D8_DELAYMODEVOUT1_D8_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D8_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D8_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D8_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D8_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D8_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D8_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D8_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D8_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D8_MUXMODERW0xF
0x0: vout1_d8
0x2: uart6_rxd
0x3: vin4a_d8
0x4: vin3a_d8
0xE: gpio8_8
0xF: Driver off
Table 18-681 CTRL_CORE_PAD_VOUT1_D9
Address Offset0x0000 1600
Physical Address0x4A00 3600InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D9_WAKEUPEVENTVOUT1_D9_WAKEUPENABLERESERVEDVOUT1_D9_SLEWCONTROLVOUT1_D9_INPUTENABLEVOUT1_D9_PULLTYPESELECTVOUT1_D9_PULLUDENABLERESERVEDVOUT1_D9_MODESELECTVOUT1_D9_DELAYMODEVOUT1_D9_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D9_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D9_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D9_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D9_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D9_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D9_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D9_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D9_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D9_MUXMODERW0xF
0x0: vout1_d9
0x2: uart6_txd
0x3: vin4a_d9
0x4: vin3a_d9
0xE: gpio8_9
0xF: Driver off
Table 18-682 CTRL_CORE_PAD_VOUT1_D10
Address Offset0x0000 1604
Physical Address0x4A00 3604InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D10_WAKEUPEVENTVOUT1_D10_WAKEUPENABLERESERVEDVOUT1_D10_SLEWCONTROLVOUT1_D10_INPUTENABLEVOUT1_D10_PULLTYPESELECTVOUT1_D10_PULLUDENABLERESERVEDVOUT1_D10_MODESELECTVOUT1_D10_DELAYMODEVOUT1_D10_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D10_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D10_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D10_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D10_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D10_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D10_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D10_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D10_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D10_MUXMODERW0xF
0x0: vout1_d10
0x2: emu3
0x3: vin4a_d10
0x4: vin3a_d10
0x5: obs5
0x6: obs21
0x7: obs_irq2
0xE: gpio8_10
0xF: Driver off
Table 18-683 CTRL_CORE_PAD_VOUT1_D11
Address Offset0x0000 1608
Physical Address0x4A00 3608InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D11_WAKEUPEVENTVOUT1_D11_WAKEUPENABLERESERVEDVOUT1_D11_SLEWCONTROLVOUT1_D11_INPUTENABLEVOUT1_D11_PULLTYPESELECTVOUT1_D11_PULLUDENABLERESERVEDVOUT1_D11_MODESELECTVOUT1_D11_DELAYMODEVOUT1_D11_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D11_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D11_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D11_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D11_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D11_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D11_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D11_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D11_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D11_MUXMODERW0xF
0x0: vout1_d11
0x2: emu10
0x3: vin4a_d11
0x4: vin3a_d11
0x5: obs6
0x6: obs22
0x7: obs_dmarq2
0xE: gpio8_11
0xF: Driver off
Table 18-684 CTRL_CORE_PAD_VOUT1_D12
Address Offset0x0000 160C
Physical Address0x4A00 360CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D12_WAKEUPEVENTVOUT1_D12_WAKEUPENABLERESERVEDVOUT1_D12_SLEWCONTROLVOUT1_D12_INPUTENABLEVOUT1_D12_PULLTYPESELECTVOUT1_D12_PULLUDENABLERESERVEDVOUT1_D12_MODESELECTVOUT1_D12_DELAYMODEVOUT1_D12_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D12_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D12_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D12_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D12_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D12_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D12_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D12_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D12_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D12_MUXMODERW0xF
0x0: vout1_d12
0x2: emu11
0x3: vin4a_d12
0x4: vin3a_d12
0x5: obs7
0x6: obs23
0xE: gpio8_12
0xF: Driver off
Table 18-685 CTRL_CORE_PAD_VOUT1_D13
Address Offset0x0000 1610
Physical Address0x4A00 3610InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D13_WAKEUPEVENTVOUT1_D13_WAKEUPENABLERESERVEDVOUT1_D13_SLEWCONTROLVOUT1_D13_INPUTENABLEVOUT1_D13_PULLTYPESELECTVOUT1_D13_PULLUDENABLERESERVEDVOUT1_D13_MODESELECTVOUT1_D13_DELAYMODEVOUT1_D13_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D13_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D13_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D13_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D13_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D13_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D13_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D13_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D13_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D13_MUXMODERW0xF
0x0: vout1_d13
0x2: emu12
0x3: vin4a_d13
0x4: vin3a_d13
0x5: obs8
0x6: obs24
0xE: gpio8_13
0xF: Driver off
Table 18-686 CTRL_CORE_PAD_VOUT1_D14
Address Offset0x0000 1614
Physical Address0x4A00 3614InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D14_WAKEUPEVENTVOUT1_D14_WAKEUPENABLERESERVEDVOUT1_D14_SLEWCONTROLVOUT1_D14_INPUTENABLEVOUT1_D14_PULLTYPESELECTVOUT1_D14_PULLUDENABLERESERVEDVOUT1_D14_MODESELECTVOUT1_D14_DELAYMODEVOUT1_D14_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D14_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D14_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D14_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D14_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D14_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D14_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D14_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D14_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D14_MUXMODERW0xF
0x0: vout1_d14
0x2: emu13
0x3: vin4a_d14
0x4: vin3a_d14
0x5: obs9
0x6: obs25
0xE: gpio8_14
0xF: Driver off
Table 18-687 CTRL_CORE_PAD_VOUT1_D15
Address Offset0x0000 1618
Physical Address0x4A00 3618InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D15_WAKEUPEVENTVOUT1_D15_WAKEUPENABLERESERVEDVOUT1_D15_SLEWCONTROLVOUT1_D15_INPUTENABLEVOUT1_D15_PULLTYPESELECTVOUT1_D15_PULLUDENABLERESERVEDVOUT1_D15_MODESELECTVOUT1_D15_DELAYMODEVOUT1_D15_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D15_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D15_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D15_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D15_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D15_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D15_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D15_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D15_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D15_MUXMODERW0xF
0x0: vout1_d15
0x2: emu14
0x3: vin4a_d15
0x4: vin3a_d15
0x5: obs10
0x6: obs26
0xE: gpio8_15
0xF: Driver off
Table 18-688 CTRL_CORE_PAD_VOUT1_D16
Address Offset0x0000 161C
Physical Address0x4A00 361CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D16_WAKEUPEVENTVOUT1_D16_WAKEUPENABLERESERVEDVOUT1_D16_SLEWCONTROLVOUT1_D16_INPUTENABLEVOUT1_D16_PULLTYPESELECTVOUT1_D16_PULLUDENABLERESERVEDVOUT1_D16_MODESELECTVOUT1_D16_DELAYMODEVOUT1_D16_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D16_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D16_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D16_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D16_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D16_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D16_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D16_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D16_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D16_MUXMODERW0xF
0x0: vout1_d16
0x2: uart7_rxd
0x3: vin4a_d0
0x4: vin3a_d0
0xE: gpio8_16
0xF: Driver off
Table 18-689 CTRL_CORE_PAD_VOUT1_D17
Address Offset0x0000 1620
Physical Address0x4A00 3620InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D17_WAKEUPEVENTVOUT1_D17_WAKEUPENABLERESERVEDVOUT1_D17_SLEWCONTROLVOUT1_D17_INPUTENABLEVOUT1_D17_PULLTYPESELECTVOUT1_D17_PULLUDENABLERESERVEDVOUT1_D17_MODESELECTVOUT1_D17_DELAYMODEVOUT1_D17_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D17_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D17_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D17_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D17_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D17_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D17_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D17_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D17_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D17_MUXMODERW0xF
0x0: vout1_d17
0x2: uart7_txd
0x3: vin4a_d1
0x4: vin3a_d1
0xE: gpio8_17
0xF: Driver off
Table 18-690 CTRL_CORE_PAD_VOUT1_D18
Address Offset0x0000 1624
Physical Address0x4A00 3624InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D18_WAKEUPEVENTVOUT1_D18_WAKEUPENABLERESERVEDVOUT1_D18_SLEWCONTROLVOUT1_D18_INPUTENABLEVOUT1_D18_PULLTYPESELECTVOUT1_D18_PULLUDENABLERESERVEDVOUT1_D18_MODESELECTVOUT1_D18_DELAYMODEVOUT1_D18_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D18_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D18_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D18_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D18_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D18_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D18_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D18_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D18_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D18_MUXMODERW0xF
0x0: vout1_d18
0x2: emu4
0x3: vin4a_d2
0x4: vin3a_d2
0x5: obs11
0x6: obs27
0xE: gpio8_18
0xF: Driver off
Table 18-691 CTRL_CORE_PAD_VOUT1_D19
Address Offset0x0000 1628
Physical Address0x4A00 3628InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D19_WAKEUPEVENTVOUT1_D19_WAKEUPENABLERESERVEDVOUT1_D19_SLEWCONTROLVOUT1_D19_INPUTENABLEVOUT1_D19_PULLTYPESELECTVOUT1_D19_PULLUDENABLERESERVEDVOUT1_D19_MODESELECTVOUT1_D19_DELAYMODEVOUT1_D19_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D19_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D19_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D19_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D19_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D19_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D19_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D19_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D19_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D19_MUXMODERW0xF
0x0: vout1_d19
0x2: emu15
0x3: vin4a_d3
0x4: vin3a_d3
0x5: obs12
0x6: obs28
0xE: gpio8_19
0xF: Driver off
Table 18-692 CTRL_CORE_PAD_VOUT1_D20
Address Offset0x0000 162C
Physical Address0x4A00 362CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D20_WAKEUPEVENTVOUT1_D20_WAKEUPENABLERESERVEDVOUT1_D20_SLEWCONTROLVOUT1_D20_INPUTENABLEVOUT1_D20_PULLTYPESELECTVOUT1_D20_PULLUDENABLERESERVEDVOUT1_D20_MODESELECTVOUT1_D20_DELAYMODEVOUT1_D20_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D20_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D20_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D20_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D20_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D20_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D20_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D20_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D20_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D20_MUXMODERW0xF
0x0: vout1_d20
0x2: emu16
0x3: vin4a_d4
0x4: vin3a_d4
0x5: obs13
0x6: obs29
0xE: gpio8_20
0xF: Driver off
Table 18-693 CTRL_CORE_PAD_VOUT1_D21
Address Offset0x0000 1630
Physical Address0x4A00 3630InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D21_WAKEUPEVENTVOUT1_D21_WAKEUPENABLERESERVEDVOUT1_D21_SLEWCONTROLVOUT1_D21_INPUTENABLEVOUT1_D21_PULLTYPESELECTVOUT1_D21_PULLUDENABLERESERVEDVOUT1_D21_MODESELECTVOUT1_D21_DELAYMODEVOUT1_D21_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D21_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D21_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D21_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D21_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D21_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D21_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D21_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D21_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D21_MUXMODERW0xF
0x0: vout1_d21
0x2: emu17
0x3: vin4a_d5
0x4: vin3a_d5
0x5: obs14
0x6: obs30
0xE: gpio8_21
0xF: Driver off
Table 18-694 CTRL_CORE_PAD_VOUT1_D22
Address Offset0x0000 1634
Physical Address0x4A00 3634InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D22_WAKEUPEVENTVOUT1_D22_WAKEUPENABLERESERVEDVOUT1_D22_SLEWCONTROLVOUT1_D22_INPUTENABLEVOUT1_D22_PULLTYPESELECTVOUT1_D22_PULLUDENABLERESERVEDVOUT1_D22_MODESELECTVOUT1_D22_DELAYMODEVOUT1_D22_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D22_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D22_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D22_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D22_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D22_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D22_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D22_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D22_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D22_MUXMODERW0xF
0x0: vout1_d22
0x2: emu18
0x3: vin4a_d6
0x4: vin3a_d6
0x5: obs15
0x6: obs31
0xE: gpio8_22
0xF: Driver off
Table 18-695 CTRL_CORE_PAD_VOUT1_D23
Address Offset0x0000 1638
Physical Address0x4A00 3638InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDVOUT1_D23_WAKEUPEVENTVOUT1_D23_WAKEUPENABLERESERVEDVOUT1_D23_SLEWCONTROLVOUT1_D23_INPUTENABLEVOUT1_D23_PULLTYPESELECTVOUT1_D23_PULLUDENABLERESERVEDVOUT1_D23_MODESELECTVOUT1_D23_DELAYMODEVOUT1_D23_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25VOUT1_D23_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24VOUT1_D23_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19VOUT1_D23_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18VOUT1_D23_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17VOUT1_D23_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16VOUT1_D23_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8VOUT1_D23_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4VOUT1_D23_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0VOUT1_D23_MUXMODERW0xF
0x0: vout1_d23
0x2: emu19
0x3: vin4a_d7
0x4: vin3a_d7
0x8: spi3_cs3
0xE: gpio8_23
0xF: Driver off
Table 18-696 CTRL_CORE_PAD_MDIO_MCLK
Address Offset0x0000 163C
Physical Address0x4A00 363CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMDIO_MCLK_WAKEUPEVENTMDIO_MCLK_WAKEUPENABLERESERVEDMDIO_MCLK_SLEWCONTROLMDIO_MCLK_INPUTENABLEMDIO_MCLK_PULLTYPESELECTMDIO_MCLK_PULLUDENABLERESERVEDMDIO_MCLK_MODESELECTMDIO_MCLK_DELAYMODEMDIO_MCLK_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MDIO_MCLK_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MDIO_MCLK_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MDIO_MCLK_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MDIO_MCLK_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MDIO_MCLK_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MDIO_MCLK_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MDIO_MCLK_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MDIO_MCLK_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MDIO_MCLK_MUXMODERW0xF
0x0: mdio_mclk
0x1: uart3_rtsn
0x3: mii0_col
0x4: vin2a_clk0
0x5: vin4b_clk1
0xE: gpio5_15
0xF: Driver off
Table 18-697 CTRL_CORE_PAD_MDIO_D
Address Offset0x0000 1640
Physical Address0x4A00 3640InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMDIO_D_WAKEUPEVENTMDIO_D_WAKEUPENABLERESERVEDMDIO_D_SLEWCONTROLMDIO_D_INPUTENABLEMDIO_D_PULLTYPESELECTMDIO_D_PULLUDENABLERESERVEDMDIO_D_MODESELECTMDIO_D_DELAYMODEMDIO_D_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MDIO_D_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MDIO_D_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MDIO_D_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MDIO_D_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MDIO_D_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MDIO_D_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MDIO_D_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MDIO_D_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MDIO_D_MUXMODERW0xF
0x0: mdio_d
0x1: uart3_ctsn
0x3: mii0_txer
0x4: vin2a_d0
0x5: vin4b_d0
0xE: gpio5_16
0xF: Driver off
Table 18-698 CTRL_CORE_PAD_RMII_MHZ_50_CLK
Address Offset0x0000 1644
Physical Address0x4A00 3644InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRMII_MHZ_50_CLK_WAKEUPEVENTRMII_MHZ_50_CLK_WAKEUPENABLERESERVEDRMII_MHZ_50_CLK_SLEWCONTROLRMII_MHZ_50_CLK_INPUTENABLERMII_MHZ_50_CLK_PULLTYPESELECTRMII_MHZ_50_CLK_PULLUDENABLERESERVEDRMII_MHZ_50_CLK_MODESELECTRMII_MHZ_50_CLK_DELAYMODERMII_MHZ_50_CLK_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RMII_MHZ_50_CLK_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RMII_MHZ_50_CLK_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RMII_MHZ_50_CLK_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RMII_MHZ_50_CLK_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RMII_MHZ_50_CLK_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RMII_MHZ_50_CLK_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RMII_MHZ_50_CLK_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RMII_MHZ_50_CLK_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RMII_MHZ_50_CLK_MUXMODERW0xF
0x0: RMII_MHZ_50_CLK
0x4: vin2a_d11
0xE: gpio5_17
0xF: Driver off
Table 18-699 CTRL_CORE_PAD_UART3_RXD
Address Offset0x0000 1648
Physical Address0x4A00 3648InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART3_RXD_WAKEUPEVENTUART3_RXD_WAKEUPENABLERESERVEDUART3_RXD_SLEWCONTROLUART3_RXD_INPUTENABLEUART3_RXD_PULLTYPESELECTUART3_RXD_PULLUDENABLERESERVEDUART3_RXD_MODESELECTUART3_RXD_DELAYMODEUART3_RXD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART3_RXD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART3_RXD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART3_RXD_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART3_RXD_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART3_RXD_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART3_RXD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART3_RXD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART3_RXD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART3_RXD_MUXMODERW0xF
0x0: uart3_rxd
0x2: rmii1_crs
0x3: mii0_rxdv
0x4: vin2a_d1
0x5: vin4b_d1
0x7: spi3_sclk
0xE: gpio5_18
0xF: Driver off
Table 18-700 CTRL_CORE_PAD_UART3_TXD
Address Offset0x0000 164C
Physical Address0x4A00 364CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART3_TXD_WAKEUPEVENTUART3_TXD_WAKEUPENABLERESERVEDUART3_TXD_SLEWCONTROLUART3_TXD_INPUTENABLEUART3_TXD_PULLTYPESELECTUART3_TXD_PULLUDENABLERESERVEDUART3_TXD_MODESELECTUART3_TXD_DELAYMODEUART3_TXD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART3_TXD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART3_TXD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART3_TXD_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART3_TXD_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART3_TXD_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART3_TXD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART3_TXD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART3_TXD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART3_TXD_MUXMODERW0xF
0x0: uart3_txd
0x2: rmii1_rxer
0x3: mii0_rxclk
0x4: vin2a_d2
0x5: vin4b_d2
0x7: spi3_d1
0x8: spi4_cs1
0xE: gpio5_19
0xF: Driver off
Table 18-701 CTRL_CORE_PAD_RGMII0_TXC
Address Offset0x0000 1650
Physical Address0x4A00 3650InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_TXC_WAKEUPEVENTRGMII0_TXC_WAKEUPENABLERESERVEDRGMII0_TXC_SLEWCONTROLRGMII0_TXC_INPUTENABLERGMII0_TXC_PULLTYPESELECTRGMII0_TXC_PULLUDENABLERESERVEDRGMII0_TXC_MODESELECTRGMII0_TXC_DELAYMODERGMII0_TXC_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_TXC_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_TXC_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_TXC_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_TXC_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_TXC_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_TXC_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_TXC_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_TXC_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_TXC_MUXMODERW0xF
0x0: rgmii0_txc
0x1: uart3_ctsn
0x2: rmii1_rxd1
0x3: mii0_rxd3
0x4: vin2a_d3
0x5: vin4b_d3
0x6: usb4_ulpi_clk
0x7: spi3_d0
0x8: spi4_cs2
0xE: gpio5_20
0xF: Driver off
Table 18-702 CTRL_CORE_PAD_RGMII0_TXCTL
Address Offset0x0000 1654
Physical Address0x4A00 3654InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_TXCTL_WAKEUPEVENTRGMII0_TXCTL_WAKEUPENABLERESERVEDRGMII0_TXCTL_SLEWCONTROLRGMII0_TXCTL_INPUTENABLERGMII0_TXCTL_PULLTYPESELECTRGMII0_TXCTL_PULLUDENABLERESERVEDRGMII0_TXCTL_MODESELECTRGMII0_TXCTL_DELAYMODERGMII0_TXCTL_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_TXCTL_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_TXCTL_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_TXCTL_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_TXCTL_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_TXCTL_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_TXCTL_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_TXCTL_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_TXCTL_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_TXCTL_MUXMODERW0xF
0x0: rgmii0_txctl
0x1: uart3_rtsn
0x2: rmii1_rxd0
0x3: mii0_rxd2
0x4: vin2a_d4
0x5: vin4b_d4
0x6: usb4_ulpi_stp
0x7: spi3_cs0
0x8: spi4_cs3
0xE: gpio5_21
0xF: Driver off
Table 18-703 CTRL_CORE_PAD_RGMII0_TXD3
Address Offset0x0000 1658
Physical Address0x4A00 3658InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_TXD3_WAKEUPEVENTRGMII0_TXD3_WAKEUPENABLERESERVEDRGMII0_TXD3_SLEWCONTROLRGMII0_TXD3_INPUTENABLERGMII0_TXD3_PULLTYPESELECTRGMII0_TXD3_PULLUDENABLERESERVEDRGMII0_TXD3_MODESELECTRGMII0_TXD3_DELAYMODERGMII0_TXD3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_TXD3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_TXD3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_TXD3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_TXD3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_TXD3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_TXD3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_TXD3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_TXD3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_TXD3_MUXMODERW0xF
0x0: rgmii0_txd3
0x1: rmii0_crs
0x3: mii0_crs
0x4: vin2a_de0
0x5: vin4b_de1
0x6: usb4_ulpi_dir
0x7: spi4_sclk
0x8: uart4_rxd
0xE: gpio5_22
0xF: Driver off
Table 18-704 CTRL_CORE_PAD_RGMII0_TXD2
Address Offset0x0000 165C
Physical Address0x4A00 365CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_TXD2_WAKEUPEVENTRGMII0_TXD2_WAKEUPENABLERESERVEDRGMII0_TXD2_SLEWCONTROLRGMII0_TXD2_INPUTENABLERGMII0_TXD2_PULLTYPESELECTRGMII0_TXD2_PULLUDENABLERESERVEDRGMII0_TXD2_MODESELECTRGMII0_TXD2_DELAYMODERGMII0_TXD2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_TXD2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_TXD2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_TXD2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_TXD2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_TXD2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_TXD2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_TXD2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_TXD2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_TXD2_MUXMODERW0xF
0x0: rgmii0_txd2
0x1: rmii0_rxer
0x3: mii0_rxer
0x4: vin2a_hsync0
0x5: vin4b_hsync1
0x6: usb4_ulpi_nxt
0x7: spi4_d1
0x8: uart4_txd
0xE: gpio5_23
0xF: Driver off
Table 18-705 CTRL_CORE_PAD_RGMII0_TXD1
Address Offset0x0000 1660
Physical Address0x4A00 3660InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_TXD1_WAKEUPEVENTRGMII0_TXD1_WAKEUPENABLERESERVEDRGMII0_TXD1_SLEWCONTROLRGMII0_TXD1_INPUTENABLERGMII0_TXD1_PULLTYPESELECTRGMII0_TXD1_PULLUDENABLERESERVEDRGMII0_TXD1_MODESELECTRGMII0_TXD1_DELAYMODERGMII0_TXD1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_TXD1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_TXD1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_TXD1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_TXD1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_TXD1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_TXD1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_TXD1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_TXD1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_TXD1_MUXMODERW0xF
0x0: rgmii0_txd1
0x1: rmii0_rxd1
0x3: mii0_rxd1
0x4: vin2a_vsync0
0x5: vin4b_vsync1
0x6: usb4_ulpi_d0
0x7: spi4_d0
0x8: uart4_ctsn
0xE: gpio5_24
0xF: Driver off
Table 18-706 CTRL_CORE_PAD_RGMII0_TXD0
Address Offset0x0000 1664
Physical Address0x4A00 3664InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_TXD0_WAKEUPEVENTRGMII0_TXD0_WAKEUPENABLERESERVEDRGMII0_TXD0_SLEWCONTROLRGMII0_TXD0_INPUTENABLERGMII0_TXD0_PULLTYPESELECTRGMII0_TXD0_PULLUDENABLERESERVEDRGMII0_TXD0_MODESELECTRGMII0_TXD0_DELAYMODERGMII0_TXD0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_TXD0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_TXD0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_TXD0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_TXD0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_TXD0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_TXD0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_TXD0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_TXD0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_TXD0_MUXMODERW0xF
0x0: rgmii0_txd0
0x1: rmii0_rxd0
0x3: mii0_rxd0
0x4: vin2a_d10
0x6: usb4_ulpi_d1
0x7: spi4_cs0
0x8: uart4_rtsn
0xE: gpio5_25
0xF: Driver off
Table 18-707 CTRL_CORE_PAD_RGMII0_RXC
Address Offset0x0000 1668
Physical Address0x4A00 3668InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_RXC_WAKEUPEVENTRGMII0_RXC_WAKEUPENABLERESERVEDRGMII0_RXC_SLEWCONTROLRGMII0_RXC_INPUTENABLERGMII0_RXC_PULLTYPESELECTRGMII0_RXC_PULLUDENABLERESERVEDRGMII0_RXC_MODESELECTRGMII0_RXC_DELAYMODERGMII0_RXC_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_RXC_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_RXC_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_RXC_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_RXC_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_RXC_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_RXC_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_RXC_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_RXC_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_RXC_MUXMODERW0xF
0x0: rgmii0_rxc
0x2: rmii1_txen
0x3: mii0_txclk
0x4: vin2a_d5
0x5: vin4b_d5
0x6: usb4_ulpi_d2
0xE: gpio5_26
0xF: Driver off
Table 18-708 CTRL_CORE_PAD_RGMII0_RXCTL
Address Offset0x0000 166C
Physical Address0x4A00 366CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_RXCTL_WAKEUPEVENTRGMII0_RXCTL_WAKEUPENABLERESERVEDRGMII0_RXCTL_SLEWCONTROLRGMII0_RXCTL_INPUTENABLERGMII0_RXCTL_PULLTYPESELECTRGMII0_RXCTL_PULLUDENABLERESERVEDRGMII0_RXCTL_MODESELECTRGMII0_RXCTL_DELAYMODERGMII0_RXCTL_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_RXCTL_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_RXCTL_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_RXCTL_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_RXCTL_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_RXCTL_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_RXCTL_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_RXCTL_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_RXCTL_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_RXCTL_MUXMODERW0xF
0x0: rgmii0_rxctl
0x2: rmii1_txd1
0x3: mii0_txd3
0x4: vin2a_d6
0x5: vin4b_d6
0x6: usb4_ulpi_d3
0xE: gpio5_27
0xF: Driver off
Table 18-709 CTRL_CORE_PAD_RGMII0_RXD3
Address Offset0x0000 1670
Physical Address0x4A00 3670InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_RXD3_WAKEUPEVENTRGMII0_RXD3_WAKEUPENABLERESERVEDRGMII0_RXD3_SLEWCONTROLRGMII0_RXD3_INPUTENABLERGMII0_RXD3_PULLTYPESELECTRGMII0_RXD3_PULLUDENABLERESERVEDRGMII0_RXD3_MODESELECTRGMII0_RXD3_DELAYMODERGMII0_RXD3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_RXD3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_RXD3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_RXD3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_RXD3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_RXD3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_RXD3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_RXD3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_RXD3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_RXD3_MUXMODERW0xF
0x0: rgmii0_rxd3
0x2: rmii1_txd0
0x3: mii0_txd2
0x4: vin2a_d7
0x5: vin4b_d7
0x6: usb4_ulpi_d4
0xE: gpio5_28
0xF: Driver off
Table 18-710 CTRL_CORE_PAD_RGMII0_RXD2
Address Offset0x0000 1674
Physical Address0x4A00 3674InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_RXD2_WAKEUPEVENTRGMII0_RXD2_WAKEUPENABLERESERVEDRGMII0_RXD2_SLEWCONTROLRGMII0_RXD2_INPUTENABLERGMII0_RXD2_PULLTYPESELECTRGMII0_RXD2_PULLUDENABLERESERVEDRGMII0_RXD2_MODESELECTRGMII0_RXD2_DELAYMODERGMII0_RXD2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_RXD2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_RXD2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_RXD2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_RXD2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_RXD2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_RXD2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_RXD2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_RXD2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_RXD2_MUXMODERW0xF
0x0: rgmii0_rxd2
0x1: rmii0_txen
0x3: mii0_txen
0x4: vin2a_d8
0x6: usb4_ulpi_d5
0xE: gpio5_29
0xF: Driver off
Table 18-711 CTRL_CORE_PAD_RGMII0_RXD1
Address Offset0x0000 1678
Physical Address0x4A00 3678InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_RXD1_WAKEUPEVENTRGMII0_RXD1_WAKEUPENABLERESERVEDRGMII0_RXD1_SLEWCONTROLRGMII0_RXD1_INPUTENABLERGMII0_RXD1_PULLTYPESELECTRGMII0_RXD1_PULLUDENABLERESERVEDRGMII0_RXD1_MODESELECTRGMII0_RXD1_DELAYMODERGMII0_RXD1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_RXD1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_RXD1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_RXD1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_RXD1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_RXD1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_RXD1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_RXD1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_RXD1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_RXD1_MUXMODERW0xF
0x0: rgmii0_rxd1
0x1: rmii0_txd1
0x3: mii0_txd1
0x4: vin2a_d9
0x6: usb4_ulpi_d6
0xE: gpio5_30
0xF: Driver off
Table 18-712 CTRL_CORE_PAD_RGMII0_RXD0
Address Offset0x0000 167C
Physical Address0x4A00 367CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRGMII0_RXD0_WAKEUPEVENTRGMII0_RXD0_WAKEUPENABLERESERVEDRGMII0_RXD0_SLEWCONTROLRGMII0_RXD0_INPUTENABLERGMII0_RXD0_PULLTYPESELECTRGMII0_RXD0_PULLUDENABLERESERVEDRGMII0_RXD0_MODESELECTRGMII0_RXD0_DELAYMODERGMII0_RXD0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RGMII0_RXD0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RGMII0_RXD0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RGMII0_RXD0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RGMII0_RXD0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RGMII0_RXD0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RGMII0_RXD0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RGMII0_RXD0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RGMII0_RXD0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RGMII0_RXD0_MUXMODERW0xF
0x0: rgmii0_rxd0
0x1: rmii0_txd0
0x3: mii0_txd0
0x4: vin2a_fld0
0x5: vin4b_fld1
0x6: usb4_ulpi_d7
0xE: gpio5_31
0xF: Driver off
Table 18-713 CTRL_CORE_PAD_USB1_DRVVBUS
Address Offset0x0000 1680
Physical Address0x4A00 3680InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUSB1_DRVVBUS_WAKEUPEVENTUSB1_DRVVBUS_WAKEUPENABLERESERVEDUSB1_DRVVBUS_SLEWCONTROLUSB1_DRVVBUS_INPUTENABLEUSB1_DRVVBUS_PULLTYPESELECTUSB1_DRVVBUS_PULLUDENABLERESERVEDUSB1_DRVVBUS_MODESELECTUSB1_DRVVBUS_DELAYMODEUSB1_DRVVBUS_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25USB1_DRVVBUS_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24USB1_DRVVBUS_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19USB1_DRVVBUS_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18USB1_DRVVBUS_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17USB1_DRVVBUS_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16USB1_DRVVBUS_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8USB1_DRVVBUS_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4USB1_DRVVBUS_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0USB1_DRVVBUS_MUXMODERW0xF
0x0: usb1_drvvbus
0x7: timer16
0xE: gpio6_12
0xF: Driver off
Table 18-714 CTRL_CORE_PAD_USB2_DRVVBUS
Address Offset0x0000 1684
Physical Address0x4A00 3684InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUSB2_DRVVBUS_WAKEUPEVENTUSB2_DRVVBUS_WAKEUPENABLERESERVEDUSB2_DRVVBUS_SLEWCONTROLUSB2_DRVVBUS_INPUTENABLEUSB2_DRVVBUS_PULLTYPESELECTUSB2_DRVVBUS_PULLUDENABLERESERVEDUSB2_DRVVBUS_MODESELECTUSB2_DRVVBUS_DELAYMODEUSB2_DRVVBUS_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25USB2_DRVVBUS_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24USB2_DRVVBUS_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19USB2_DRVVBUS_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18USB2_DRVVBUS_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17USB2_DRVVBUS_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16USB2_DRVVBUS_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8USB2_DRVVBUS_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4USB2_DRVVBUS_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0USB2_DRVVBUS_MUXMODERW0xF
0x0: usb2_drvvbus
0x7: timer15
0xE: gpio6_13
0xF: Driver off
Table 18-715 CTRL_CORE_PAD_GPIO6_14
Address Offset0x0000 1688
Physical Address0x4A00 3688InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPIO6_14_WAKEUPEVENTGPIO6_14_WAKEUPENABLERESERVEDGPIO6_14_SLEWCONTROLGPIO6_14_INPUTENABLEGPIO6_14_PULLTYPESELECTGPIO6_14_PULLUDENABLERESERVEDGPIO6_14_MODESELECTGPIO6_14_DELAYMODEGPIO6_14_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPIO6_14_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPIO6_14_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPIO6_14_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPIO6_14_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPIO6_14_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPIO6_14_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPIO6_14_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPIO6_14_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPIO6_14_MUXMODERW0xF
0x0: gpio6_14
0x1: mcasp1_axr8
0x2: dcan2_tx
0x3: uart10_rxd
0x6: vout2_hsync
0x8: vin4a_hsync0
0x9: i2c3_sda
0xA: timer1
0xE: gpio6_14
0xF: Driver off
Table 18-716 CTRL_CORE_PAD_GPIO6_15
Address Offset0x0000 168C
Physical Address0x4A00 368CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPIO6_15_WAKEUPEVENTGPIO6_15_WAKEUPENABLERESERVEDGPIO6_15_SLEWCONTROLGPIO6_15_INPUTENABLEGPIO6_15_PULLTYPESELECTGPIO6_15_PULLUDENABLERESERVEDGPIO6_15_MODESELECTGPIO6_15_DELAYMODEGPIO6_15_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPIO6_15_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPIO6_15_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPIO6_15_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPIO6_15_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPIO6_15_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPIO6_15_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPIO6_15_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPIO6_15_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPIO6_15_MUXMODERW0xF
0x0: gpio6_15
0x1: mcasp1_axr9
0x2: dcan2_rx
0x3: uart10_txd
0x6: vout2_vsync
0x8: vin4a_vsync0
0x9: i2c3_scl
0xA: timer2
0xE: gpio6_15
0xF: Driver off
Table 18-717 CTRL_CORE_PAD_GPIO6_16
Address Offset0x0000 1690
Physical Address0x4A00 3690InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPIO6_16_WAKEUPEVENTGPIO6_16_WAKEUPENABLERESERVEDGPIO6_16_SLEWCONTROLGPIO6_16_INPUTENABLEGPIO6_16_PULLTYPESELECTGPIO6_16_PULLUDENABLERESERVEDGPIO6_16_MODESELECTGPIO6_16_DELAYMODEGPIO6_16_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPIO6_16_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPIO6_16_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPIO6_16_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPIO6_16_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPIO6_16_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPIO6_16_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPIO6_16_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPIO6_16_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPIO6_16_MUXMODERW0xF
0x0: gpio6_16
0x1: mcasp1_axr10
0x6: vout2_fld
0x8: vin4a_fld0
0x9: clkout1
0xA: timer3
0xE: gpio6_16
0xF: Driver off
Table 18-718 CTRL_CORE_PAD_XREF_CLK0
Address Offset0x0000 1694
Physical Address0x4A00 3694InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDXREF_CLK0_WAKEUPEVENTXREF_CLK0_WAKEUPENABLERESERVEDXREF_CLK0_SLEWCONTROLXREF_CLK0_INPUTENABLEXREF_CLK0_PULLTYPESELECTXREF_CLK0_PULLUDENABLERESERVEDXREF_CLK0_MODESELECTXREF_CLK0_DELAYMODEXREF_CLK0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25XREF_CLK0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24XREF_CLK0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19XREF_CLK0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18XREF_CLK0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17XREF_CLK0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16XREF_CLK0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8XREF_CLK0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4XREF_CLK0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0XREF_CLK0_MUXMODERW0xF
0x0: xref_clk0
0x1: mcasp2_axr8
0x2: mcasp1_axr4
0x3: mcasp1_ahclkx
0x4: mcasp5_ahclkx
0x5: atl_clk0
0x7: vin6a_d0
0x8: hdq0
0x9: clkout2
0xA: timer13
0xE: gpio6_17
0xF: Driver off
Table 18-719 CTRL_CORE_PAD_XREF_CLK1
Address Offset0x0000 1698
Physical Address0x4A00 3698InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDXREF_CLK1_WAKEUPEVENTXREF_CLK1_WAKEUPENABLERESERVEDXREF_CLK1_SLEWCONTROLXREF_CLK1_INPUTENABLEXREF_CLK1_PULLTYPESELECTXREF_CLK1_PULLUDENABLERESERVEDXREF_CLK1_MODESELECTXREF_CLK1_DELAYMODEXREF_CLK1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25XREF_CLK1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24XREF_CLK1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19XREF_CLK1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18XREF_CLK1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17XREF_CLK1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16XREF_CLK1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8XREF_CLK1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4XREF_CLK1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0XREF_CLK1_MUXMODERW0xF
0x0: xref_clk1
0x1: mcasp2_axr9
0x2: mcasp1_axr5
0x3: mcasp2_ahclkx
0x4: mcasp6_ahclkx
0x5: atl_clk1
0x7: vin6a_clk0
0xA: timer14
0xE: gpio6_18
0xF: Driver off
Table 18-720 CTRL_CORE_PAD_XREF_CLK2
Address Offset0x0000 169C
Physical Address0x4A00 369CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDXREF_CLK2_WAKEUPEVENTXREF_CLK2_WAKEUPENABLERESERVEDXREF_CLK2_SLEWCONTROLXREF_CLK2_INPUTENABLEXREF_CLK2_PULLTYPESELECTXREF_CLK2_PULLUDENABLERESERVEDXREF_CLK2_MODESELECTXREF_CLK2_DELAYMODEXREF_CLK2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25XREF_CLK2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24XREF_CLK2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19XREF_CLK2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18XREF_CLK2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17XREF_CLK2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16XREF_CLK2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8XREF_CLK2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4XREF_CLK2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0XREF_CLK2_MUXMODERW0xF
0x0: xref_clk2
0x1: mcasp2_axr10
0x2: mcasp1_axr6
0x3: mcasp3_ahclkx
0x4: mcasp7_ahclkx
0x5: atl_clk2
0x6: vout2_clk
0x8: vin4a_clk0
0xA: timer15
0xE: gpio6_19
0xF: Driver off
Table 18-721 CTRL_CORE_PAD_XREF_CLK3
Address Offset0x0000 16A0
Physical Address0x4A00 36A0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDXREF_CLK3_WAKEUPEVENTXREF_CLK3_WAKEUPENABLERESERVEDXREF_CLK3_SLEWCONTROLXREF_CLK3_INPUTENABLEXREF_CLK3_PULLTYPESELECTXREF_CLK3_PULLUDENABLERESERVEDXREF_CLK3_MODESELECTXREF_CLK3_DELAYMODEXREF_CLK3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25XREF_CLK3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24XREF_CLK3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19XREF_CLK3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18XREF_CLK3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17XREF_CLK3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16XREF_CLK3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8XREF_CLK3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4XREF_CLK3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0XREF_CLK3_MUXMODERW0xF
0x0: xref_clk3
0x1: mcasp2_axr11
0x2: mcasp1_axr7
0x3: mcasp4_ahclkx
0x4: mcasp8_ahclkx
0x5: atl_clk3
0x6: vout2_de
0x7: hdq0
0x8: vin4a_de0
0x9: clkout3
0xA: timer16
0xE: gpio6_20
0xF: Driver off
Table 18-722 CTRL_CORE_PAD_MCASP1_ACLKX
Address Offset0x0000 16A4
Physical Address0x4A00 36A4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_ACLKX_WAKEUPEVENTMCASP1_ACLKX_WAKEUPENABLERESERVEDMCASP1_ACLKX_SLEWCONTROLMCASP1_ACLKX_INPUTENABLEMCASP1_ACLKX_PULLTYPESELECTMCASP1_ACLKX_PULLUDENABLERESERVEDMCASP1_ACLKX_MODESELECTMCASP1_ACLKX_DELAYMODEMCASP1_ACLKX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_ACLKX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_ACLKX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_ACLKX_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_ACLKX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_ACLKX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_ACLKX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_ACLKX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_ACLKX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_ACLKX_MUXMODERW0xF
0x0: mcasp1_aclkx
0x7: vin6a_fld0
0xA: i2c3_sda
0xE: gpio7_31
0xF: Driver off
Table 18-723 CTRL_CORE_PAD_MCASP1_FSX
Address Offset0x0000 16A8
Physical Address0x4A00 36A8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_FSX_WAKEUPEVENTMCASP1_FSX_WAKEUPENABLERESERVEDMCASP1_FSX_SLEWCONTROLMCASP1_FSX_INPUTENABLEMCASP1_FSX_PULLTYPESELECTMCASP1_FSX_PULLUDENABLERESERVEDMCASP1_FSX_MODESELECTMCASP1_FSX_DELAYMODEMCASP1_FSX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_FSX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_FSX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_FSX_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_FSX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_FSX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_FSX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_FSX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_FSX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_FSX_MUXMODERW0xF
0x0: mcasp1_fsx
0x7: vin6a_de0
0xA: i2c3_scl
0xE: gpio7_30
0xF: Driver off
Table 18-724 CTRL_CORE_PAD_MCASP1_ACLKR
Address Offset0x0000 16AC
Physical Address0x4A00 36ACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_ACLKR_WAKEUPEVENTMCASP1_ACLKR_WAKEUPENABLERESERVEDMCASP1_ACLKR_SLEWCONTROLMCASP1_ACLKR_INPUTENABLEMCASP1_ACLKR_PULLTYPESELECTMCASP1_ACLKR_PULLUDENABLERESERVEDMCASP1_ACLKR_MODESELECTMCASP1_ACLKR_DELAYMODEMCASP1_ACLKR_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_ACLKR_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_ACLKR_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_ACLKR_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_ACLKR_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_ACLKR_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_ACLKR_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_ACLKR_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_ACLKR_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_ACLKR_MUXMODERW0xF
0x0: mcasp1_aclkr
0x1: mcasp7_axr2
0x6: vout2_d0
0x8: vin4a_d0
0xA: i2c4_sda
0xE: gpio5_0
0xF: Driver off
Table 18-725 CTRL_CORE_PAD_MCASP1_FSR
Address Offset0x0000 16B0
Physical Address0x4A00 36B0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_FSR_WAKEUPEVENTMCASP1_FSR_WAKEUPENABLERESERVEDMCASP1_FSR_SLEWCONTROLMCASP1_FSR_INPUTENABLEMCASP1_FSR_PULLTYPESELECTMCASP1_FSR_PULLUDENABLERESERVEDMCASP1_FSR_MODESELECTMCASP1_FSR_DELAYMODEMCASP1_FSR_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_FSR_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_FSR_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_FSR_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_FSR_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_FSR_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_FSR_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_FSR_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_FSR_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_FSR_MUXMODERW0xF
0x0: mcasp1_fsr
0x1: mcasp7_axr3
0x6: vout2_d1
0x8: vin4a_d1
0xA: i2c4_scl
0xE: gpio5_1
0xF: Driver off
Table 18-726 CTRL_CORE_PAD_MCASP1_AXR0
Address Offset0x0000 16B4
Physical Address0x4A00 36B4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR0_WAKEUPEVENTMCASP1_AXR0_WAKEUPENABLERESERVEDMCASP1_AXR0_SLEWCONTROLMCASP1_AXR0_INPUTENABLEMCASP1_AXR0_PULLTYPESELECTMCASP1_AXR0_PULLUDENABLERESERVEDMCASP1_AXR0_MODESELECTMCASP1_AXR0_DELAYMODEMCASP1_AXR0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR0_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR0_MUXMODERW0xF
0x0: mcasp1_axr0
0x3: uart6_rxd
0x7: vin6a_vsync0
0xA: i2c5_sda
0xE: gpio5_2
0xF: Driver off
Table 18-727 CTRL_CORE_PAD_MCASP1_AXR1
Address Offset0x0000 16B8
Physical Address0x4A00 36B8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR1_WAKEUPEVENTMCASP1_AXR1_WAKEUPENABLERESERVEDMCASP1_AXR1_SLEWCONTROLMCASP1_AXR1_INPUTENABLEMCASP1_AXR1_PULLTYPESELECTMCASP1_AXR1_PULLUDENABLERESERVEDMCASP1_AXR1_MODESELECTMCASP1_AXR1_DELAYMODEMCASP1_AXR1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR1_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR1_MUXMODERW0xF
0x0: mcasp1_axr1
0x3: uart6_txd
0x7: vin6a_hsync0
0xA: i2c5_scl
0xE: gpio5_3
0xF: Driver off
Table 18-728 CTRL_CORE_PAD_MCASP1_AXR2
Address Offset0x0000 16BC
Physical Address0x4A00 36BCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR2_WAKEUPEVENTMCASP1_AXR2_WAKEUPENABLERESERVEDMCASP1_AXR2_SLEWCONTROLMCASP1_AXR2_INPUTENABLEMCASP1_AXR2_PULLTYPESELECTMCASP1_AXR2_PULLUDENABLERESERVEDMCASP1_AXR2_MODESELECTMCASP1_AXR2_DELAYMODEMCASP1_AXR2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR2_MUXMODERW0xF
0x0: mcasp1_axr2
0x1: mcasp6_axr2
0x3: uart6_ctsn
0x6: vout2_d2
0x8: vin4a_d2
0xE: gpio5_4
0xF: Driver off
Table 18-729 CTRL_CORE_PAD_MCASP1_AXR3
Address Offset0x0000 16C0
Physical Address0x4A00 36C0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR3_WAKEUPEVENTMCASP1_AXR3_WAKEUPENABLERESERVEDMCASP1_AXR3_SLEWCONTROLMCASP1_AXR3_INPUTENABLEMCASP1_AXR3_PULLTYPESELECTMCASP1_AXR3_PULLUDENABLERESERVEDMCASP1_AXR3_MODESELECTMCASP1_AXR3_DELAYMODEMCASP1_AXR3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR3_MUXMODERW0xF
0x0: mcasp1_axr3
0x1: mcasp6_axr3
0x3: uart6_rtsn
0x6: vout2_d3
0x8: vin4a_d3
0xE: gpio5_5
0xF: Driver off
Table 18-730 CTRL_CORE_PAD_MCASP1_AXR4
Address Offset0x0000 16C4
Physical Address0x4A00 36C4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR4_WAKEUPEVENTMCASP1_AXR4_WAKEUPENABLERESERVEDMCASP1_AXR4_SLEWCONTROLMCASP1_AXR4_INPUTENABLEMCASP1_AXR4_PULLTYPESELECTMCASP1_AXR4_PULLUDENABLERESERVEDMCASP1_AXR4_MODESELECTMCASP1_AXR4_DELAYMODEMCASP1_AXR4_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR4_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR4_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR4_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR4_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR4_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR4_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR4_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR4_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR4_MUXMODERW0xF
0x0: mcasp1_axr4
0x1: mcasp4_axr2
0x6: vout2_d4
0x8: vin4a_d4
0xE: gpio5_6
0xF: Driver off
Table 18-731 CTRL_CORE_PAD_MCASP1_AXR5
Address Offset0x0000 16C8
Physical Address0x4A00 36C8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR5_WAKEUPEVENTMCASP1_AXR5_WAKEUPENABLERESERVEDMCASP1_AXR5_SLEWCONTROLMCASP1_AXR5_INPUTENABLEMCASP1_AXR5_PULLTYPESELECTMCASP1_AXR5_PULLUDENABLERESERVEDMCASP1_AXR5_MODESELECTMCASP1_AXR5_DELAYMODEMCASP1_AXR5_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR5_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR5_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR5_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR5_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR5_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR5_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR5_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR5_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR5_MUXMODERW0xF
0x0: mcasp1_axr5
0x1: mcasp4_axr3
0x6: vout2_d5
0x8: vin4a_d5
0xE: gpio5_7
0xF: Driver off
Table 18-732 CTRL_CORE_PAD_MCASP1_AXR6
Address Offset0x0000 16CC
Physical Address0x4A00 36CCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR6_WAKEUPEVENTMCASP1_AXR6_WAKEUPENABLERESERVEDMCASP1_AXR6_SLEWCONTROLMCASP1_AXR6_INPUTENABLEMCASP1_AXR6_PULLTYPESELECTMCASP1_AXR6_PULLUDENABLERESERVEDMCASP1_AXR6_MODESELECTMCASP1_AXR6_DELAYMODEMCASP1_AXR6_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR6_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR6_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR6_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR6_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR6_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR6_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR6_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR6_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR6_MUXMODERW0xF
0x0: mcasp1_axr6
0x1: mcasp5_axr2
0x6: vout2_d6
0x8: vin4a_d6
0xE: gpio5_8
0xF: Driver off
Table 18-733 CTRL_CORE_PAD_MCASP1_AXR7
Address Offset0x0000 16D0
Physical Address0x4A00 36D0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR7_WAKEUPEVENTMCASP1_AXR7_WAKEUPENABLERESERVEDMCASP1_AXR7_SLEWCONTROLMCASP1_AXR7_INPUTENABLEMCASP1_AXR7_PULLTYPESELECTMCASP1_AXR7_PULLUDENABLERESERVEDMCASP1_AXR7_MODESELECTMCASP1_AXR7_DELAYMODEMCASP1_AXR7_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR7_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR7_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR7_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR7_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR7_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR7_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR7_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR7_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR7_MUXMODERW0xF
0x0: mcasp1_axr7
0x1: mcasp5_axr3
0x6: vout2_d7
0x8: vin4a_d7
0xA: timer4
0xE: gpio5_9
0xF: Driver off
Table 18-734 CTRL_CORE_PAD_MCASP1_AXR8
Address Offset0x0000 16D4
Physical Address0x4A00 36D4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR8_WAKEUPEVENTMCASP1_AXR8_WAKEUPENABLERESERVEDMCASP1_AXR8_SLEWCONTROLMCASP1_AXR8_INPUTENABLEMCASP1_AXR8_PULLTYPESELECTMCASP1_AXR8_PULLUDENABLERESERVEDMCASP1_AXR8_MODESELECTMCASP1_AXR8_DELAYMODEMCASP1_AXR8_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR8_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR8_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR8_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR8_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR8_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR8_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR8_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR8_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR8_MUXMODERW0xF
0x0: mcasp1_axr8
0x1: mcasp6_axr0
0x3: spi3_sclk
0x7: vin6a_d15
0xA: timer5
0xE: gpio5_10
0xF: Driver off
Table 18-735 CTRL_CORE_PAD_MCASP1_AXR9
Address Offset0x0000 16D8
Physical Address0x4A00 36D8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR9_WAKEUPEVENTMCASP1_AXR9_WAKEUPENABLERESERVEDMCASP1_AXR9_SLEWCONTROLMCASP1_AXR9_INPUTENABLEMCASP1_AXR9_PULLTYPESELECTMCASP1_AXR9_PULLUDENABLERESERVEDMCASP1_AXR9_MODESELECTMCASP1_AXR9_DELAYMODEMCASP1_AXR9_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR9_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR9_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR9_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR9_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR9_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR9_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR9_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR9_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR9_MUXMODERW0xF
0x0: mcasp1_axr9
0x1: mcasp6_axr1
0x3: spi3_d1
0x7: vin6a_d14
0xA: timer6
0xE: gpio5_11
0xF: Driver off
Table 18-736 CTRL_CORE_PAD_MCASP1_AXR10
Address Offset0x0000 16DC
Physical Address0x4A00 36DCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR10_WAKEUPEVENTMCASP1_AXR10_WAKEUPENABLERESERVEDMCASP1_AXR10_SLEWCONTROLMCASP1_AXR10_INPUTENABLEMCASP1_AXR10_PULLTYPESELECTMCASP1_AXR10_PULLUDENABLERESERVEDMCASP1_AXR10_MODESELECTMCASP1_AXR10_DELAYMODEMCASP1_AXR10_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR10_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR10_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR10_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR10_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR10_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR10_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR10_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR10_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR10_MUXMODERW0xF
0x0: mcasp1_axr10
0x1: mcasp6_aclkx
0x2: mcasp6_aclkr
0x3: spi3_d0
0x7: vin6a_d13
0xA: timer7
0xE: gpio5_12
0xF: Driver off
Table 18-737 CTRL_CORE_PAD_MCASP1_AXR11
Address Offset0x0000 16E0
Physical Address0x4A00 36E0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR11_WAKEUPEVENTMCASP1_AXR11_WAKEUPENABLERESERVEDMCASP1_AXR11_SLEWCONTROLMCASP1_AXR11_INPUTENABLEMCASP1_AXR11_PULLTYPESELECTMCASP1_AXR11_PULLUDENABLERESERVEDMCASP1_AXR11_MODESELECTMCASP1_AXR11_DELAYMODEMCASP1_AXR11_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR11_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR11_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR11_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR11_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR11_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR11_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR11_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR11_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR11_MUXMODERW0xF
0x0: mcasp1_axr11
0x1: mcasp6_fsx
0x2: mcasp6_fsr
0x3: spi3_cs0
0x7: vin6a_d12
0xA: timer8
0xE: gpio4_17
0xF: Driver off
Table 18-738 CTRL_CORE_PAD_MCASP1_AXR12
Address Offset0x0000 16E4
Physical Address0x4A00 36E4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR12_WAKEUPEVENTMCASP1_AXR12_WAKEUPENABLERESERVEDMCASP1_AXR12_SLEWCONTROLMCASP1_AXR12_INPUTENABLEMCASP1_AXR12_PULLTYPESELECTMCASP1_AXR12_PULLUDENABLERESERVEDMCASP1_AXR12_MODESELECTMCASP1_AXR12_DELAYMODEMCASP1_AXR12_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR12_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR12_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR12_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR12_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR12_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR12_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR12_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR12_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR12_MUXMODERW0xF
0x0: mcasp1_axr12
0x1: mcasp7_axr0
0x3: spi3_cs1
0x7: vin6a_d11
0xA: timer9
0xE: gpio4_18
0xF: Driver off
Table 18-739 CTRL_CORE_PAD_MCASP1_AXR13
Address Offset0x0000 16E8
Physical Address0x4A00 36E8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR13_WAKEUPEVENTMCASP1_AXR13_WAKEUPENABLERESERVEDMCASP1_AXR13_SLEWCONTROLMCASP1_AXR13_INPUTENABLEMCASP1_AXR13_PULLTYPESELECTMCASP1_AXR13_PULLUDENABLERESERVEDMCASP1_AXR13_MODESELECTMCASP1_AXR13_DELAYMODEMCASP1_AXR13_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR13_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR13_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR13_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR13_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR13_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR13_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR13_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR13_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR13_MUXMODERW0xF
0x0: mcasp1_axr13
0x1: mcasp7_axr1
0x7: vin6a_d10
0xA: timer10
0xE: gpio6_4
0xF: Driver off
Table 18-740 CTRL_CORE_PAD_MCASP1_AXR14
Address Offset0x0000 16EC
Physical Address0x4A00 36ECInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR14_WAKEUPEVENTMCASP1_AXR14_WAKEUPENABLERESERVEDMCASP1_AXR14_SLEWCONTROLMCASP1_AXR14_INPUTENABLEMCASP1_AXR14_PULLTYPESELECTMCASP1_AXR14_PULLUDENABLERESERVEDMCASP1_AXR14_MODESELECTMCASP1_AXR14_DELAYMODEMCASP1_AXR14_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR14_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR14_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR14_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR14_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR14_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR14_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR14_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR14_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR14_MUXMODERW0xF
0x0: mcasp1_axr14
0x1: mcasp7_aclkx
0x2: mcasp7_aclkr
0x7: vin6a_d9
0xA: timer11
0xE: gpio6_5
0xF: Driver off
Table 18-741 CTRL_CORE_PAD_MCASP1_AXR15
Address Offset0x0000 16F0
Physical Address0x4A00 36F0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP1_AXR15_WAKEUPEVENTMCASP1_AXR15_WAKEUPENABLERESERVEDMCASP1_AXR15_SLEWCONTROLMCASP1_AXR15_INPUTENABLEMCASP1_AXR15_PULLTYPESELECTMCASP1_AXR15_PULLUDENABLERESERVEDMCASP1_AXR15_MODESELECTMCASP1_AXR15_DELAYMODEMCASP1_AXR15_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP1_AXR15_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP1_AXR15_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP1_AXR15_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP1_AXR15_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP1_AXR15_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP1_AXR15_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP1_AXR15_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP1_AXR15_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP1_AXR15_MUXMODERW0xF
0x0: mcasp1_axr15
0x1: mcasp7_fsx
0x2: mcasp7_fsr
0x7: vin6a_d8
0xA: timer12
0xE: gpio6_6
0xF: Driver off
Table 18-742 CTRL_CORE_PAD_MCASP2_ACLKX
Address Offset0x0000 16F4
Physical Address0x4A00 36F4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_ACLKX_WAKEUPEVENTMCASP2_ACLKX_WAKEUPENABLERESERVEDMCASP2_ACLKX_SLEWCONTROLMCASP2_ACLKX_INPUTENABLEMCASP2_ACLKX_PULLTYPESELECTMCASP2_ACLKX_PULLUDENABLERESERVEDMCASP2_ACLKX_MODESELECTMCASP2_ACLKX_DELAYMODEMCASP2_ACLKX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_ACLKX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_ACLKX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_ACLKX_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_ACLKX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_ACLKX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_ACLKX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_ACLKX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_ACLKX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_ACLKX_MUXMODERW0xF
0x0: mcasp2_aclkx
0x7: vin6a_d7
0xF: Driver off
Table 18-743 CTRL_CORE_PAD_MCASP2_FSX
Address Offset0x0000 16F8
Physical Address0x4A00 36F8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_FSX_WAKEUPEVENTMCASP2_FSX_WAKEUPENABLERESERVEDMCASP2_FSX_SLEWCONTROLMCASP2_FSX_INPUTENABLEMCASP2_FSX_PULLTYPESELECTMCASP2_FSX_PULLUDENABLERESERVEDMCASP2_FSX_MODESELECTMCASP2_FSX_DELAYMODEMCASP2_FSX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_FSX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_FSX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_FSX_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_FSX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_FSX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_FSX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_FSX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_FSX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_FSX_MUXMODERW0xF
0x0: mcasp2_fsx
0x7: vin6a_d6
0xF: Driver off
Table 18-744 CTRL_CORE_PAD_MCASP2_ACLKR
Address Offset0x0000 16FC
Physical Address0x4A00 36FCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_ACLKR_WAKEUPEVENTMCASP2_ACLKR_WAKEUPENABLERESERVEDMCASP2_ACLKR_SLEWCONTROLMCASP2_ACLKR_INPUTENABLEMCASP2_ACLKR_PULLTYPESELECTMCASP2_ACLKR_PULLUDENABLERESERVEDMCASP2_ACLKR_MODESELECTMCASP2_ACLKR_DELAYMODEMCASP2_ACLKR_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_ACLKR_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_ACLKR_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_ACLKR_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_ACLKR_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_ACLKR_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_ACLKR_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_ACLKR_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_ACLKR_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_ACLKR_MUXMODERW0xF
0x0: mcasp2_aclkr
0x1: mcasp8_axr2
0x6: vout2_d8
0x8: vin4a_d8
0xF: Driver off
Table 18-745 CTRL_CORE_PAD_MCASP2_FSR
Address Offset0x0000 1700
Physical Address0x4A00 3700InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_FSR_WAKEUPEVENTMCASP2_FSR_WAKEUPENABLERESERVEDMCASP2_FSR_SLEWCONTROLMCASP2_FSR_INPUTENABLEMCASP2_FSR_PULLTYPESELECTMCASP2_FSR_PULLUDENABLERESERVEDMCASP2_FSR_MODESELECTMCASP2_FSR_DELAYMODEMCASP2_FSR_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_FSR_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_FSR_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_FSR_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_FSR_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_FSR_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_FSR_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_FSR_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_FSR_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_FSR_MUXMODERW0xF
0x0: mcasp2_fsr
0x1: mcasp8_axr3
0x6: vout2_d9
0x8: vin4a_d9
0xF: Driver off
Table 18-746 CTRL_CORE_PAD_MCASP2_AXR0
Address Offset0x0000 1704
Physical Address0x4A00 3704InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_AXR0_WAKEUPEVENTMCASP2_AXR0_WAKEUPENABLERESERVEDMCASP2_AXR0_SLEWCONTROLMCASP2_AXR0_INPUTENABLEMCASP2_AXR0_PULLTYPESELECTMCASP2_AXR0_PULLUDENABLERESERVEDMCASP2_AXR0_MODESELECTMCASP2_AXR0_DELAYMODEMCASP2_AXR0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_AXR0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_AXR0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_AXR0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_AXR0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_AXR0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_AXR0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_AXR0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_AXR0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_AXR0_MUXMODERW0xF
0x0: mcasp2_axr0
0x6: vout2_d10
0x8: vin4a_d10
0xF: Driver off
Table 18-747 CTRL_CORE_PAD_MCASP2_AXR1
Address Offset0x0000 1708
Physical Address0x4A00 3708InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_AXR1_WAKEUPEVENTMCASP2_AXR1_WAKEUPENABLERESERVEDMCASP2_AXR1_SLEWCONTROLMCASP2_AXR1_INPUTENABLEMCASP2_AXR1_PULLTYPESELECTMCASP2_AXR1_PULLUDENABLERESERVEDMCASP2_AXR1_MODESELECTMCASP2_AXR1_DELAYMODEMCASP2_AXR1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_AXR1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_AXR1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_AXR1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_AXR1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_AXR1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_AXR1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_AXR1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_AXR1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_AXR1_MUXMODERW0xF
0x0: mcasp2_axr1
0x6: vout2_d11
0x8: vin4a_d11
0xF: Driver off
Table 18-748 CTRL_CORE_PAD_MCASP2_AXR2
Address Offset0x0000 170C
Physical Address0x4A00 370CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_AXR2_WAKEUPEVENTMCASP2_AXR2_WAKEUPENABLERESERVEDMCASP2_AXR2_SLEWCONTROLMCASP2_AXR2_INPUTENABLEMCASP2_AXR2_PULLTYPESELECTMCASP2_AXR2_PULLUDENABLERESERVEDMCASP2_AXR2_MODESELECTMCASP2_AXR2_DELAYMODEMCASP2_AXR2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_AXR2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_AXR2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_AXR2_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_AXR2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_AXR2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_AXR2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_AXR2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_AXR2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_AXR2_MUXMODERW0xF
0x0: mcasp2_axr2
0x1: mcasp3_axr2
0x7: vin6a_d5
0xE: gpio6_8
0xF: Driver off
Table 18-749 CTRL_CORE_PAD_MCASP2_AXR3
Address Offset0x0000 1710
Physical Address0x4A00 3710InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_AXR3_WAKEUPEVENTMCASP2_AXR3_WAKEUPENABLERESERVEDMCASP2_AXR3_SLEWCONTROLMCASP2_AXR3_INPUTENABLEMCASP2_AXR3_PULLTYPESELECTMCASP2_AXR3_PULLUDENABLERESERVEDMCASP2_AXR3_MODESELECTMCASP2_AXR3_DELAYMODEMCASP2_AXR3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_AXR3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_AXR3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_AXR3_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_AXR3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_AXR3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_AXR3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_AXR3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_AXR3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_AXR3_MUXMODERW0xF
0x0: mcasp2_axr3
0x1: mcasp3_axr3
0x7: vin6a_d4
0xE: gpio6_9
0xF: Driver off
Table 18-750 CTRL_CORE_PAD_MCASP2_AXR4
Address Offset0x0000 1714
Physical Address0x4A00 3714InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_AXR4_WAKEUPEVENTMCASP2_AXR4_WAKEUPENABLERESERVEDMCASP2_AXR4_SLEWCONTROLMCASP2_AXR4_INPUTENABLEMCASP2_AXR4_PULLTYPESELECTMCASP2_AXR4_PULLUDENABLERESERVEDMCASP2_AXR4_MODESELECTMCASP2_AXR4_DELAYMODEMCASP2_AXR4_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_AXR4_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_AXR4_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_AXR4_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_AXR4_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_AXR4_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_AXR4_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_AXR4_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_AXR4_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_AXR4_MUXMODERW0xF
0x0: mcasp2_axr4
0x1: mcasp8_axr0
0x6: vout2_d12
0x8: vin4a_d12
0xE: gpio1_4
0xF: Driver off
Table 18-751 CTRL_CORE_PAD_MCASP2_AXR5
Address Offset0x0000 1718
Physical Address0x4A00 3718InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_AXR5_WAKEUPEVENTMCASP2_AXR5_WAKEUPENABLERESERVEDMCASP2_AXR5_SLEWCONTROLMCASP2_AXR5_INPUTENABLEMCASP2_AXR5_PULLTYPESELECTMCASP2_AXR5_PULLUDENABLERESERVEDMCASP2_AXR5_MODESELECTMCASP2_AXR5_DELAYMODEMCASP2_AXR5_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_AXR5_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_AXR5_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_AXR5_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_AXR5_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_AXR5_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_AXR5_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_AXR5_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_AXR5_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_AXR5_MUXMODERW0xF
0x0: mcasp2_axr5
0x1: mcasp8_axr1
0x6: vout2_d13
0x8: vin4a_d13
0xE: gpio6_7
0xF: Driver off
Table 18-752 CTRL_CORE_PAD_MCASP2_AXR6
Address Offset0x0000 171C
Physical Address0x4A00 371CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_AXR6_WAKEUPEVENTMCASP2_AXR6_WAKEUPENABLERESERVEDMCASP2_AXR6_SLEWCONTROLMCASP2_AXR6_INPUTENABLEMCASP2_AXR6_PULLTYPESELECTMCASP2_AXR6_PULLUDENABLERESERVEDMCASP2_AXR6_MODESELECTMCASP2_AXR6_DELAYMODEMCASP2_AXR6_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_AXR6_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_AXR6_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_AXR6_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_AXR6_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_AXR6_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_AXR6_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_AXR6_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_AXR6_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_AXR6_MUXMODERW0xF
0x0: mcasp2_axr6
0x1: mcasp8_aclkx
0x2: mcasp8_aclkr
0x6: vout2_d14
0x8: vin4a_d14
0xE: gpio2_29
0xF: Driver off
Table 18-753 CTRL_CORE_PAD_MCASP2_AXR7
Address Offset0x0000 1720
Physical Address0x4A00 3720InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP2_AXR7_WAKEUPEVENTMCASP2_AXR7_WAKEUPENABLERESERVEDMCASP2_AXR7_SLEWCONTROLMCASP2_AXR7_INPUTENABLEMCASP2_AXR7_PULLTYPESELECTMCASP2_AXR7_PULLUDENABLERESERVEDMCASP2_AXR7_MODESELECTMCASP2_AXR7_DELAYMODEMCASP2_AXR7_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP2_AXR7_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP2_AXR7_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP2_AXR7_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP2_AXR7_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP2_AXR7_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP2_AXR7_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP2_AXR7_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP2_AXR7_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP2_AXR7_MUXMODERW0xF
0x0: mcasp2_axr7
0x1: mcasp8_fsx
0x2: mcasp8_fsr
0x6: vout2_d15
0x8: vin4a_d15
0xE: gpio1_5
0xF: Driver off
Table 18-754 CTRL_CORE_PAD_MCASP3_ACLKX
Address Offset0x0000 1724
Physical Address0x4A00 3724InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP3_ACLKX_WAKEUPEVENTMCASP3_ACLKX_WAKEUPENABLERESERVEDMCASP3_ACLKX_SLEWCONTROLMCASP3_ACLKX_INPUTENABLEMCASP3_ACLKX_PULLTYPESELECTMCASP3_ACLKX_PULLUDENABLERESERVEDMCASP3_ACLKX_MODESELECTMCASP3_ACLKX_DELAYMODEMCASP3_ACLKX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP3_ACLKX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP3_ACLKX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP3_ACLKX_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP3_ACLKX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP3_ACLKX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP3_ACLKX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP3_ACLKX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP3_ACLKX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP3_ACLKX_MUXMODERW0xF
0x0: mcasp3_aclkx
0x1: mcasp3_aclkr
0x2: mcasp2_axr12
0x3: uart7_rxd
0x7: vin6a_d3
0xE: gpio5_13
0xF: Driver off
Table 18-755 CTRL_CORE_PAD_MCASP3_FSX
Address Offset0x0000 1728
Physical Address0x4A00 3728InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP3_FSX_WAKEUPEVENTMCASP3_FSX_WAKEUPENABLERESERVEDMCASP3_FSX_SLEWCONTROLMCASP3_FSX_INPUTENABLEMCASP3_FSX_PULLTYPESELECTMCASP3_FSX_PULLUDENABLERESERVEDMCASP3_FSX_MODESELECTMCASP3_FSX_DELAYMODEMCASP3_FSX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP3_FSX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP3_FSX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP3_FSX_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP3_FSX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP3_FSX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP3_FSX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP3_FSX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP3_FSX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP3_FSX_MUXMODERW0xF
0x0: mcasp3_fsx
0x1: mcasp3_fsr
0x2: mcasp2_axr13
0x3: uart7_txd
0x7: vin6a_d2
0xE: gpio5_14
0xF: Driver off
Table 18-756 CTRL_CORE_PAD_MCASP3_AXR0
Address Offset0x0000 172C
Physical Address0x4A00 372CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP3_AXR0_WAKEUPEVENTMCASP3_AXR0_WAKEUPENABLERESERVEDMCASP3_AXR0_SLEWCONTROLMCASP3_AXR0_INPUTENABLEMCASP3_AXR0_PULLTYPESELECTMCASP3_AXR0_PULLUDENABLERESERVEDMCASP3_AXR0_MODESELECTMCASP3_AXR0_DELAYMODEMCASP3_AXR0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP3_AXR0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP3_AXR0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP3_AXR0_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP3_AXR0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP3_AXR0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP3_AXR0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP3_AXR0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP3_AXR0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP3_AXR0_MUXMODERW0xF
0x0: mcasp3_axr0
0x2: mcasp2_axr14
0x3: uart7_ctsn
0x4: uart5_rxd
0x7: vin6a_d1
0xF: Driver off
Table 18-757 CTRL_CORE_PAD_MCASP3_AXR1
Address Offset0x0000 1730
Physical Address0x4A00 3730InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP3_AXR1_WAKEUPEVENTMCASP3_AXR1_WAKEUPENABLERESERVEDMCASP3_AXR1_SLEWCONTROLMCASP3_AXR1_INPUTENABLEMCASP3_AXR1_PULLTYPESELECTMCASP3_AXR1_PULLUDENABLERESERVEDMCASP3_AXR1_MODESELECTMCASP3_AXR1_DELAYMODEMCASP3_AXR1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP3_AXR1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP3_AXR1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP3_AXR1_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP3_AXR1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP3_AXR1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP3_AXR1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP3_AXR1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP3_AXR1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP3_AXR1_MUXMODERW0xF
0x0: mcasp3_axr1
0x2: mcasp2_axr15
0x3: uart7_rtsn
0x4: uart5_txd
0x7: vin6a_d0
0x9: vin5a_fld0
0xF: Driver off
Table 18-758 CTRL_CORE_PAD_MCASP4_ACLKX
Address Offset0x0000 1734
Physical Address0x4A00 3734InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP4_ACLKX_WAKEUPEVENTMCASP4_ACLKX_WAKEUPENABLERESERVEDMCASP4_ACLKX_SLEWCONTROLMCASP4_ACLKX_INPUTENABLEMCASP4_ACLKX_PULLTYPESELECTMCASP4_ACLKX_PULLUDENABLERESERVEDMCASP4_ACLKX_MODESELECTMCASP4_ACLKX_DELAYMODEMCASP4_ACLKX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP4_ACLKX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP4_ACLKX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP4_ACLKX_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP4_ACLKX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP4_ACLKX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP4_ACLKX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP4_ACLKX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP4_ACLKX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP4_ACLKX_MUXMODERW0xF
0x0: mcasp4_aclkx
0x1: mcasp4_aclkr
0x2: spi3_sclk
0x3: uart8_rxd
0x4: i2c4_sda
0x6: vout2_d16
0x8: vin4a_d16
0x9: vin5a_d15
0xF: Driver off
Table 18-759 CTRL_CORE_PAD_MCASP4_FSX
Address Offset0x0000 1738
Physical Address0x4A00 3738InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP4_FSX_WAKEUPEVENTMCASP4_FSX_WAKEUPENABLERESERVEDMCASP4_FSX_SLEWCONTROLMCASP4_FSX_INPUTENABLEMCASP4_FSX_PULLTYPESELECTMCASP4_FSX_PULLUDENABLERESERVEDMCASP4_FSX_MODESELECTMCASP4_FSX_DELAYMODEMCASP4_FSX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP4_FSX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP4_FSX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP4_FSX_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP4_FSX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP4_FSX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP4_FSX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP4_FSX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP4_FSX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP4_FSX_MUXMODERW0xF
0x0: mcasp4_fsx
0x1: mcasp4_fsr
0x2: spi3_d1
0x3: uart8_txd
0x4: i2c4_scl
0x6: vout2_d17
0x8: vin4a_d17
0x9: vin5a_d14
0xF: Driver off
Table 18-760 CTRL_CORE_PAD_MCASP4_AXR0
Address Offset0x0000 173C
Physical Address0x4A00 373CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP4_AXR0_WAKEUPEVENTMCASP4_AXR0_WAKEUPENABLERESERVEDMCASP4_AXR0_SLEWCONTROLMCASP4_AXR0_INPUTENABLEMCASP4_AXR0_PULLTYPESELECTMCASP4_AXR0_PULLUDENABLERESERVEDMCASP4_AXR0_MODESELECTMCASP4_AXR0_DELAYMODEMCASP4_AXR0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP4_AXR0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP4_AXR0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP4_AXR0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP4_AXR0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP4_AXR0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP4_AXR0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP4_AXR0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP4_AXR0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP4_AXR0_MUXMODERW0xF
0x0: mcasp4_axr0
0x2: spi3_d0
0x3: uart8_ctsn
0x4: uart4_rxd
0x6: vout2_d18
0x8: vin4a_d18
0x9: vin5a_d13
0xF: Driver off
Table 18-761 CTRL_CORE_PAD_MCASP4_AXR1
Address Offset0x0000 1740
Physical Address0x4A00 3740InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP4_AXR1_WAKEUPEVENTMCASP4_AXR1_WAKEUPENABLERESERVEDMCASP4_AXR1_SLEWCONTROLMCASP4_AXR1_INPUTENABLEMCASP4_AXR1_PULLTYPESELECTMCASP4_AXR1_PULLUDENABLERESERVEDMCASP4_AXR1_MODESELECTMCASP4_AXR1_DELAYMODEMCASP4_AXR1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP4_AXR1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP4_AXR1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP4_AXR1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP4_AXR1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP4_AXR1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP4_AXR1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP4_AXR1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP4_AXR1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP4_AXR1_MUXMODERW0xF
0x0: mcasp4_axr1
0x2: spi3_cs0
0x3: uart8_rtsn
0x4: uart4_txd
0x6: vout2_d19
0x8: vin4a_d19
0x9: vin5a_d12
0xF: Driver off
Table 18-762 CTRL_CORE_PAD_MCASP5_ACLKX
Address Offset0x0000 1744
Physical Address0x4A00 3744InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP5_ACLKX_WAKEUPEVENTMCASP5_ACLKX_WAKEUPENABLERESERVEDMCASP5_ACLKX_SLEWCONTROLMCASP5_ACLKX_INPUTENABLEMCASP5_ACLKX_PULLTYPESELECTMCASP5_ACLKX_PULLUDENABLERESERVEDMCASP5_ACLKX_MODESELECTMCASP5_ACLKX_DELAYMODEMCASP5_ACLKX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP5_ACLKX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP5_ACLKX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP5_ACLKX_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP5_ACLKX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP5_ACLKX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP5_ACLKX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP5_ACLKX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP5_ACLKX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP5_ACLKX_MUXMODERW0xF
0x0: mcasp5_aclkx
0x1: mcasp5_aclkr
0x2: spi4_sclk
0x3: uart9_rxd
0x4: i2c5_sda
0x5: mlb_clk
0x6: vout2_d20
0x8: vin4a_d20
0x9: vin5a_d11
0xF: Driver off
Table 18-763 CTRL_CORE_PAD_MCASP5_FSX
Address Offset0x0000 1748
Physical Address0x4A00 3748InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP5_FSX_WAKEUPEVENTMCASP5_FSX_WAKEUPENABLERESERVEDMCASP5_FSX_SLEWCONTROLMCASP5_FSX_INPUTENABLEMCASP5_FSX_PULLTYPESELECTMCASP5_FSX_PULLUDENABLERESERVEDMCASP5_FSX_MODESELECTMCASP5_FSX_DELAYMODEMCASP5_FSX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP5_FSX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP5_FSX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP5_FSX_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP5_FSX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP5_FSX_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP5_FSX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP5_FSX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP5_FSX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP5_FSX_MUXMODERW0xF
0x0: mcasp5_fsx
0x1: mcasp5_fsr
0x2: spi4_d1
0x3: uart9_txd
0x4: i2c5_scl
0x6: vout2_d21
0x8: vin4a_d21
0x9: vin5a_d10
0xF: Driver off
Table 18-764 CTRL_CORE_PAD_MCASP5_AXR0
Address Offset0x0000 174C
Physical Address0x4A00 374CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP5_AXR0_WAKEUPEVENTMCASP5_AXR0_WAKEUPENABLERESERVEDMCASP5_AXR0_SLEWCONTROLMCASP5_AXR0_INPUTENABLEMCASP5_AXR0_PULLTYPESELECTMCASP5_AXR0_PULLUDENABLERESERVEDMCASP5_AXR0_MODESELECTMCASP5_AXR0_DELAYMODEMCASP5_AXR0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP5_AXR0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP5_AXR0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP5_AXR0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP5_AXR0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP5_AXR0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP5_AXR0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP5_AXR0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP5_AXR0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP5_AXR0_MUXMODERW0xF
0x0: mcasp5_axr0
0x2: spi4_d0
0x3: uart9_ctsn
0x4: uart3_rxd
0x5: mlb_sig
0x6: vout2_d22
0x8: vin4a_d22
0x9: vin5a_d9
0xF: Driver off
Table 18-765 CTRL_CORE_PAD_MCASP5_AXR1
Address Offset0x0000 1750
Physical Address0x4A00 3750InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMCASP5_AXR1_WAKEUPEVENTMCASP5_AXR1_WAKEUPENABLERESERVEDMCASP5_AXR1_SLEWCONTROLMCASP5_AXR1_INPUTENABLEMCASP5_AXR1_PULLTYPESELECTMCASP5_AXR1_PULLUDENABLERESERVEDMCASP5_AXR1_MODESELECTMCASP5_AXR1_DELAYMODEMCASP5_AXR1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MCASP5_AXR1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MCASP5_AXR1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MCASP5_AXR1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MCASP5_AXR1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MCASP5_AXR1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MCASP5_AXR1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MCASP5_AXR1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MCASP5_AXR1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MCASP5_AXR1_MUXMODERW0xF
0x0: mcasp5_axr1
0x2: spi4_cs0
0x3: uart9_rtsn
0x4: uart3_txd
0x5: mlb_dat
0x6: vout2_d23
0x8: vin4a_d23
0x9: vin5a_d8
0xF: Driver off
Table 18-766 CTRL_CORE_PAD_MMC1_CLK
Address Offset0x0000 1754
Physical Address0x4A00 3754InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC1_CLK_WAKEUPEVENTMMC1_CLK_WAKEUPENABLERESERVEDMMC1_CLK_ACTIVEMMC1_CLK_PULLTYPESELECTMMC1_CLK_PULLUDENABLERESERVEDMMC1_CLK_MODESELECTMMC1_CLK_DELAYMODEMMC1_CLK_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDReservedR0x0
25MMC1_CLK_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC1_CLK_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDReservedR0x0
18MMC1_CLK_ACTIVEControls enabling/disabling of the input buffer.
0x0: Input buffer is disabled
0x1: Input buffer is enabled		RW0x1
17MMC1_CLK_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC1_CLK_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDReservedR0x0
8MMC1_CLK_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC1_CLK_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC1_CLK_MUXMODERW0xF
0x0: mmc1_clk
0xE: gpio6_21
0xF: Driver off
Table 18-767 CTRL_CORE_PAD_MMC1_CMD
Address Offset0x0000 1758
Physical Address0x4A00 3758InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC1_CMD_WAKEUPEVENTMMC1_CMD_WAKEUPENABLERESERVEDMMC1_CMD_ACTIVEMMC1_CMD_PULLTYPESELECTMMC1_CMD_PULLUDENABLERESERVEDMMC1_CMD_MODESELECTMMC1_CMD_DELAYMODEMMC1_CMD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDReservedR0x0
25MMC1_CMD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC1_CMD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDReservedR0x0
18MMC1_CMD_ACTIVEControls enabling/disabling of the input buffer.
0x0: Input buffer is disabled
0x1: Input buffer is enabled		RW0x1
17MMC1_CMD_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC1_CMD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDReservedR0x0
8MMC1_CMD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC1_CMD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC1_CMD_MUXMODERW0xF
0x0: mmc1_cmd
0xE: gpio6_22
0xF: Driver off
Table 18-768 CTRL_CORE_PAD_MMC1_DAT0
Address Offset0x0000 175C
Physical Address0x4A00 375CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC1_DAT0_WAKEUPEVENTMMC1_DAT0_WAKEUPENABLERESERVEDMMC1_DAT0_ACTIVEMMC1_DAT0_PULLTYPESELECTMMC1_DAT0_PULLUDENABLERESERVEDMMC1_DAT0_MODESELECTMMC1_DAT0_DELAYMODEMMC1_DAT0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDReservedR0x0
25MMC1_DAT0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC1_DAT0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDReservedR0x0
18MMC1_DAT0_ACTIVEControls enabling/disabling of the input buffer.
0x0: Input buffer is disabled
0x1: Input buffer is enabled		RW0x1
17MMC1_DAT0_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC1_DAT0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDReservedR0x0
8MMC1_DAT0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC1_DAT0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC1_DAT0_MUXMODERW0xF
0x0: mmc1_dat0
0xE: gpio6_23
0xF: Driver off
Table 18-769 CTRL_CORE_PAD_MMC1_DAT1
Address Offset0x0000 1760
Physical Address0x4A00 3760InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC1_DAT1_WAKEUPEVENTMMC1_DAT1_WAKEUPENABLERESERVEDMMC1_DAT1_ACTIVEMMC1_DAT1_PULLTYPESELECTMMC1_DAT1_PULLUDENABLERESERVEDMMC1_DAT1_MODESELECTMMC1_DAT1_DELAYMODEMMC1_DAT1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDReservedR0x0
25MMC1_DAT1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC1_DAT1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDReservedR0x0
18MMC1_DAT1_ACTIVEControls enabling/disabling of the input buffer.
0x0: Input buffer is disabled
0x1: Input buffer is enabled		RW0x1
17MMC1_DAT1_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC1_DAT1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDReservedR0x0
8MMC1_DAT1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC1_DAT1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC1_DAT1_MUXMODERW0xF
0x0: mmc1_dat1
0xE: gpio6_24
0xF: Driver off
Table 18-770 CTRL_CORE_PAD_MMC1_DAT2
Address Offset0x0000 1764
Physical Address0x4A00 3764InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC1_DAT2_WAKEUPEVENTMMC1_DAT2_WAKEUPENABLERESERVEDMMC1_DAT2_ACTIVEMMC1_DAT2_PULLTYPESELECTMMC1_DAT2_PULLUDENABLERESERVEDMMC1_DAT2_MODESELECTMMC1_DAT2_DELAYMODEMMC1_DAT2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC1_DAT2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC1_DAT2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDR0x0
18MMC1_DAT2_ACTIVEControls enabling/disabling of the input buffer.
0x0: Input buffer is disabled
0x1: Input buffer is enabled		RW0x1
17MMC1_DAT2_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC1_DAT2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC1_DAT2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC1_DAT2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC1_DAT2_MUXMODERW0xF
0x0: mmc1_dat2
0xE: gpio6_25
0xF: Driver off
Table 18-771 CTRL_CORE_PAD_MMC1_DAT3
Address Offset0x0000 1768
Physical Address0x4A00 3768InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC1_DAT3_WAKEUPEVENTMMC1_DAT3_WAKEUPENABLERESERVEDMMC1_DAT3_ACTIVEMMC1_DAT3_PULLTYPESELECTMMC1_DAT3_PULLUDENABLERESERVEDMMC1_DAT3_MODESELECTMMC1_DAT3_DELAYMODEMMC1_DAT3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC1_DAT3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC1_DAT3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDR0x0
18MMC1_DAT3_ACTIVEControls enabling/disabling of the input buffer.
0x0: Input buffer is disabled
0x1: Input buffer is enabled		RW0x1
17MMC1_DAT3_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC1_DAT3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC1_DAT3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC1_DAT3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC1_DAT3_MUXMODERW0xF
0x0: mmc1_dat3
0xE: gpio6_26
0xF: Driver off
Table 18-772 CTRL_CORE_PAD_MMC1_SDCD
Address Offset0x0000 176C
Physical Address0x4A00 376CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC1_SDCD_WAKEUPEVENTMMC1_SDCD_WAKEUPENABLERESERVEDMMC1_SDCD_SLEWCONTROLMMC1_SDCD_INPUTENABLEMMC1_SDCD_PULLTYPESELECTMMC1_SDCD_PULLUDENABLERESERVEDMMC1_SDCD_MODESELECTMMC1_SDCD_DELAYMODEMMC1_SDCD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC1_SDCD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC1_SDCD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC1_SDCD_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC1_SDCD_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC1_SDCD_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC1_SDCD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC1_SDCD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC1_SDCD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC1_SDCD_MUXMODERW0xF
0x0: mmc1_sdcd
0x3: uart6_rxd
0x4: i2c4_sda
0xE: gpio6_27
0xF: Driver off
Table 18-773 CTRL_CORE_PAD_MMC1_SDWP
Address Offset0x0000 1770
Physical Address0x4A00 3770InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC1_SDWP_WAKEUPEVENTMMC1_SDWP_WAKEUPENABLERESERVEDMMC1_SDWP_SLEWCONTROLMMC1_SDWP_INPUTENABLEMMC1_SDWP_PULLTYPESELECTMMC1_SDWP_PULLUDENABLERESERVEDMMC1_SDWP_MODESELECTMMC1_SDWP_DELAYMODEMMC1_SDWP_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC1_SDWP_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC1_SDWP_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC1_SDWP_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC1_SDWP_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC1_SDWP_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC1_SDWP_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC1_SDWP_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC1_SDWP_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC1_SDWP_MUXMODERW0xF
0x0: mmc1_sdwp
0x3: uart6_txd
0x4: i2c4_scl
0xE: gpio6_28
0xF: Driver off
Table 18-774 CTRL_CORE_PAD_GPIO6_10
Address Offset0x0000 1774
Physical Address0x4A00 3774InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPIO6_10_WAKEUPEVENTGPIO6_10_WAKEUPENABLERESERVEDGPIO6_10_SLEWCONTROLGPIO6_10_INPUTENABLEGPIO6_10_PULLTYPESELECTGPIO6_10_PULLUDENABLERESERVEDGPIO6_10_MODESELECTGPIO6_10_DELAYMODEGPIO6_10_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPIO6_10_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPIO6_10_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPIO6_10_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPIO6_10_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPIO6_10_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPIO6_10_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPIO6_10_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPIO6_10_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPIO6_10_MUXMODERW0xF
0x0: gpio6_10
0x1: mdio_mclk
0x2: i2c3_sda
0x3: usb3_ulpi_d7
0x4: vin2b_hsync1
0x9: vin5a_clk0
0xA: ehrpwm2A
0xE: gpio6_10
0xF: Driver off
Table 18-775 CTRL_CORE_PAD_GPIO6_11
Address Offset0x0000 1778
Physical Address0x4A00 3778InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDGPIO6_11_WAKEUPEVENTGPIO6_11_WAKEUPENABLERESERVEDGPIO6_11_SLEWCONTROLGPIO6_11_INPUTENABLEGPIO6_11_PULLTYPESELECTGPIO6_11_PULLUDENABLERESERVEDGPIO6_11_MODESELECTGPIO6_11_DELAYMODEGPIO6_11_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25GPIO6_11_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24GPIO6_11_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19GPIO6_11_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18GPIO6_11_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17GPIO6_11_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16GPIO6_11_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8GPIO6_11_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4GPIO6_11_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0GPIO6_11_MUXMODERW0xF
0x0: gpio6_11
0x1: mdio_d
0x2: i2c3_scl
0x3: usb3_ulpi_d6
0x4: vin2b_vsync1
0x9: vin5a_de0
0xA: ehrpwm2B
0xE: gpio6_11
0xF: Driver off
Table 18-776 CTRL_CORE_PAD_MMC3_CLK
Address Offset0x0000 177C
Physical Address0x4A00 377CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_CLK_WAKEUPEVENTMMC3_CLK_WAKEUPENABLERESERVEDMMC3_CLK_SLEWCONTROLMMC3_CLK_INPUTENABLEMMC3_CLK_PULLTYPESELECTMMC3_CLK_PULLUDENABLERESERVEDMMC3_CLK_MODESELECTMMC3_CLK_DELAYMODEMMC3_CLK_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_CLK_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_CLK_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_CLK_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_CLK_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_CLK_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_CLK_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_CLK_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_CLK_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_CLK_MUXMODERW0xF
0x0: mmc3_clk
0x3: usb3_ulpi_d5
0x4: vin2b_d7
0x9: vin5a_d7
0xA: ehrpwm2_tripzone_input
0xE: gpio6_29
0xF: Driver off
Table 18-777 CTRL_CORE_PAD_MMC3_CMD
Address Offset0x0000 1780
Physical Address0x4A00 3780InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_CMD_WAKEUPEVENTMMC3_CMD_WAKEUPENABLERESERVEDMMC3_CMD_SLEWCONTROLMMC3_CMD_INPUTENABLEMMC3_CMD_PULLTYPESELECTMMC3_CMD_PULLUDENABLERESERVEDMMC3_CMD_MODESELECTMMC3_CMD_DELAYMODEMMC3_CMD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_CMD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_CMD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_CMD_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_CMD_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_CMD_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_CMD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_CMD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_CMD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_CMD_MUXMODERW0xF
0x0: mmc3_cmd
0x1: spi3_sclk
0x3: usb3_ulpi_d4
0x4: vin2b_d6
0x9: vin5a_d6
0xA: eCAP2_in_PWM2_out
0xE: gpio6_30
0xF: Driver off
Table 18-778 CTRL_CORE_PAD_MMC3_DAT0
Address Offset0x0000 1784
Physical Address0x4A00 3784InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_DAT0_WAKEUPEVENTMMC3_DAT0_WAKEUPENABLERESERVEDMMC3_DAT0_SLEWCONTROLMMC3_DAT0_INPUTENABLEMMC3_DAT0_PULLTYPESELECTMMC3_DAT0_PULLUDENABLERESERVEDMMC3_DAT0_MODESELECTMMC3_DAT0_DELAYMODEMMC3_DAT0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_DAT0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_DAT0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_DAT0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_DAT0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_DAT0_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_DAT0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_DAT0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_DAT0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_DAT0_MUXMODERW0xF
0x0: mmc3_dat0
0x1: spi3_d1
0x2: uart5_rxd
0x3: usb3_ulpi_d3
0x4: vin2b_d5
0x9: vin5a_d5
0xA: eQEP3A_in
0xE: gpio6_31
0xF: Driver off
Table 18-779 CTRL_CORE_PAD_MMC3_DAT1
Address Offset0x0000 1788
Physical Address0x4A00 3788InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_DAT1_WAKEUPEVENTMMC3_DAT1_WAKEUPENABLERESERVEDMMC3_DAT1_SLEWCONTROLMMC3_DAT1_INPUTENABLEMMC3_DAT1_PULLTYPESELECTMMC3_DAT1_PULLUDENABLERESERVEDMMC3_DAT1_MODESELECTMMC3_DAT1_DELAYMODEMMC3_DAT1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_DAT1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_DAT1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_DAT1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_DAT1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_DAT1_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_DAT1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_DAT1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_DAT1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_DAT1_MUXMODERW0xF
0x0: mmc3_dat1
0x1: spi3_d0
0x2: uart5_txd
0x3: usb3_ulpi_d2
0x4: vin2b_d4
0x9: vin5a_d4
0xA: eQEP3B_in
0xE: gpio7_0
0xF: Driver off
Table 18-780 CTRL_CORE_PAD_MMC3_DAT2
Address Offset0x0000 178C
Physical Address0x4A00 378CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_DAT2_WAKEUPEVENTMMC3_DAT2_WAKEUPENABLERESERVEDMMC3_DAT2_SLEWCONTROLMMC3_DAT2_INPUTENABLEMMC3_DAT2_PULLTYPESELECTMMC3_DAT2_PULLUDENABLERESERVEDMMC3_DAT2_MODESELECTMMC3_DAT2_DELAYMODEMMC3_DAT2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_DAT2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_DAT2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_DAT2_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_DAT2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_DAT2_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_DAT2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_DAT2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_DAT2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_DAT2_MUXMODERW0xF
0x0: mmc3_dat2
0x1: spi3_cs0
0x2: uart5_ctsn
0x3: usb3_ulpi_d1
0x4: vin2b_d3
0x9: vin5a_d3
0xA: eQEP3_index
0xE: gpio7_1
0xF: Driver off
Table 18-781 CTRL_CORE_PAD_MMC3_DAT3
Address Offset0x0000 1790
Physical Address0x4A00 3790InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_DAT3_WAKEUPEVENTMMC3_DAT3_WAKEUPENABLERESERVEDMMC3_DAT3_SLEWCONTROLMMC3_DAT3_INPUTENABLEMMC3_DAT3_PULLTYPESELECTMMC3_DAT3_PULLUDENABLERESERVEDMMC3_DAT3_MODESELECTMMC3_DAT3_DELAYMODEMMC3_DAT3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_DAT3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_DAT3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_DAT3_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_DAT3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_DAT3_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_DAT3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_DAT3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_DAT3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_DAT3_MUXMODERW0xF
0x0: mmc3_dat3
0x1: spi3_cs1
0x2: uart5_rtsn
0x3: usb3_ulpi_d0
0x4: vin2b_d2
0x9: vin5a_d2
0xA: eQEP3_strobe
0xE: gpio7_2
0xF: Driver off
Table 18-782 CTRL_CORE_PAD_MMC3_DAT4
Address Offset0x0000 1794
Physical Address0x4A00 3794InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_DAT4_WAKEUPEVENTMMC3_DAT4_WAKEUPENABLERESERVEDMMC3_DAT4_SLEWCONTROLMMC3_DAT4_INPUTENABLEMMC3_DAT4_PULLTYPESELECTMMC3_DAT4_PULLUDENABLERESERVEDMMC3_DAT4_MODESELECTMMC3_DAT4_DELAYMODEMMC3_DAT4_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_DAT4_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_DAT4_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_DAT4_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_DAT4_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_DAT4_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_DAT4_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_DAT4_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_DAT4_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_DAT4_MUXMODERW0xF
0x0: mmc3_dat4
0x1: spi4_sclk
0x2: uart10_rxd
0x3: usb3_ulpi_nxt
0x4: vin2b_d1
0x9: vin5a_d1
0xA: ehrpwm3A
0xE: gpio1_22
0xF: Driver off
Table 18-783 CTRL_CORE_PAD_MMC3_DAT5
Address Offset0x0000 1798
Physical Address0x4A00 3798InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_DAT5_WAKEUPEVENTMMC3_DAT5_WAKEUPENABLERESERVEDMMC3_DAT5_SLEWCONTROLMMC3_DAT5_INPUTENABLEMMC3_DAT5_PULLTYPESELECTMMC3_DAT5_PULLUDENABLERESERVEDMMC3_DAT5_MODESELECTMMC3_DAT5_DELAYMODEMMC3_DAT5_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_DAT5_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_DAT5_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_DAT5_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_DAT5_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_DAT5_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_DAT5_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_DAT5_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_DAT5_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_DAT5_MUXMODERW0xF
0x0: mmc3_dat5
0x1: spi4_d1
0x2: uart10_txd
0x3: usb3_ulpi_dir
0x4: vin2b_d0
0x9: vin5a_d0
0xA: ehrpwm3B
0xE: gpio1_23
0xF: Driver off
Table 18-784 CTRL_CORE_PAD_MMC3_DAT6
Address Offset0x0000 179C
Physical Address0x4A00 379CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_DAT6_WAKEUPEVENTMMC3_DAT6_WAKEUPENABLERESERVEDMMC3_DAT6_SLEWCONTROLMMC3_DAT6_INPUTENABLEMMC3_DAT6_PULLTYPESELECTMMC3_DAT6_PULLUDENABLERESERVEDMMC3_DAT6_MODESELECTMMC3_DAT6_DELAYMODEMMC3_DAT6_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_DAT6_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_DAT6_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_DAT6_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_DAT6_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_DAT6_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_DAT6_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_DAT6_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_DAT6_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_DAT6_MUXMODERW0xF
0x0: mmc3_dat6
0x1: spi4_d0
0x2: uart10_ctsn
0x3: usb3_ulpi_stp
0x4: vin2b_de1
0x9: vin5a_hsync0
0xA: ehrpwm3_tripzone_input
0xE: gpio1_24
0xF: Driver off
Table 18-785 CTRL_CORE_PAD_MMC3_DAT7
Address Offset0x0000 17A0
Physical Address0x4A00 37A0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMC3_DAT7_WAKEUPEVENTMMC3_DAT7_WAKEUPENABLERESERVEDMMC3_DAT7_SLEWCONTROLMMC3_DAT7_INPUTENABLEMMC3_DAT7_PULLTYPESELECTMMC3_DAT7_PULLUDENABLERESERVEDMMC3_DAT7_MODESELECTMMC3_DAT7_DELAYMODEMMC3_DAT7_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25MMC3_DAT7_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24MMC3_DAT7_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19MMC3_DAT7_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18MMC3_DAT7_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17MMC3_DAT7_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16MMC3_DAT7_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8MMC3_DAT7_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4MMC3_DAT7_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0MMC3_DAT7_MUXMODERW0xF
0x0: mmc3_dat7
0x1: spi4_cs0
0x2: uart10_rtsn
0x3: usb3_ulpi_clk
0x4: vin2b_clk1
0x9: vin5a_vsync0
0xA: eCAP3_in_PWM3_out
0xE: gpio1_25
0xF: Driver off
Table 18-786 CTRL_CORE_PAD_SPI1_SCLK
Address Offset0x0000 17A4
Physical Address0x4A00 37A4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI1_SCLK_WAKEUPEVENTSPI1_SCLK_WAKEUPENABLERESERVEDSPI1_SCLK_SLEWCONTROLSPI1_SCLK_INPUTENABLESPI1_SCLK_PULLTYPESELECTSPI1_SCLK_PULLUDENABLERESERVEDSPI1_SCLK_MODESELECTSPI1_SCLK_DELAYMODESPI1_SCLK_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI1_SCLK_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI1_SCLK_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI1_SCLK_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI1_SCLK_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI1_SCLK_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI1_SCLK_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI1_SCLK_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI1_SCLK_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI1_SCLK_MUXMODERW0xF
0x0: spi1_sclk
0xE: gpio7_7
0xF: Driver off
Table 18-787 CTRL_CORE_PAD_SPI1_D1
Address Offset0x0000 17A8
Physical Address0x4A00 37A8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI1_D1_WAKEUPEVENTSPI1_D1_WAKEUPENABLERESERVEDSPI1_D1_SLEWCONTROLSPI1_D1_INPUTENABLESPI1_D1_PULLTYPESELECTSPI1_D1_PULLUDENABLERESERVEDSPI1_D1_MODESELECTSPI1_D1_DELAYMODESPI1_D1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI1_D1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI1_D1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI1_D1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI1_D1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI1_D1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI1_D1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI1_D1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI1_D1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI1_D1_MUXMODERW0xF
0x0: spi1_d1
0xE: gpio7_8
0xF: Driver off
Table 18-788 CTRL_CORE_PAD_SPI1_D0
Address Offset0x0000 17AC
Physical Address0x4A00 37ACInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI1_D0_WAKEUPEVENTSPI1_D0_WAKEUPENABLERESERVEDSPI1_D0_SLEWCONTROLSPI1_D0_INPUTENABLESPI1_D0_PULLTYPESELECTSPI1_D0_PULLUDENABLERESERVEDSPI1_D0_MODESELECTSPI1_D0_DELAYMODESPI1_D0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI1_D0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI1_D0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI1_D0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI1_D0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI1_D0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI1_D0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI1_D0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI1_D0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI1_D0_MUXMODERW0xF
0x0: spi1_d0
0xE: gpio7_9
0xF: Driver off
Table 18-789 CTRL_CORE_PAD_SPI1_CS0
Address Offset0x0000 17B0
Physical Address0x4A00 37B0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI1_CS0_WAKEUPEVENTSPI1_CS0_WAKEUPENABLERESERVEDSPI1_CS0_SLEWCONTROLSPI1_CS0_INPUTENABLESPI1_CS0_PULLTYPESELECTSPI1_CS0_PULLUDENABLERESERVEDSPI1_CS0_MODESELECTSPI1_CS0_DELAYMODESPI1_CS0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI1_CS0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI1_CS0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI1_CS0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI1_CS0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI1_CS0_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI1_CS0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI1_CS0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI1_CS0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI1_CS0_MUXMODERW0xF
0x0: spi1_cs0
0xE: gpio7_10
0xF: Driver off
Table 18-790 CTRL_CORE_PAD_SPI1_CS1
Address Offset0x0000 17B4
Physical Address0x4A00 37B4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI1_CS1_WAKEUPEVENTSPI1_CS1_WAKEUPENABLERESERVEDSPI1_CS1_SLEWCONTROLSPI1_CS1_INPUTENABLESPI1_CS1_PULLTYPESELECTSPI1_CS1_PULLUDENABLERESERVEDSPI1_CS1_MODESELECTSPI1_CS1_DELAYMODESPI1_CS1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI1_CS1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI1_CS1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI1_CS1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI1_CS1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI1_CS1_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI1_CS1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI1_CS1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI1_CS1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI1_CS1_MUXMODERW0xF
0x0: spi1_cs1
0x2: sata1_led
0x3: spi2_cs1
0xE: gpio7_11
0xF: Driver off
Table 18-791 CTRL_CORE_PAD_SPI1_CS2
Address Offset0x0000 17B8
Physical Address0x4A00 37B8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI1_CS2_WAKEUPEVENTSPI1_CS2_WAKEUPENABLERESERVEDSPI1_CS2_SLEWCONTROLSPI1_CS2_INPUTENABLESPI1_CS2_PULLTYPESELECTSPI1_CS2_PULLUDENABLERESERVEDSPI1_CS2_MODESELECTSPI1_CS2_DELAYMODESPI1_CS2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI1_CS2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI1_CS2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI1_CS2_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI1_CS2_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI1_CS2_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI1_CS2_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI1_CS2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI1_CS2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI1_CS2_MUXMODERW0xF
0x0: spi1_cs2
0x1: uart4_rxd
0x2: mmc3_sdcd
0x3: spi2_cs2
0x4: dcan2_tx
0x5: mdio_mclk
0x6: hdmi1_hpd
0xE: gpio7_12
0xF: Driver off
Table 18-792 CTRL_CORE_PAD_SPI1_CS3
Address Offset0x0000 17BC
Physical Address0x4A00 37BCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI1_CS3_WAKEUPEVENTSPI1_CS3_WAKEUPENABLERESERVEDSPI1_CS3_SLEWCONTROLSPI1_CS3_INPUTENABLESPI1_CS3_PULLTYPESELECTSPI1_CS3_PULLUDENABLERESERVEDSPI1_CS3_MODESELECTSPI1_CS3_DELAYMODESPI1_CS3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI1_CS3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI1_CS3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI1_CS3_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI1_CS3_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI1_CS3_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI1_CS3_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI1_CS3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI1_CS3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI1_CS3_MUXMODERW0xF
0x0: spi1_cs3
0x1: uart4_txd
0x2: mmc3_sdwp
0x3: spi2_cs3
0x4: dcan2_rx
0x5: mdio_d
0x6: hdmi1_cec
0xE: gpio7_13
0xF: Driver off
Table 18-793 CTRL_CORE_PAD_SPI2_SCLK
Address Offset0x0000 17C0
Physical Address0x4A00 37C0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI2_SCLK_WAKEUPEVENTSPI2_SCLK_WAKEUPENABLERESERVEDSPI2_SCLK_SLEWCONTROLSPI2_SCLK_INPUTENABLESPI2_SCLK_PULLTYPESELECTSPI2_SCLK_PULLUDENABLERESERVEDSPI2_SCLK_MODESELECTSPI2_SCLK_DELAYMODESPI2_SCLK_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI2_SCLK_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI2_SCLK_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI2_SCLK_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI2_SCLK_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI2_SCLK_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI2_SCLK_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI2_SCLK_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI2_SCLK_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI2_SCLK_MUXMODERW0xF
0x0: spi2_sclk
0x1: uart3_rxd
0xE: gpio7_14
0xF: Driver off
Table 18-794 CTRL_CORE_PAD_SPI2_D1
Address Offset0x0000 17C4
Physical Address0x4A00 37C4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI2_D1_WAKEUPEVENTSPI2_D1_WAKEUPENABLERESERVEDSPI2_D1_SLEWCONTROLSPI2_D1_INPUTENABLESPI2_D1_PULLTYPESELECTSPI2_D1_PULLUDENABLERESERVEDSPI2_D1_MODESELECTSPI2_D1_DELAYMODESPI2_D1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI2_D1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI2_D1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI2_D1_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI2_D1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI2_D1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI2_D1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI2_D1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI2_D1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI2_D1_MUXMODERW0xF
0x0: spi2_d1
0x1: uart3_txd
0xE: gpio7_15
0xF: Driver off
Table 18-795 CTRL_CORE_PAD_SPI2_D0
Address Offset0x0000 17C8
Physical Address0x4A00 37C8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI2_D0_WAKEUPEVENTSPI2_D0_WAKEUPENABLERESERVEDSPI2_D0_SLEWCONTROLSPI2_D0_INPUTENABLESPI2_D0_PULLTYPESELECTSPI2_D0_PULLUDENABLERESERVEDSPI2_D0_MODESELECTSPI2_D0_DELAYMODESPI2_D0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI2_D0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI2_D0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI2_D0_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI2_D0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI2_D0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI2_D0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI2_D0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI2_D0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI2_D0_MUXMODERW0xF
0x0: spi2_d0
0x1: uart3_ctsn
0x2: uart5_rxd
0xE: gpio7_16
0xF: Driver off
Table 18-796 CTRL_CORE_PAD_SPI2_CS0
Address Offset0x0000 17CC
Physical Address0x4A00 37CCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSPI2_CS0_WAKEUPEVENTSPI2_CS0_WAKEUPENABLERESERVEDSPI2_CS0_SLEWCONTROLSPI2_CS0_INPUTENABLESPI2_CS0_PULLTYPESELECTSPI2_CS0_PULLUDENABLERESERVEDSPI2_CS0_MODESELECTSPI2_CS0_DELAYMODESPI2_CS0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25SPI2_CS0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24SPI2_CS0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19SPI2_CS0_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18SPI2_CS0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17SPI2_CS0_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16SPI2_CS0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8SPI2_CS0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4SPI2_CS0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0SPI2_CS0_MUXMODERW0xF
0x0: spi2_cs0
0x1: uart3_rtsn
0x2: uart5_txd
0xE: gpio7_17
0xF: Driver off
Table 18-797 CTRL_CORE_PAD_DCAN1_TX
Address Offset0x0000 17D0
Physical Address0x4A00 37D0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDCAN1_TX_WAKEUPEVENTDCAN1_TX_WAKEUPENABLERESERVEDDCAN1_TX_SLEWCONTROLDCAN1_TX_INPUTENABLEDCAN1_TX_PULLTYPESELECTDCAN1_TX_PULLUDENABLERESERVEDDCAN1_TX_MODESELECTDCAN1_TX_DELAYMODEDCAN1_TX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25DCAN1_TX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24DCAN1_TX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19DCAN1_TX_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18DCAN1_TX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17DCAN1_TX_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16DCAN1_TX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8DCAN1_TX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4DCAN1_TX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0DCAN1_TX_MUXMODERW0xF
0x0: dcan1_tx
0x2: uart8_rxd
0x3: mmc2_sdcd
0x6: hdmi1_hpd
0xE: gpio1_14
0xF: Driver off
Table 18-798 CTRL_CORE_PAD_DCAN1_RX
Address Offset0x0000 17D4
Physical Address0x4A00 37D4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDCAN1_RX_WAKEUPEVENTDCAN1_RX_WAKEUPENABLERESERVEDDCAN1_RX_SLEWCONTROLDCAN1_RX_INPUTENABLEDCAN1_RX_PULLTYPESELECTDCAN1_RX_PULLUDENABLERESERVEDDCAN1_RX_MODESELECTDCAN1_RX_DELAYMODEDCAN1_RX_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25DCAN1_RX_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24DCAN1_RX_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19DCAN1_RX_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18DCAN1_RX_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17DCAN1_RX_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16DCAN1_RX_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8DCAN1_RX_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4DCAN1_RX_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0DCAN1_RX_MUXMODERW0xF
0x0: dcan1_rx
0x2: uart8_txd
0x3: mmc2_sdwp
0x4: sata1_led
0x6: hdmi1_cec
0xE: gpio1_15
0xF: Driver off
Table 18-799 CTRL_CORE_PAD_UART1_RXD
Address Offset0x0000 17E0
Physical Address0x4A00 37E0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART1_RXD_WAKEUPEVENTUART1_RXD_WAKEUPENABLERESERVEDUART1_RXD_SLEWCONTROLUART1_RXD_INPUTENABLEUART1_RXD_PULLTYPESELECTUART1_RXD_PULLUDENABLERESERVEDUART1_RXD_MODESELECTUART1_RXD_DELAYMODEUART1_RXD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART1_RXD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART1_RXD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART1_RXD_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART1_RXD_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART1_RXD_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART1_RXD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART1_RXD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART1_RXD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART1_RXD_MUXMODERW0xF
0x0: uart1_rxd
0x3: mmc4_sdcd
0xE: gpio7_22
0xF: Driver off
Table 18-800 CTRL_CORE_PAD_UART1_TXD
Address Offset0x0000 17E4
Physical Address0x4A00 37E4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART1_TXD_WAKEUPEVENTUART1_TXD_WAKEUPENABLERESERVEDUART1_TXD_SLEWCONTROLUART1_TXD_INPUTENABLEUART1_TXD_PULLTYPESELECTUART1_TXD_PULLUDENABLERESERVEDUART1_TXD_MODESELECTUART1_TXD_DELAYMODEUART1_TXD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART1_TXD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART1_TXD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART1_TXD_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART1_TXD_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART1_TXD_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART1_TXD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART1_TXD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART1_TXD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART1_TXD_MUXMODERW0xF
0x0: uart1_txd
0x3: mmc4_sdwp
0xE: gpio7_23
0xF: Driver off
Table 18-801 CTRL_CORE_PAD_UART1_CTSN
Address Offset0x0000 17E8
Physical Address0x4A00 37E8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART1_CTSN_WAKEUPEVENTUART1_CTSN_WAKEUPENABLERESERVEDUART1_CTSN_SLEWCONTROLUART1_CTSN_INPUTENABLEUART1_CTSN_PULLTYPESELECTUART1_CTSN_PULLUDENABLERESERVEDUART1_CTSN_MODESELECTUART1_CTSN_DELAYMODEUART1_CTSN_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART1_CTSN_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART1_CTSN_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART1_CTSN_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART1_CTSN_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART1_CTSN_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART1_CTSN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART1_CTSN_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART1_CTSN_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART1_CTSN_MUXMODERW0xF
0x0: uart1_ctsn
0x2: uart9_rxd
0x3: mmc4_clk
0xE: gpio7_24
0xF: Driver off
Table 18-802 CTRL_CORE_PAD_UART1_RTSN
Address Offset0x0000 17EC
Physical Address0x4A00 37ECInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART1_RTSN_WAKEUPEVENTUART1_RTSN_WAKEUPENABLERESERVEDUART1_RTSN_SLEWCONTROLUART1_RTSN_INPUTENABLEUART1_RTSN_PULLTYPESELECTUART1_RTSN_PULLUDENABLERESERVEDUART1_RTSN_MODESELECTUART1_RTSN_DELAYMODEUART1_RTSN_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART1_RTSN_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART1_RTSN_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART1_RTSN_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART1_RTSN_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART1_RTSN_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART1_RTSN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART1_RTSN_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART1_RTSN_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART1_RTSN_MUXMODERW0xF
0x0: uart1_rtsn
0x2: uart9_txd
0x3: mmc4_cmd
0xE: gpio7_25
0xF: Driver off
Table 18-803 CTRL_CORE_PAD_UART2_RXD
Address Offset0x0000 17F0
Physical Address0x4A00 37F0InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART2_RXD_WAKEUPEVENTUART2_RXD_WAKEUPENABLERESERVEDUART2_RXD_SLEWCONTROLUART2_RXD_INPUTENABLEUART2_RXD_PULLTYPESELECTUART2_RXD_PULLUDENABLERESERVEDUART2_RXD_MODESELECTUART2_RXD_DELAYMODEUART2_RXD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART2_RXD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART2_RXD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART2_RXD_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART2_RXD_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART2_RXD_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART2_RXD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART2_RXD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART2_RXD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART2_RXD_MUXMODERW0xF
0x0: Reserved
0x1: uart3_ctsn
0x2: uart3_rctx
0x3: mmc4_dat0
0x4: uart2_rxd
0x5: uart1_dcdn
0xE: gpio7_26
0xF: Driver off
Table 18-804 CTRL_CORE_PAD_UART2_TXD
Address Offset0x0000 17F4
Physical Address0x4A00 37F4InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART2_TXD_WAKEUPEVENTUART2_TXD_WAKEUPENABLERESERVEDUART2_TXD_SLEWCONTROLUART2_TXD_INPUTENABLEUART2_TXD_PULLTYPESELECTUART2_TXD_PULLUDENABLERESERVEDUART2_TXD_MODESELECTUART2_TXD_DELAYMODEUART2_TXD_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART2_TXD_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART2_TXD_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART2_TXD_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART2_TXD_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART2_TXD_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART2_TXD_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART2_TXD_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART2_TXD_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART2_TXD_MUXMODERW0xF
0x0: uart2_txd
0x1: uart3_rtsn
0x2: uart3_sd
0x3: mmc4_dat1
0x4: uart2_txd
0x5: uart1_dsrn
0xE: gpio7_27
0xF: Driver off
Table 18-805 CTRL_CORE_PAD_UART2_CTSN
Address Offset0x0000 17F8
Physical Address0x4A00 37F8InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART2_CTSN_WAKEUPEVENTUART2_CTSN_WAKEUPENABLERESERVEDUART2_CTSN_SLEWCONTROLUART2_CTSN_INPUTENABLEUART2_CTSN_PULLTYPESELECTUART2_CTSN_PULLUDENABLERESERVEDUART2_CTSN_MODESELECTUART2_CTSN_DELAYMODEUART2_CTSN_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART2_CTSN_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART2_CTSN_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART2_CTSN_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART2_CTSN_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART2_CTSN_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART2_CTSN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART2_CTSN_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART2_CTSN_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART2_CTSN_MUXMODERW0xF
0x0: uart2_ctsn
0x2: uart3_rxd
0x3: mmc4_dat2
0x4: uart10_rxd
0x5: uart1_dtrn
0xE: gpio1_16
0xF: Driver off
Table 18-806 CTRL_CORE_PAD_UART2_RTSN
Address Offset0x0000 17FC
Physical Address0x4A00 37FCInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDUART2_RTSN_WAKEUPEVENTUART2_RTSN_WAKEUPENABLERESERVEDUART2_RTSN_SLEWCONTROLUART2_RTSN_INPUTENABLEUART2_RTSN_PULLTYPESELECTUART2_RTSN_PULLUDENABLERESERVEDUART2_RTSN_MODESELECTUART2_RTSN_DELAYMODEUART2_RTSN_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25UART2_RTSN_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24UART2_RTSN_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19UART2_RTSN_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18UART2_RTSN_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17UART2_RTSN_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16UART2_RTSN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8UART2_RTSN_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4UART2_RTSN_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0UART2_RTSN_MUXMODERW0xF
0x0: uart2_rtsn
0x1: uart3_txd
0x2: uart3_irtx
0x3: mmc4_dat3
0x4: uart10_txd
0x5: uart1_rin
0xE: gpio1_17
0xF: Driver off
Table 18-807 CTRL_CORE_PAD_I2C1_SDA
Address Offset0x0000 1800
Physical Address0x4A00 3800InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDI2C1_SDA_WAKEUPEVENTI2C1_SDA_WAKEUPENABLERESERVEDI2C1_SDA_INPUTENABLEI2C1_SDA_PULLTYPESELECTI2C1_SDA_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25I2C1_SDA_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24I2C1_SDA_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDR0x0
18I2C1_SDA_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17I2C1_SDA_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16I2C1_SDA_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-808 CTRL_CORE_PAD_I2C1_SCL
Address Offset0x0000 1804
Physical Address0x4A00 3804InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDI2C1_SCL_WAKEUPEVENTI2C1_SCL_WAKEUPENABLERESERVEDI2C1_SCL_INPUTENABLEI2C1_SCL_PULLTYPESELECTI2C1_SCL_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25I2C1_SCL_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24I2C1_SCL_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDR0x0
18I2C1_SCL_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17I2C1_SCL_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16I2C1_SCL_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-809 CTRL_CORE_PAD_I2C2_SDA
Address Offset0x0000 1808
Physical Address0x4A00 3808InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDI2C2_SDA_WAKEUPEVENTI2C2_SDA_WAKEUPENABLERESERVEDI2C2_SDA_INPUTENABLEI2C2_SDA_PULLTYPESELECTI2C2_SDA_PULLUDENABLERESERVEDI2C2_SDA_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25I2C2_SDA_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24I2C2_SDA_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDR0x0
18I2C2_SDA_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17I2C2_SDA_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16I2C2_SDA_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:4RESERVEDR0x0
3:0I2C2_SDA_MUXMODERW0xF
0x0: i2c2_sda
0x1: hdmi1_ddc_scl
0xF: Driver off
Table 18-810 CTRL_CORE_PAD_I2C2_SCL
Address Offset0x0000 180C
Physical Address0x4A00 380CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDI2C2_SCL_WAKEUPEVENTI2C2_SCL_WAKEUPENABLERESERVEDI2C2_SCL_INPUTENABLEI2C2_SCL_PULLTYPESELECTI2C2_SCL_PULLUDENABLERESERVEDI2C2_SCL_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25I2C2_SCL_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24I2C2_SCL_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:19RESERVEDR0x0
18I2C2_SCL_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17I2C2_SCL_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16I2C2_SCL_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:4RESERVEDR0x0
3:0I2C2_SCL_MUXMODERW0xF
0x0: i2c2_scl
0x1: hdmi1_ddc_sda
0xF: Driver off
Table 18-811 CTRL_CORE_PAD_WAKEUP0
Address Offset0x0000 1818
Physical Address0x4A00 3818InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDWAKEUP0_WAKEUPEVENTWAKEUP0_WAKEUPENABLERESERVEDWAKEUP0_PULLTYPESELECTWAKEUP0_PULLUDENABLERESERVEDWAKEUP0_MODESELECTWAKEUP0_DELAYMODEWAKEUP0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25WAKEUP0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24WAKEUP0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:18RESERVEDR0x0
17WAKEUP0_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16WAKEUP0_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8WAKEUP0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4WAKEUP0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0WAKEUP0_MUXMODERW0xF
0x0: Wakeup0
0x1: dcan1_rx
0xE: gpio1_0
0xF: Driver off
Table 18-812 CTRL_CORE_PAD_WAKEUP1
Address Offset0x0000 181C
Physical Address0x4A00 381CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDWAKEUP1_WAKEUPEVENTWAKEUP1_WAKEUPENABLERESERVEDWAKEUP1_PULLTYPESELECTWAKEUP1_PULLUDENABLERESERVEDWAKEUP1_MODESELECTWAKEUP1_DELAYMODEWAKEUP1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25WAKEUP1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24WAKEUP1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:18RESERVEDR0x0
17WAKEUP1_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16WAKEUP1_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8WAKEUP1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4WAKEUP1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0WAKEUP1_MUXMODERW0xF
0x0: Wakeup1
0x1: dcan2_rx
0xE: gpio1_1
0xF: Driver off
Table 18-813 CTRL_CORE_PAD_WAKEUP2
Address Offset0x0000 1820
Physical Address0x4A00 3820InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDWAKEUP2_WAKEUPEVENTWAKEUP2_WAKEUPENABLERESERVEDWAKEUP2_PULLTYPESELECTWAKEUP2_PULLUDENABLERESERVEDWAKEUP2_MODESELECTWAKEUP2_DELAYMODEWAKEUP2_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25WAKEUP2_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24WAKEUP2_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:18RESERVEDR0x0
17WAKEUP2_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16WAKEUP2_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8WAKEUP2_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4WAKEUP2_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0WAKEUP2_MUXMODERW0xF
0x0: Wakeup2
0x1: sys_nirq2
0xE: gpio1_2
0xF: Driver off
Table 18-814 CTRL_CORE_PAD_WAKEUP3
Address Offset0x0000 1824
Physical Address0x4A00 3824InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDWAKEUP3_WAKEUPEVENTWAKEUP3_WAKEUPENABLERESERVEDWAKEUP3_PULLTYPESELECTWAKEUP3_PULLUDENABLERESERVEDWAKEUP3_MODESELECTWAKEUP3_DELAYMODEWAKEUP3_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25WAKEUP3_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24WAKEUP3_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:18RESERVEDR0x0
17WAKEUP3_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16WAKEUP3_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8WAKEUP3_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4WAKEUP3_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0WAKEUP3_MUXMODERW0xF
0x0: Wakeup3
0x1: sys_nirq1
0xE: gpio1_3
0xF: Driver off
Table 18-815 CTRL_CORE_PAD_ON_OFF
Address Offset0x0000 1828
Physical Address0x4A00 3828InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDON_OFF_PULLTYPESELECTON_OFF_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17ON_OFF_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16ON_OFF_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-816 CTRL_CORE_PAD_RTC_PORZ
Address Offset0x0000 182C
Physical Address0x4A00 382CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRTC_PORZ_PULLTYPESELECTRTC_PORZ_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17RTC_PORZ_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RTC_PORZ_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-817 CTRL_CORE_PAD_TMS
Address Offset0x0000 1830
Physical Address0x4A00 3830InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTMS_SLEWCONTROLTMS_INPUTENABLETMS_PULLTYPESELECTTMS_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:20RESERVEDR0x0
19TMS_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18TMS_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17TMS_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16TMS_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-818 CTRL_CORE_PAD_TDI
Address Offset0x0000 1834
Physical Address0x4A00 3834InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTDI_WAKEUPEVENTTDI_WAKEUPENABLERESERVEDTDI_SLEWCONTROLTDI_INPUTENABLETDI_PULLTYPESELECTTDI_PULLUDENABLERESERVEDTDI_MODESELECTTDI_DELAYMODETDI_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25TDI_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24TDI_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19TDI_SLEWCONTROLRW0x1
0x0: Fast slew is selected
0x1: Slow slew is selected
18TDI_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17TDI_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16TDI_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8TDI_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4TDI_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0TDI_MUXMODERW0x0
0x0: tdi
0xE: gpio8_27
Table 18-819 CTRL_CORE_PAD_TDO
Address Offset0x0000 1838
Physical Address0x4A00 3838InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTDO_WAKEUPEVENTTDO_WAKEUPENABLERESERVEDTDO_SLEWCONTROLTDO_INPUTENABLETDO_PULLTYPESELECTTDO_PULLUDENABLERESERVEDTDO_MODESELECTTDO_DELAYMODETDO_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25TDO_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24TDO_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19TDO_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18TDO_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17TDO_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16TDO_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8TDO_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4TDO_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0TDO_MUXMODERW0x0
0x0: tdo
0xE: gpio8_28
Table 18-820 CTRL_CORE_PAD_TCLK
Address Offset0x0000 183C
Physical Address0x4A00 383CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTCLK_INPUTENABLETCLK_PULLTYPESELECTTCLK_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:19RESERVEDR0x0
18TCLK_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17TCLK_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16TCLK_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-821 CTRL_CORE_PAD_TRSTN
Address Offset0x0000 1840
Physical Address0x4A00 3840InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDTRSTN_SLEWCONTROLTRSTN_INPUTENABLETRSTN_PULLTYPESELECTTRSTN_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:20RESERVEDR0x0
19TRSTN_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18TRSTN_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17TRSTN_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16TRSTN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-822 CTRL_CORE_PAD_RTCK
Address Offset0x0000 1844
Physical Address0x4A00 3844InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRTCK_WAKEUPEVENTRTCK_WAKEUPENABLERESERVEDRTCK_SLEWCONTROLRTCK_INPUTENABLERTCK_PULLTYPESELECTRTCK_PULLUDENABLERESERVEDRTCK_MODESELECTRTCK_DELAYMODERTCK_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25RTCK_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24RTCK_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19RTCK_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18RTCK_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17RTCK_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RTCK_PULLUDENABLERW0x1
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8RTCK_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4RTCK_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0RTCK_MUXMODERW0x0
0x0: rtck
0xE: gpio8_29
Table 18-823 CTRL_CORE_PAD_EMU0
Address Offset0x0000 1848
Physical Address0x4A00 3848InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEMU0_WAKEUPEVENTEMU0_WAKEUPENABLERESERVEDEMU0_SLEWCONTROLEMU0_INPUTENABLEEMU0_PULLTYPESELECTEMU0_PULLUDENABLERESERVEDEMU0_MODESELECTEMU0_DELAYMODEEMU0_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25EMU0_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24EMU0_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19EMU0_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18EMU0_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17EMU0_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16EMU0_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8EMU0_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4EMU0_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0EMU0_MUXMODERW0x0
0x0: emu0
0xE: gpio8_30
Table 18-824 CTRL_CORE_PAD_EMU1
Address Offset0x0000 184C
Physical Address0x4A00 384CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEMU1_WAKEUPEVENTEMU1_WAKEUPENABLERESERVEDEMU1_SLEWCONTROLEMU1_INPUTENABLEEMU1_PULLTYPESELECTEMU1_PULLUDENABLERESERVEDEMU1_MODESELECTEMU1_DELAYMODEEMU1_MUXMODE
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25EMU1_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24EMU1_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:20RESERVEDR0x0
19EMU1_SLEWCONTROLRW0x0
0x0: Fast slew is selected
0x1: Slow slew is selected
18EMU1_INPUTENABLERW0x1
0x0: Receive mode is disabled
0x1: Receive mode is enabled
17EMU1_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16EMU1_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:9RESERVEDR0x0
8EMU1_MODESELECTSelects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in Section 18.4.6.1.5, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in Section 18.4.6.1.6, Manual IO Timing Modes.RW0x0
0x0: Default IO Timing Mode is used
0x1: A Virtual or Manual IO Timing Mode is used
7:4EMU1_DELAYMODEThis bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See Section 18.4.6.1.5, Virtual IO Timing Modes for details.RW0x0
3:0EMU1_MUXMODERW0x0
0x0: emu1
0xE: gpio8_31
Table 18-825 CTRL_CORE_PAD_RESETN
Address Offset0x0000 185C
Physical Address0x4A00 385CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRESETN_PULLTYPESELECTRESETN_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17RESETN_PULLTYPESELECTRW0x1
0x0: Pull Down is selected
0x1: Pull Up is selected
16RESETN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-826 CTRL_CORE_PAD_NMIN_DSP
Address Offset0x0000 1860
Physical Address0x4A00 3860InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDNMIN_WAKEUPEVENTNMIN_WAKEUPENABLERESERVEDNMIN_PULLTYPESELECTNMIN_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25NMIN_WAKEUPEVENTR0x0
0x0: No wakeup event detected
0x1: Wakeup event detected
24NMIN_WAKEUPENABLERW0x0
0x0: Wakeup is disabled
0x1: Wakeup is enabled
23:18RESERVEDR0x0
17NMIN_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16NMIN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-827 CTRL_CORE_PAD_RSTOUTN
Address Offset0x0000 1864
Physical Address0x4A00 3864InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRSTOUTN_PULLTYPESELECTRSTOUTN_PULLUDENABLERESERVED
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17RSTOUTN_PULLTYPESELECTRW0x0
0x0: Pull Down is selected
0x1: Pull Up is selected
16RSTOUTN_PULLUDENABLERW0x0
0x0: Enables weak Pull Up/Down
0x1: Disables weak Pull Up/Down
15:0RESERVEDR0x0
Table 18-828 CTRL_CORE_PADCONF_WAKEUPEVENT_0
Address Offset0x0000 1868
Physical Address0x4A00 3868InstanceCTRL_MODULE_CORE
Description
TypeR
313029282726252423222120191817161514131211109876543210
GPMC_A15_DUPLICATEWAKEUPEVENTGPMC_A14_DUPLICATEWAKEUPEVENTGPMC_A13_DUPLICATEWAKEUPEVENTGPMC_A12_DUPLICATEWAKEUPEVENTGPMC_A11_DUPLICATEWAKEUPEVENTGPMC_A10_DUPLICATEWAKEUPEVENTGPMC_A9_DUPLICATEWAKEUPEVENTGPMC_A8_DUPLICATEWAKEUPEVENTGPMC_A7_DUPLICATEWAKEUPEVENTGPMC_A6_DUPLICATEWAKEUPEVENTGPMC_A5_DUPLICATEWAKEUPEVENTGPMC_A4_DUPLICATEWAKEUPEVENTGPMC_A3_DUPLICATEWAKEUPEVENTGPMC_A2_DUPLICATEWAKEUPEVENTGPMC_A1_DUPLICATEWAKEUPEVENTGPMC_A0_DUPLICATEWAKEUPEVENTGPMC_AD15_DUPLICATEWAKEUPEVENTGPMC_AD14_DUPLICATEWAKEUPEVENTGPMC_AD13_DUPLICATEWAKEUPEVENTGPMC_AD12_DUPLICATEWAKEUPEVENTGPMC_AD11_DUPLICATEWAKEUPEVENTGPMC_AD10_DUPLICATEWAKEUPEVENTGPMC_AD9_DUPLICATEWAKEUPEVENTGPMC_AD8_DUPLICATEWAKEUPEVENTGPMC_AD7_DUPLICATEWAKEUPEVENTGPMC_AD6_DUPLICATEWAKEUPEVENTGPMC_AD5_DUPLICATEWAKEUPEVENTGPMC_AD4_DUPLICATEWAKEUPEVENTGPMC_AD3_DUPLICATEWAKEUPEVENTGPMC_AD2_DUPLICATEWAKEUPEVENTGPMC_AD1_DUPLICATEWAKEUPEVENTGPMC_AD0_DUPLICATEWAKEUPEVENT
BitsField NameDescriptionTypeReset
31GPMC_A15_DUPLICATEWAKEUPEVENTR0x0
30GPMC_A14_DUPLICATEWAKEUPEVENTR0x0
29GPMC_A13_DUPLICATEWAKEUPEVENTR0x0
28GPMC_A12_DUPLICATEWAKEUPEVENTR0x0
27GPMC_A11_DUPLICATEWAKEUPEVENTR0x0
26GPMC_A10_DUPLICATEWAKEUPEVENTR0x0
25GPMC_A9_DUPLICATEWAKEUPEVENTR0x0
24GPMC_A8_DUPLICATEWAKEUPEVENTR0x0
23GPMC_A7_DUPLICATEWAKEUPEVENTR0x0
22GPMC_A6_DUPLICATEWAKEUPEVENTR0x0
21GPMC_A5_DUPLICATEWAKEUPEVENTR0x0
20GPMC_A4_DUPLICATEWAKEUPEVENTR0x0
19GPMC_A3_DUPLICATEWAKEUPEVENTR0x0
18GPMC_A2_DUPLICATEWAKEUPEVENTR0x0
17GPMC_A1_DUPLICATEWAKEUPEVENTR0x0
16GPMC_A0_DUPLICATEWAKEUPEVENTR0x0
15GPMC_AD15_DUPLICATEWAKEUPEVENTR0x0
14GPMC_AD14_DUPLICATEWAKEUPEVENTR0x0
13GPMC_AD13_DUPLICATEWAKEUPEVENTR0x0
12GPMC_AD12_DUPLICATEWAKEUPEVENTR0x0
11GPMC_AD11_DUPLICATEWAKEUPEVENTR0x0
10GPMC_AD10_DUPLICATEWAKEUPEVENTR0x0
9GPMC_AD9_DUPLICATEWAKEUPEVENTR0x0
8GPMC_AD8_DUPLICATEWAKEUPEVENTR0x0
7GPMC_AD7_DUPLICATEWAKEUPEVENTR0x0
6GPMC_AD6_DUPLICATEWAKEUPEVENTR0x0
5GPMC_AD5_DUPLICATEWAKEUPEVENTR0x0
4GPMC_AD4_DUPLICATEWAKEUPEVENTR0x0
3GPMC_AD3_DUPLICATEWAKEUPEVENTR0x0
2GPMC_AD2_DUPLICATEWAKEUPEVENTR0x0
1GPMC_AD1_DUPLICATEWAKEUPEVENTR0x0
0GPMC_AD0_DUPLICATEWAKEUPEVENTR0x0
Table 18-829 CTRL_CORE_PADCONF_WAKEUPEVENT_1
Address Offset0x0000 186C
Physical Address0x4A00 386CInstanceCTRL_MODULE_CORE
Description
TypeR
313029282726252423222120191817161514131211109876543210
VIN1A_D2_DUPLICATEWAKEUPEVENTVIN1A_D1_DUPLICATEWAKEUPEVENTVIN1A_D0_DUPLICATEWAKEUPEVENTVIN1A_VSYNC0_DUPLICATEWAKEUPEVENTVIN1A_HSYNC0_DUPLICATEWAKEUPEVENTVIN1A_FLD0_DUPLICATEWAKEUPEVENTVIN1A_DE0_DUPLICATEWAKEUPEVENTVIN1B_CLK1_DUPLICATEWAKEUPEVENTVIN1A_CLK0_DUPLICATEWAKEUPEVENTGPMC_WAIT0_DUPLICATEWAKEUPEVENTGPMC_BEN1_DUPLICATEWAKEUPEVENTGPMC_BEN0_DUPLICATEWAKEUPEVENTGPMC_WEN_DUPLICATEWAKEUPEVENTGPMC_OEN_REN_DUPLICATEWAKEUPEVENTGPMC_ADVN_ALE_DUPLICATEWAKEUPEVENTGPMC_CLK_DUPLICATEWAKEUPEVENTGPMC_CS3_DUPLICATEWAKEUPEVENTGPMC_CS2_DUPLICATEWAKEUPEVENTGPMC_CS0_DUPLICATEWAKEUPEVENTGPMC_CS1_DUPLICATEWAKEUPEVENTGPMC_A27_DUPLICATEWAKEUPEVENTGPMC_A26_DUPLICATEWAKEUPEVENTGPMC_A25_DUPLICATEWAKEUPEVENTGPMC_A24_DUPLICATEWAKEUPEVENTGPMC_A23_DUPLICATEWAKEUPEVENTGPMC_A22_DUPLICATEWAKEUPEVENTGPMC_A21_DUPLICATEWAKEUPEVENTGPMC_A20_DUPLICATEWAKEUPEVENTGPMC_A19_DUPLICATEWAKEUPEVENTGPMC_A18_DUPLICATEWAKEUPEVENTGPMC_A17_DUPLICATEWAKEUPEVENTGPMC_A16_DUPLICATEWAKEUPEVENT
BitsField NameDescriptionTypeReset
31VIN1A_D2_DUPLICATEWAKEUPEVENTR0x0
30VIN1A_D1_DUPLICATEWAKEUPEVENTR0x0
29VIN1A_D0_DUPLICATEWAKEUPEVENTR0x0
28VIN1A_VSYNC0_DUPLICATEWAKEUPEVENTR0x0
27VIN1A_HSYNC0_DUPLICATEWAKEUPEVENTR0x0
26VIN1A_FLD0_DUPLICATEWAKEUPEVENTR0x0
25VIN1A_DE0_DUPLICATEWAKEUPEVENTR0x0
24VIN1B_CLK1_DUPLICATEWAKEUPEVENTR0x0
23VIN1A_CLK0_DUPLICATEWAKEUPEVENTR0x0
22GPMC_WAIT0_DUPLICATEWAKEUPEVENTR0x0
21GPMC_BEN1_DUPLICATEWAKEUPEVENTR0x0
20GPMC_BEN0_DUPLICATEWAKEUPEVENTR0x0
19GPMC_WEN_DUPLICATEWAKEUPEVENTR0x0
18GPMC_OEN_REN_DUPLICATEWAKEUPEVENTR0x0
17GPMC_ADVN_ALE_DUPLICATEWAKEUPEVENTR0x0
16GPMC_CLK_DUPLICATEWAKEUPEVENTR0x0
15GPMC_CS3_DUPLICATEWAKEUPEVENTR0x0
14GPMC_CS2_DUPLICATEWAKEUPEVENTR0x0
13GPMC_CS0_DUPLICATEWAKEUPEVENTR0x0
12GPMC_CS1_DUPLICATEWAKEUPEVENTR0x0
11GPMC_A27_DUPLICATEWAKEUPEVENTR0x0
10GPMC_A26_DUPLICATEWAKEUPEVENTR0x0
9GPMC_A25_DUPLICATEWAKEUPEVENTR0x0
8GPMC_A24_DUPLICATEWAKEUPEVENTR0x0
7GPMC_A23_DUPLICATEWAKEUPEVENTR0x0
6GPMC_A22_DUPLICATEWAKEUPEVENTR0x0
5GPMC_A21_DUPLICATEWAKEUPEVENTR0x0
4GPMC_A20_DUPLICATEWAKEUPEVENTR0x0
3GPMC_A19_DUPLICATEWAKEUPEVENTR0x0
2GPMC_A18_DUPLICATEWAKEUPEVENTR0x0
1GPMC_A17_DUPLICATEWAKEUPEVENTR0x0
0GPMC_A16_DUPLICATEWAKEUPEVENTR0x0
Table 18-830 CTRL_CORE_PADCONF_WAKEUPEVENT_2
Address Offset0x0000 1870
Physical Address0x4A00 3870InstanceCTRL_MODULE_CORE
Description
TypeR
313029282726252423222120191817161514131211109876543210
VIN2A_D5_DUPLICATEWAKEUPEVENTVIN2A_D4_DUPLICATEWAKEUPEVENTVIN2A_D3_DUPLICATEWAKEUPEVENTVIN2A_D2_DUPLICATEWAKEUPEVENTVIN2A_D1_DUPLICATEWAKEUPEVENTVIN2A_D0_DUPLICATEWAKEUPEVENTVIN2A_VSYNC0_DUPLICATEWAKEUPEVENTVIN2A_HSYNC0_DUPLICATEWAKEUPEVENTVIN2A_FLD0_DUPLICATEWAKEUPEVENTVIN2A_DE0_DUPLICATEWAKEUPEVENTVIN2A_CLK0_DUPLICATEWAKEUPEVENTVIN1A_D23_DUPLICATEWAKEUPEVENTVIN1A_D22_DUPLICATEWAKEUPEVENTVIN1A_D21_DUPLICATEWAKEUPEVENTVIN1A_D20_DUPLICATEWAKEUPEVENTVIN1A_D19_DUPLICATEWAKEUPEVENTVIN1A_D18_DUPLICATEWAKEUPEVENTVIN1A_D17_DUPLICATEWAKEUPEVENTVIN1A_D16_DUPLICATEWAKEUPEVENTVIN1A_D15_DUPLICATEWAKEUPEVENTVIN1A_D14_DUPLICATEWAKEUPEVENTVIN1A_D13_DUPLICATEWAKEUPEVENTVIN1A_D12_DUPLICATEWAKEUPEVENTVIN1A_D11_DUPLICATEWAKEUPEVENTVIN1A_D10_DUPLICATEWAKEUPEVENTVIN1A_D9_DUPLICATEWAKEUPEVENTVIN1A_D8_DUPLICATEWAKEUPEVENTVIN1A_D7_DUPLICATEWAKEUPEVENTVIN1A_D6_DUPLICATEWAKEUPEVENTVIN1A_D5_DUPLICATEWAKEUPEVENTVIN1A_D4_DUPLICATEWAKEUPEVENTVIN1A_D3_DUPLICATEWAKEUPEVENT
BitsField NameDescriptionTypeReset
31VIN2A_D5_DUPLICATEWAKEUPEVENTR0x0
30VIN2A_D4_DUPLICATEWAKEUPEVENTR0x0
29VIN2A_D3_DUPLICATEWAKEUPEVENTR0x0
28VIN2A_D2_DUPLICATEWAKEUPEVENTR0x0
27VIN2A_D1_DUPLICATEWAKEUPEVENTR0x0
26VIN2A_D0_DUPLICATEWAKEUPEVENTR0x0
25VIN2A_VSYNC0_DUPLICATEWAKEUPEVENTR0x0
24VIN2A_HSYNC0_DUPLICATEWAKEUPEVENTR0x0
23VIN2A_FLD0_DUPLICATEWAKEUPEVENTR0x0
22VIN2A_DE0_DUPLICATEWAKEUPEVENTR0x0
21VIN2A_CLK0_DUPLICATEWAKEUPEVENTR0x0
20VIN1A_D23_DUPLICATEWAKEUPEVENTR0x0
19VIN1A_D22_DUPLICATEWAKEUPEVENTR0x0
18VIN1A_D21_DUPLICATEWAKEUPEVENTR0x0
17VIN1A_D20_DUPLICATEWAKEUPEVENTR0x0
16VIN1A_D19_DUPLICATEWAKEUPEVENTR0x0
15VIN1A_D18_DUPLICATEWAKEUPEVENTR0x0
14VIN1A_D17_DUPLICATEWAKEUPEVENTR0x0
13VIN1A_D16_DUPLICATEWAKEUPEVENTR0x0
12VIN1A_D15_DUPLICATEWAKEUPEVENTR0x0
11VIN1A_D14_DUPLICATEWAKEUPEVENTR0x0
10VIN1A_D13_DUPLICATEWAKEUPEVENTR0x0
9VIN1A_D12_DUPLICATEWAKEUPEVENTR0x0
8VIN1A_D11_DUPLICATEWAKEUPEVENTR0x0
7VIN1A_D10_DUPLICATEWAKEUPEVENTR0x0
6VIN1A_D9_DUPLICATEWAKEUPEVENTR0x0
5VIN1A_D8_DUPLICATEWAKEUPEVENTR0x0
4VIN1A_D7_DUPLICATEWAKEUPEVENTR0x0
3VIN1A_D6_DUPLICATEWAKEUPEVENTR0x0
2VIN1A_D5_DUPLICATEWAKEUPEVENTR0x0
1VIN1A_D4_DUPLICATEWAKEUPEVENTR0x0
0VIN1A_D3_DUPLICATEWAKEUPEVENTR0x0
Table 18-831 CTRL_CORE_PADCONF_WAKEUPEVENT_3
Address Offset0x0000 1874
Physical Address0x4A00 3874InstanceCTRL_MODULE_CORE
Description
TypeR
313029282726252423222120191817161514131211109876543210
VOUT1_D8_DUPLICATEWAKEUPEVENTVOUT1_D7_DUPLICATEWAKEUPEVENTVOUT1_D6_DUPLICATEWAKEUPEVENTVOUT1_D5_DUPLICATEWAKEUPEVENTVOUT1_D4_DUPLICATEWAKEUPEVENTVOUT1_D3_DUPLICATEWAKEUPEVENTVOUT1_D2_DUPLICATEWAKEUPEVENTVOUT1_D1_DUPLICATEWAKEUPEVENTVOUT1_D0_DUPLICATEWAKEUPEVENTVOUT1_VSYNC_DUPLICATEWAKEUPEVENTVOUT1_HSYNC_DUPLICATEWAKEUPEVENTVOUT1_FLD_DUPLICATEWAKEUPEVENTVOUT1_DE_DUPLICATEWAKEUPEVENTVOUT1_CLK_DUPLICATEWAKEUPEVENTVIN2A_D23_DUPLICATEWAKEUPEVENTVIN2A_D22_DUPLICATEWAKEUPEVENTVIN2A_D21_DUPLICATEWAKEUPEVENTVIN2A_D20_DUPLICATEWAKEUPEVENTVIN2A_D19_DUPLICATEWAKEUPEVENTVIN2A_D18_DUPLICATEWAKEUPEVENTVIN2A_D17_DUPLICATEWAKEUPEVENTVIN2A_D16_DUPLICATEWAKEUPEVENTVIN2A_D15_DUPLICATEWAKEUPEVENTVIN2A_D14_DUPLICATEWAKEUPEVENTVIN2A_D13_DUPLICATEWAKEUPEVENTVIN2A_D12_DUPLICATEWAKEUPEVENTVIN2A_D11_DUPLICATEWAKEUPEVENTVIN2A_D10_DUPLICATEWAKEUPEVENTVIN2A_D9_DUPLICATEWAKEUPEVENTVIN2A_D8_DUPLICATEWAKEUPEVENTVIN2A_D7_DUPLICATEWAKEUPEVENTVIN2A_D6_DUPLICATEWAKEUPEVENT
BitsField NameDescriptionTypeReset
31VOUT1_D8_DUPLICATEWAKEUPEVENTR0x0
30VOUT1_D7_DUPLICATEWAKEUPEVENTR0x0
29VOUT1_D6_DUPLICATEWAKEUPEVENTR0x0
28VOUT1_D5_DUPLICATEWAKEUPEVENTR0x0
27VOUT1_D4_DUPLICATEWAKEUPEVENTR0x0
26VOUT1_D3_DUPLICATEWAKEUPEVENTR0x0
25VOUT1_D2_DUPLICATEWAKEUPEVENTR0x0
24VOUT1_D1_DUPLICATEWAKEUPEVENTR0x0
23VOUT1_D0_DUPLICATEWAKEUPEVENTR0x0
22VOUT1_VSYNC_DUPLICATEWAKEUPEVENTR0x0
21VOUT1_HSYNC_DUPLICATEWAKEUPEVENTR0x0
20VOUT1_FLD_DUPLICATEWAKEUPEVENTR0x0
19VOUT1_DE_DUPLICATEWAKEUPEVENTR0x0
18VOUT1_CLK_DUPLICATEWAKEUPEVENTR0x0
17VIN2A_D23_DUPLICATEWAKEUPEVENTR0x0
16VIN2A_D22_DUPLICATEWAKEUPEVENTR0x0
15VIN2A_D21_DUPLICATEWAKEUPEVENTR0x0
14VIN2A_D20_DUPLICATEWAKEUPEVENTR0x0
13VIN2A_D19_DUPLICATEWAKEUPEVENTR0x0
12VIN2A_D18_DUPLICATEWAKEUPEVENTR0x0
11VIN2A_D17_DUPLICATEWAKEUPEVENTR0x0
10VIN2A_D16_DUPLICATEWAKEUPEVENTR0x0
9VIN2A_D15_DUPLICATEWAKEUPEVENTR0x0
8VIN2A_D14_DUPLICATEWAKEUPEVENTR0x0
7VIN2A_D13_DUPLICATEWAKEUPEVENTR0x0
6VIN2A_D12_DUPLICATEWAKEUPEVENTR0x0
5VIN2A_D11_DUPLICATEWAKEUPEVENTR0x0
4VIN2A_D10_DUPLICATEWAKEUPEVENTR0x0
3VIN2A_D9_DUPLICATEWAKEUPEVENTR0x0
2VIN2A_D8_DUPLICATEWAKEUPEVENTR0x0
1VIN2A_D7_DUPLICATEWAKEUPEVENTR0x0
0VIN2A_D6_DUPLICATEWAKEUPEVENTR0x0
Table 18-832 CTRL_CORE_PADCONF_WAKEUPEVENT_4
Address Offset0x0000 1878
Physical Address0x4A00 3878InstanceCTRL_MODULE_CORE
Description
TypeR
313029282726252423222120191817161514131211109876543210
RGMII0_RXD0_DUPLICATEWAKEUPEVENTRGMII0_RXD1_DUPLICATEWAKEUPEVENTRGMII0_RXD2_DUPLICATEWAKEUPEVENTRGMII0_RXD3_DUPLICATEWAKEUPEVENTRGMII0_RXCTL_DUPLICATEWAKEUPEVENTRGMII0_RXC_DUPLICATEWAKEUPEVENTRGMII0_TXD0_DUPLICATEWAKEUPEVENTRGMII0_TXD1_DUPLICATEWAKEUPEVENTRGMII0_TXD2_DUPLICATEWAKEUPEVENTRGMII0_TXD3_DUPLICATEWAKEUPEVENTRGMII0_TXCTL_DUPLICATEWAKEUPEVENTRGMII0_TXC_DUPLICATEWAKEUPEVENTUART3_TXD_DUPLICATEWAKEUPEVENTUART3_RXD_DUPLICATEWAKEUPEVENTRMII_MHZ_50_CLK_DUPLICATEWAKEUPEVENTMDIO_D_DUPLICATEWAKEUPEVENTMDIO_MCLK_DUPLICATEWAKEUPEVENTVOUT1_D23_DUPLICATEWAKEUPEVENTVOUT1_D22_DUPLICATEWAKEUPEVENTVOUT1_D21_DUPLICATEWAKEUPEVENTVOUT1_D20_DUPLICATEWAKEUPEVENTVOUT1_D19_DUPLICATEWAKEUPEVENTVOUT1_D18_DUPLICATEWAKEUPEVENTVOUT1_D17_DUPLICATEWAKEUPEVENTVOUT1_D16_DUPLICATEWAKEUPEVENTVOUT1_D15_DUPLICATEWAKEUPEVENTVOUT1_D14_DUPLICATEWAKEUPEVENTVOUT1_D13_DUPLICATEWAKEUPEVENTVOUT1_D12_DUPLICATEWAKEUPEVENTVOUT1_D11_DUPLICATEWAKEUPEVENTVOUT1_D10_DUPLICATEWAKEUPEVENTVOUT1_D9_DUPLICATEWAKEUPEVENT
BitsField NameDescriptionTypeReset
31RGMII0_RXD0_DUPLICATEWAKEUPEVENTR0x0
30RGMII0_RXD1_DUPLICATEWAKEUPEVENTR0x0
29RGMII0_RXD2_DUPLICATEWAKEUPEVENTR0x0
28RGMII0_RXD3_DUPLICATEWAKEUPEVENTR0x0
27RGMII0_RXCTL_DUPLICATEWAKEUPEVENTR0x0
26RGMII0_RXC_DUPLICATEWAKEUPEVENTR0x0
25RGMII0_TXD0_DUPLICATEWAKEUPEVENTR0x0
24RGMII0_TXD1_DUPLICATEWAKEUPEVENTR0x0
23RGMII0_TXD2_DUPLICATEWAKEUPEVENTR0x0
22RGMII0_TXD3_DUPLICATEWAKEUPEVENTR0x0
21RGMII0_TXCTL_DUPLICATEWAKEUPEVENTR0x0
20RGMII0_TXC_DUPLICATEWAKEUPEVENTR0x0
19UART3_TXD_DUPLICATEWAKEUPEVENTR0x0
18UART3_RXD_DUPLICATEWAKEUPEVENTR0x0
17RMII_MHZ_50_CLK_DUPLICATEWAKEUPEVENTR0x0
16MDIO_D_DUPLICATEWAKEUPEVENTR0x0
15MDIO_MCLK_DUPLICATEWAKEUPEVENTR0x0
14VOUT1_D23_DUPLICATEWAKEUPEVENTR0x0
13VOUT1_D22_DUPLICATEWAKEUPEVENTR0x0
12VOUT1_D21_DUPLICATEWAKEUPEVENTR0x0
11VOUT1_D20_DUPLICATEWAKEUPEVENTR0x0
10VOUT1_D19_DUPLICATEWAKEUPEVENTR0x0
9VOUT1_D18_DUPLICATEWAKEUPEVENTR0x0
8VOUT1_D17_DUPLICATEWAKEUPEVENTR0x0
7VOUT1_D16_DUPLICATEWAKEUPEVENTR0x0
6VOUT1_D15_DUPLICATEWAKEUPEVENTR0x0
5VOUT1_D14_DUPLICATEWAKEUPEVENTR0x0
4VOUT1_D13_DUPLICATEWAKEUPEVENTR0x0
3VOUT1_D12_DUPLICATEWAKEUPEVENTR0x0
2VOUT1_D11_DUPLICATEWAKEUPEVENTR0x0
1VOUT1_D10_DUPLICATEWAKEUPEVENTR0x0
0VOUT1_D9_DUPLICATEWAKEUPEVENTR0x0
Table 18-833 CTRL_CORE_PADCONF_WAKEUPEVENT_5
Address Offset0x0000 187C
Physical Address0x4A00 387CInstanceCTRL_MODULE_CORE
Description
TypeR
313029282726252423222120191817161514131211109876543210
MCASP2_ACLKR_DUPLICATEWAKEUPEVENTMCASP2_FSX_DUPLICATEWAKEUPEVENTMCASP2_ACLKX_DUPLICATEWAKEUPEVENTMCASP1_AXR15_DUPLICATEWAKEUPEVENTMCASP1_AXR14_DUPLICATEWAKEUPEVENTMCASP1_AXR13_DUPLICATEWAKEUPEVENTMCASP1_AXR12_DUPLICATEWAKEUPEVENTMCASP1_AXR11_DUPLICATEWAKEUPEVENTMCASP1_AXR10_DUPLICATEWAKEUPEVENTMCASP1_AXR9_DUPLICATEWAKEUPEVENTMCASP1_AXR8_DUPLICATEWAKEUPEVENTMCASP1_AXR7_DUPLICATEWAKEUPEVENTMCASP1_AXR6_DUPLICATEWAKEUPEVENTMCASP1_AXR5_DUPLICATEWAKEUPEVENTMCASP1_AXR4_DUPLICATEWAKEUPEVENTMCASP1_AXR3_DUPLICATEWAKEUPEVENTMCASP1_AXR2_DUPLICATEWAKEUPEVENTMCASP1_AXR1_DUPLICATEWAKEUPEVENTMCASP1_AXR0_DUPLICATEWAKEUPEVENTMCASP1_FSR_DUPLICATEWAKEUPEVENTMCASP1_ACLKR_DUPLICATEWAKEUPEVENTMCASP1_FSX_DUPLICATEWAKEUPEVENTMCASP1_ACLKX_DUPLICATEWAKEUPEVENTXREF_CLK3_DUPLICATEWAKEUPEVENTXREF_CLK2_DUPLICATEWAKEUPEVENTXREF_CLK1_DUPLICATEWAKEUPEVENTXREF_CLK0_DUPLICATEWAKEUPEVENTGPIO6_16_DUPLICATEWAKEUPEVENTGPIO6_15_DUPLICATEWAKEUPEVENTGPIO6_14_DUPLICATEWAKEUPEVENTUSB2_DRVVBUS_DUPLICATEWAKEUPEVENTUSB1_DRVVBUS_DUPLICATEWAKEUPEVENT
BitsField NameDescriptionTypeReset
31MCASP2_ACLKR_DUPLICATEWAKEUPEVENTR0x0
30MCASP2_FSX_DUPLICATEWAKEUPEVENTR0x0
29MCASP2_ACLKX_DUPLICATEWAKEUPEVENTR0x0
28MCASP1_AXR15_DUPLICATEWAKEUPEVENTR0x0
27MCASP1_AXR14_DUPLICATEWAKEUPEVENTR0x0
26MCASP1_AXR13_DUPLICATEWAKEUPEVENTR0x0
25MCASP1_AXR12_DUPLICATEWAKEUPEVENTR0x0
24MCASP1_AXR11_DUPLICATEWAKEUPEVENTR0x0
23MCASP1_AXR10_DUPLICATEWAKEUPEVENTR0x0
22MCASP1_AXR9_DUPLICATEWAKEUPEVENTR0x0
21MCASP1_AXR8_DUPLICATEWAKEUPEVENTR0x0
20MCASP1_AXR7_DUPLICATEWAKEUPEVENTR0x0
19MCASP1_AXR6_DUPLICATEWAKEUPEVENTR0x0
18MCASP1_AXR5_DUPLICATEWAKEUPEVENTR0x0
17MCASP1_AXR4_DUPLICATEWAKEUPEVENTR0x0
16MCASP1_AXR3_DUPLICATEWAKEUPEVENTR0x0
15MCASP1_AXR2_DUPLICATEWAKEUPEVENTR0x0
14MCASP1_AXR1_DUPLICATEWAKEUPEVENTR0x0
13MCASP1_AXR0_DUPLICATEWAKEUPEVENTR0x0
12MCASP1_FSR_DUPLICATEWAKEUPEVENTR0x0
11MCASP1_ACLKR_DUPLICATEWAKEUPEVENTR0x0
10MCASP1_FSX_DUPLICATEWAKEUPEVENTR0x0
9MCASP1_ACLKX_DUPLICATEWAKEUPEVENTR0x0
8XREF_CLK3_DUPLICATEWAKEUPEVENTR0x0
7XREF_CLK2_DUPLICATEWAKEUPEVENTR0x0
6XREF_CLK1_DUPLICATEWAKEUPEVENTR0x0
5XREF_CLK0_DUPLICATEWAKEUPEVENTR0x0
4GPIO6_16_DUPLICATEWAKEUPEVENTR0x0
3GPIO6_15_DUPLICATEWAKEUPEVENTR0x0
2GPIO6_14_DUPLICATEWAKEUPEVENTR0x0
1USB2_DRVVBUS_DUPLICATEWAKEUPEVENTR0x0
0USB1_DRVVBUS_DUPLICATEWAKEUPEVENTR0x0
Table 18-834 CTRL_CORE_PADCONF_WAKEUPEVENT_6
Address Offset0x0000 1880
Physical Address0x4A00 3880InstanceCTRL_MODULE_CORE
Description
TypeR
313029282726252423222120191817161514131211109876543210
MMC3_CLK_DUPLICATEWAKEUPEVENTGPIO6_11_DUPLICATEWAKEUPEVENTGPIO6_10_DUPLICATEWAKEUPEVENTMMC1_SDWP_DUPLICATEWAKEUPEVENTMMC1_SDCD_DUPLICATEWAKEUPEVENTMMC1_DAT3_DUPLICATEWAKEUPEVENTMMC1_DAT2_DUPLICATEWAKEUPEVENTMMC1_DAT1_DUPLICATEWAKEUPEVENTMMC1_DAT0_DUPLICATEWAKEUPEVENTMMC1_CMD_DUPLICATEWAKEUPEVENTMMC1_CLK_DUPLICATEWAKEUPEVENTMCASP5_AXR1_DUPLICATEWAKEUPEVENTMCASP5_AXR0_DUPLICATEWAKEUPEVENTMCASP5_FSX_DUPLICATEWAKEUPEVENTMCASP5_ACLKX_DUPLICATEWAKEUPEVENTMCASP4_AXR1_DUPLICATEWAKEUPEVENTMCASP4_AXR0_DUPLICATEWAKEUPEVENTMCASP4_FSX_DUPLICATEWAKEUPEVENTMCASP4_ACLKX_DUPLICATEWAKEUPEVENTMCASP3_AXR1_DUPLICATEWAKEUPEVENTMCASP3_AXR0_DUPLICATEWAKEUPEVENTMCASP3_FSX_DUPLICATEWAKEUPEVENTMCASP3_ACLKX_DUPLICATEWAKEUPEVENTMCASP2_AXR7_DUPLICATEWAKEUPEVENTMCASP2_AXR6_DUPLICATEWAKEUPEVENTMCASP2_AXR5_DUPLICATEWAKEUPEVENTMCASP2_AXR4_DUPLICATEWAKEUPEVENTMCASP2_AXR3_DUPLICATEWAKEUPEVENTMCASP2_AXR2_DUPLICATEWAKEUPEVENTMCASP2_AXR1_DUPLICATEWAKEUPEVENTMCASP2_AXR0_DUPLICATEWAKEUPEVENTMCASP2_FSR_DUPLICATEWAKEUPEVENT
BitsField NameDescriptionTypeReset
31MMC3_CLK_DUPLICATEWAKEUPEVENTR0x0
30GPIO6_11_DUPLICATEWAKEUPEVENTR0x0
29GPIO6_10_DUPLICATEWAKEUPEVENTR0x0
28MMC1_SDWP_DUPLICATEWAKEUPEVENTR0x0
27MMC1_SDCD_DUPLICATEWAKEUPEVENTR0x0
26MMC1_DAT3_DUPLICATEWAKEUPEVENTR0x0
25MMC1_DAT2_DUPLICATEWAKEUPEVENTR0x0
24MMC1_DAT1_DUPLICATEWAKEUPEVENTR0x0
23MMC1_DAT0_DUPLICATEWAKEUPEVENTR0x0
22MMC1_CMD_DUPLICATEWAKEUPEVENTR0x0
21MMC1_CLK_DUPLICATEWAKEUPEVENTR0x0
20MCASP5_AXR1_DUPLICATEWAKEUPEVENTR0x0
19MCASP5_AXR0_DUPLICATEWAKEUPEVENTR0x0
18MCASP5_FSX_DUPLICATEWAKEUPEVENTR0x0
17MCASP5_ACLKX_DUPLICATEWAKEUPEVENTR0x0
16MCASP4_AXR1_DUPLICATEWAKEUPEVENTR0x0
15MCASP4_AXR0_DUPLICATEWAKEUPEVENTR0x0
14MCASP4_FSX_DUPLICATEWAKEUPEVENTR0x0
13MCASP4_ACLKX_DUPLICATEWAKEUPEVENTR0x0
12MCASP3_AXR1_DUPLICATEWAKEUPEVENTR0x0
11MCASP3_AXR0_DUPLICATEWAKEUPEVENTR0x0
10MCASP3_FSX_DUPLICATEWAKEUPEVENTR0x0
9MCASP3_ACLKX_DUPLICATEWAKEUPEVENTR0x0
8MCASP2_AXR7_DUPLICATEWAKEUPEVENTR0x0
7MCASP2_AXR6_DUPLICATEWAKEUPEVENTR0x0
6MCASP2_AXR5_DUPLICATEWAKEUPEVENTR0x0
5MCASP2_AXR4_DUPLICATEWAKEUPEVENTR0x0
4MCASP2_AXR3_DUPLICATEWAKEUPEVENTR0x0
3MCASP2_AXR2_DUPLICATEWAKEUPEVENTR0x0
2MCASP2_AXR1_DUPLICATEWAKEUPEVENTR0x0
1MCASP2_AXR0_DUPLICATEWAKEUPEVENTR0x0
0MCASP2_FSR_DUPLICATEWAKEUPEVENTR0x0
Table 18-835 CTRL_CORE_PADCONF_WAKEUPEVENT_7
Address Offset0x0000 1884
Physical Address0x4A00 3884InstanceCTRL_MODULE_CORE
Description
TypeR
313029282726252423222120191817161514131211109876543210
UART2_RTSN_DUPLICATEWAKEUPEVENTUART2_CTSN_DUPLICATEWAKEUPEVENTUART2_TXD_DUPLICATEWAKEUPEVENTUART2_RXD_DUPLICATEWAKEUPEVENTUART1_RTSN_DUPLICATEWAKEUPEVENTUART1_CTSN_DUPLICATEWAKEUPEVENTUART1_TXD_DUPLICATEWAKEUPEVENTUART1_RXD_DUPLICATEWAKEUPEVENTDCAN2_RX_DUPLICATEWAKEUPEVENTDCAN2_TX_DUPLICATEWAKEUPEVENTDCAN1_RX_DUPLICATEWAKEUPEVENTDCAN1_TX_DUPLICATEWAKEUPEVENTSPI2_CS0_DUPLICATEWAKEUPEVENTSPI2_D0_DUPLICATEWAKEUPEVENTSPI2_D1_DUPLICATEWAKEUPEVENTSPI2_SCLK_DUPLICATEWAKEUPEVENTSPI1_CS3_DUPLICATEWAKEUPEVENTSPI1_CS2_DUPLICATEWAKEUPEVENTSPI1_CS1_DUPLICATEWAKEUPEVENTSPI1_CS0_DUPLICATEWAKEUPEVENTSPI1_D0_DUPLICATEWAKEUPEVENTSPI1_D1_DUPLICATEWAKEUPEVENTSPI1_SCLK_DUPLICATEWAKEUPEVENTMMC3_DAT7_DUPLICATEWAKEUPEVENTMMC3_DAT6_DUPLICATEWAKEUPEVENTMMC3_DAT5_DUPLICATEWAKEUPEVENTMMC3_DAT4_DUPLICATEWAKEUPEVENTMMC3_DAT3_DUPLICATEWAKEUPEVENTMMC3_DAT2_DUPLICATEWAKEUPEVENTMMC3_DAT1_DUPLICATEWAKEUPEVENTMMC3_DAT0_DUPLICATEWAKEUPEVENTMMC3_CMD_DUPLICATEWAKEUPEVENT
BitsField NameDescriptionTypeReset
31UART2_RTSN_DUPLICATEWAKEUPEVENTR0x0
30UART2_CTSN_DUPLICATEWAKEUPEVENTR0x0
29UART2_TXD_DUPLICATEWAKEUPEVENTR0x0
28UART2_RXD_DUPLICATEWAKEUPEVENTR0x0
27UART1_RTSN_DUPLICATEWAKEUPEVENTR0x0
26UART1_CTSN_DUPLICATEWAKEUPEVENTR0x0
25UART1_TXD_DUPLICATEWAKEUPEVENTR0x0
24UART1_RXD_DUPLICATEWAKEUPEVENTR0x0
23DCAN2_RX_DUPLICATEWAKEUPEVENTR0x0
22DCAN2_TX_DUPLICATEWAKEUPEVENTR0x0
21DCAN1_RX_DUPLICATEWAKEUPEVENTR0x0
20DCAN1_TX_DUPLICATEWAKEUPEVENTR0x0
19SPI2_CS0_DUPLICATEWAKEUPEVENTR0x0
18SPI2_D0_DUPLICATEWAKEUPEVENTR0x0
17SPI2_D1_DUPLICATEWAKEUPEVENTR0x0
16SPI2_SCLK_DUPLICATEWAKEUPEVENTR0x0
15SPI1_CS3_DUPLICATEWAKEUPEVENTR0x0
14SPI1_CS2_DUPLICATEWAKEUPEVENTR0x0
13SPI1_CS1_DUPLICATEWAKEUPEVENTR0x0
12SPI1_CS0_DUPLICATEWAKEUPEVENTR0x0
11SPI1_D0_DUPLICATEWAKEUPEVENTR0x0
10SPI1_D1_DUPLICATEWAKEUPEVENTR0x0
9SPI1_SCLK_DUPLICATEWAKEUPEVENTR0x0
8MMC3_DAT7_DUPLICATEWAKEUPEVENTR0x0
7MMC3_DAT6_DUPLICATEWAKEUPEVENTR0x0
6MMC3_DAT5_DUPLICATEWAKEUPEVENTR0x0
5MMC3_DAT4_DUPLICATEWAKEUPEVENTR0x0
4MMC3_DAT3_DUPLICATEWAKEUPEVENTR0x0
3MMC3_DAT2_DUPLICATEWAKEUPEVENTR0x0
2MMC3_DAT1_DUPLICATEWAKEUPEVENTR0x0
1MMC3_DAT0_DUPLICATEWAKEUPEVENTR0x0
0MMC3_CMD_DUPLICATEWAKEUPEVENTR0x0
Table 18-836 CTRL_CORE_PADCONF_WAKEUPEVENT_8
Address Offset0x0000 1888
Physical Address0x4A00 3888InstanceCTRL_MODULE_CORE
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDNMIN_DUPLICATEWAKEUPEVENTEMU4_DUPLICATEWAKEUPEVENTEMU3_DUPLICATEWAKEUPEVENTEMU2_DUPLICATEWAKEUPEVENTEMU1_DUPLICATEWAKEUPEVENTEMU0_DUPLICATEWAKEUPEVENTRTCK_DUPLICATEWAKEUPEVENTTDO_DUPLICATEWAKEUPEVENTTDI_DUPLICATEWAKEUPEVENTWAKEUP3_DUPLICATEWAKEUPEVENTWAKEUP2_DUPLICATEWAKEUPEVENTWAKEUP1_DUPLICATEWAKEUPEVENTWAKEUP0_DUPLICATEWAKEUPEVENTI2C3_SCL_DUPLICATEWAKEUPEVENTI2C3_SDA_DUPLICATEWAKEUPEVENTI2C2_SCL_DUPLICATEWAKEUPEVENTI2C2_SDA_DUPLICATEWAKEUPEVENTI2C1_SCL_DUPLICATEWAKEUPEVENTI2C1_SDA_DUPLICATEWAKEUPEVENT
BitsField NameDescriptionTypeReset
31:19RESERVEDR0x0
18NMIN_DUPLICATEWAKEUPEVENTR0x0
17EMU4_DUPLICATEWAKEUPEVENTR0x0
16EMU3_DUPLICATEWAKEUPEVENTR0x0
15EMU2_DUPLICATEWAKEUPEVENTR0x0
14EMU1_DUPLICATEWAKEUPEVENTR0x0
13EMU0_DUPLICATEWAKEUPEVENTR0x0
12RTCK_DUPLICATEWAKEUPEVENTR0x0
11TDO_DUPLICATEWAKEUPEVENTR0x0
10TDI_DUPLICATEWAKEUPEVENTR0x0
9WAKEUP3_DUPLICATEWAKEUPEVENTR0x0
8WAKEUP2_DUPLICATEWAKEUPEVENTR0x0
7WAKEUP1_DUPLICATEWAKEUPEVENTR0x0
6WAKEUP0_DUPLICATEWAKEUPEVENTR0x0
5I2C3_SCL_DUPLICATEWAKEUPEVENTR0x0
4I2C3_SDA_DUPLICATEWAKEUPEVENTR0x0
3I2C2_SCL_DUPLICATEWAKEUPEVENTR0x0
2I2C2_SDA_DUPLICATEWAKEUPEVENTR0x0
1I2C1_SCL_DUPLICATEWAKEUPEVENTR0x0
0I2C1_SDA_DUPLICATEWAKEUPEVENTR0x0
Table 18-837 CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_2
Address offset0x0000 1B08
Physical Address0x4A00 3B08InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_NOM.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_GPU_2
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_NOM which has to be written to the CTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL [4:0] LDOVBBGPU_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_GPU_2AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-838 CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_3
Address offset0x0000 1B0C
Physical Address0x4A00 3B0CInstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_OD.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_GPU_3
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_OD which has to be written to the CTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL [4:0] LDOVBBGPU_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_GPU_3AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-839 CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_4
Address Offset0x0000 1B10
Physical Address0x4A00 3B10InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_HIGH.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_GPU_4
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_HIGH which has to be written to the CTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL [4:0] LDOVBBGPU_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_GPU_4

AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value.

R0x-
Table 18-840 CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_5
Address Offset0x0000 1B14
Physical Address0x4A00 3B14InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_PLUS.
This register also stores information about ABB configuration for that OPP.
TypeR
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_PLUS which has to be written to the CTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL[4:0] LDOVBBGPU_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_GPU_5

AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_PLUS. To get the actual value in mV, the value read from this bit field must be converted to decimal value.

R0x-
Table 18-841 CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_1
Address offset0x0000 1B1C
Physical Address0x4A00 3B1CInstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_LOW.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_MPU_1
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_LOW which has to be written to the CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL[4:0] LDOVBBMPU_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_MPU_1AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_LOW. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-842 CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_2
Address offset0x0000 1B20
Physical Address0x4A00 3B20InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_NOM.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_MPU_2
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_NOM which has to be written to the CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL[4:0] LDOVBBMPU_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_MPU_2AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-843 CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_3
Address offset0x0000 1B24
Physical Address0x4A00 3B24InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_OD.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_MPU_3
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_OD which has to be written to the CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL[4:0] LDOVBBMPU_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_MPU_3AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value.R0x-
Table 18-844 CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_4
Address Offset0x0000 1B28
Physical Address0x4A00 3B28InstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_HIGH.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_MPU_4
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_HIGH which has to be written to the CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL[4:0] LDOVBBMPU_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_MPU_4

AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value.

R0x-
Table 18-845 CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_5
Address Offset0x0000 1B2C
Physical Address0x4A00 3B2CInstanceCTRL_MODULE_CORE
DescriptionThis register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_PLUS.
This register also stores information about ABB configuration for that OPP.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDABBENVSETABBRESERVEDSTD_FUSE_OPP_VMIN_MPU_5
BitsField NameDescriptionTypeReset
31:26RESERVED

Reserved

R0x-
25ABBENR0x-
0x0: ABB is disabled
0x1: ABB is enabled
24:20VSETABBThis bit field shows the ABB LDO target value for OPP_PLUS which has to be written to the CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL[4:0] LDOVBBMPU_FBB_VSET_OUT bit field, if ABB is enabled.R0x-
19:12RESERVED

Reserved

R0x-
11:0STD_FUSE_OPP_VMIN_MPU_5

AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_PLUS. To get the actual value in mV, the value read from this bit field must be converted to decimal value.

R0x-
Table 18-846 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_0
Address Offset0x0000 1B38
Physical Address0x4A00 3B38InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_LVT_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_LVT_0R0x0
Table 18-847 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_1
Address Offset0x0000 1B3C
Physical Address0x4A00 3B3CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_LVT_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_LVT_1R0x0
Table 18-848 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_2
Address Offset0x0000 1B40
Physical Address0x4A00 3B40InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_LVT_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_LVT_2R0x0
Table 18-849 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_3
Address Offset0x0000 1B44
Physical Address0x4A00 3B44InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_LVT_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_LVT_3R0x0
Table 18-850 CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_4
Address Offset0x0000 1B48
Physical Address0x4A00 3B48InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_DSPEVE_LVT_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_DSPEVE_LVT_4R0x0
Table 18-851 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_0
Address Offset0x0000 1B4C
Physical Address0x4A00 3B4CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_IVA [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_LVT_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_LVT_0R0x0
Table 18-852 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_1
Address Offset0x0000 1B50
Physical Address0x4A00 3B50InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_IVA [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_LVT_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_LVT_1R0x0
Table 18-853 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_2
Address Offset0x0000 1B54
Physical Address0x4A00 3B54InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_IVA [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_LVT_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_LVT_2R0x0
Table 18-854 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_3
Address Offset0x0000 1B58
Physical Address0x4A00 3B58InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_IVA [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_LVT_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_LVT_3R0x0
Table 18-855 CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_4
Address Offset0x0000 1B5C
Physical Address0x4A00 3B5CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_IVA [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_IVA_LVT_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_IVA_LVT_4R0x0
Table 18-856 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_0
Address Offset0x0000 1B60
Physical Address0x4A00 3B60InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_LVT_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_LVT_0R0x0
Table 18-857 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_1
Address Offset0x0000 1B64
Physical Address0x4A00 3B64InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_LVT_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_LVT_1R0x0
Table 18-858 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_2
Address Offset0x0000 1B68
Physical Address0x4A00 3B68InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_LVT_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_LVT_2R0x0
Table 18-859 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_3
Address Offset0x0000 1B6C
Physical Address0x4A00 3B6CInstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_LVT_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_LVT_3R0x0
Table 18-860 CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_4
Address Offset0x0000 1B70
Physical Address0x4A00 3B70InstanceCTRL_MODULE_CORE
DescriptionStandard Fuse OPP VDD_CORE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_OPP_VDD_CORE_LVT_4
BitsField NameDescriptionTypeReset
31:0STD_FUSE_OPP_VDD_CORE_LVT_4R0x0
Table 18-861 CTRL_CORE_LDOSRAM_CORE_4_VOLTAGE_CTRL
Address Offset0x0000 1B74
Physical Address0x4A00 3B74InstanceCTRL_MODULE_CORE
DescriptionCORE 4th SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMCORE_4_RETMODE_MUX_CTRLLDOSRAMCORE_4_RETMODE_VSET_INLDOSRAMCORE_4_RETMODE_VSET_OUTRESERVEDLDOSRAMCORE_4_ACTMODE_MUX_CTRLLDOSRAMCORE_4_ACTMODE_VSET_INLDOSRAMCORE_4_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMCORE_4_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMCORE_4_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMCORE_4_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMCORE_4_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMCORE_4_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMCORE_4_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-862 CTRL_CORE_LDOSRAM_CORE_5_VOLTAGE_CTRL
Address Offset0x0000 1B78
Physical Address0x4A00 3B78InstanceCTRL_MODULE_CORE
DescriptionCORE 5th SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMCORE_5_RETMODE_MUX_CTRLLDOSRAMCORE_5_RETMODE_VSET_INLDOSRAMCORE_5_RETMODE_VSET_OUTRESERVEDLDOSRAMCORE_5_ACTMODE_MUX_CTRLLDOSRAMCORE_5_ACTMODE_VSET_INLDOSRAMCORE_5_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMCORE_5_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMCORE_5_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMCORE_5_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMCORE_5_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMCORE_5_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMCORE_5_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-863 CTRL_CORE_LDOSRAM_DSPEVE_2_VOLTAGE_CTRL
Address Offset0x0000 1B7C
Physical Address0x4A00 3B7CInstanceCTRL_MODULE_CORE
DescriptionDSPEVE 2nd SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMDSPEVE_2_RETMODE_MUX_CTRLLDOSRAMDSPEVE_2_RETMODE_VSET_INLDOSRAMDSPEVE_2_RETMODE_VSET_OUTRESERVEDLDOSRAMDSPEVE_2_ACTMODE_MUX_CTRLLDOSRAMDSPEVE_2_ACTMODE_VSET_INLDOSRAMDSPEVE_2_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMDSPEVE_2_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMDSPEVE_2_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMDSPEVE_2_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMDSPEVE_2_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMDSPEVE_2_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-864 CTRL_CORE_SMA_SW_2
Address Offset0x0000 1C04
Physical Address0x4A00 3C04InstanceCTRL_MODULE_CORE
DescriptionOCP Spare Register
TypeRW
313029282726252423222120191817161514131211109876543210
SMA_SW_2
BitsField NameDescriptionTypeReset
31:0SMA_SW_2

OCP spare register

RW0x0
Table 18-865 CTRL_CORE_SMA_SW_3
Address Offset0x0000 1C08
Physical Address0x4A00 3C08InstanceCTRL_MODULE_CORE
DescriptionOCP Spare Register
TypeRW
313029282726252423222120191817161514131211109876543210
SMA_SW_3
BitsField NameDescriptionTypeReset
31:0SMA_SW_3

OCP spare register

RW0x0
Table 18-866 CTRL_CORE_SMA_SW_6
Address Offset0x0000 1C14
Physical Address0x4A00 3C14InstanceCTRL_MODULE_CORE
DescriptionOCP Spare Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPLLEN_CONTROLRESERVEDPCIE_TX_RX_CONTROLRESERVEDRMII_CLK_SETTINGRESERVEDMUXSEL_32K_CLKIN
BitsField NameDescriptionTypeReset
31:29RESERVEDR0x0
28:27PLLEN_CONTROL

PLLEN control setting.

Bit [28] – Controls the CLKOUT of DPLL_USB_OTG

0x0: CLKOUT is disabled.

0x1: CLKOUT is enabled.

Bit [27] – Controls the CLKOUT of DPLL_SATA

0x0: CLKOUT is disabled.

0x1: CLKOUT is enabled.

RW0x0
26:18RESERVEDR0x0
17:16PCIE_TX_RX_CONTROL

PCIe RX and TX control of ACSPCIe.

0x0: ACSPCIe Power Down Mode

0x1: ACSPCIe TX Mode

0x2: ACSPCIe RX Mode

0x3: Reserved

RW0x0
15:9RESERVEDR0x0
8RMII_CLK_SETTING

RMII CLK setting

0x0: Internal clock from DPLL_GMAC

0x1: External clock from RMII_MHZ_50_CLK pin

RW0x0
7:1RESERVEDR0x0
0MUXSEL_32K_CLKINSetting for mux to select 32KHz clock input to PRCM. This bit must NOT be modified by software. The 32kHz clock selection is done through the device sysboot[9:8] signals.RW0x0
Table 18-867 CTRL_CORE_SMA_SW_7
Address Offset0x0000 1C18
Physical Address0x4A00 3C18InstanceCTRL_MODULE_CORE
DescriptionOCP Spare Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDMMU1_ABORT_ENABLEMMU2_ABORT_ENABLERESERVEDEDMA_TC1_WR_MMU_ROUTE_ENABLEEDMA_TC1_RD_MMU_ROUTE_ENABLEEDMA_TC0_WR_MMU_ROUTE_ENABLEEDMA_TC0_RD_MMU_ROUTE_ENABLEPCIE_SS2_MMU_ROUTE_ENABLEPCIE_SS1_MMU_ROUTE_ENABLERESERVEDPCIE_SS2_AXI2OCP_LEGACY_MODE_ENABLEPCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE
BitsField NameDescriptionTypeReset
31:18RESERVEDReservedR0x0
17MMU1_ABORT_ENABLEMMU1 abort enableRW0x0
16MMU2_ABORT_ENABLEMMU2 abort enableRW0x0
15:14RESERVEDReservedR0x0
13EDMA_TC1_WR_MMU_ROUTE_ENABLEEDMA TC1 WR traffic MMU route enableRW0x0
12EDMA_TC1_RD_MMU_ROUTE_ENABLEEDMA TC1 RD traffic MMU route enableRW0x0
11EDMA_TC0_WR_MMU_ROUTE_ENABLEEDMA TC0 WR traffic MMU route enableRW0x0
10EDMA_TC0_RD_MMU_ROUTE_ENABLEEDMA TC0 RD traffic MMU route enableRW0x0
9PCIE_SS2_MMU_ROUTE_ENABLEPCIe_SS2 MMU route enableRW0x0
8PCIE_SS1_MMU_ROUTE_ENABLEPCIe_SS1 MMU route enableRW0x0
7:2RESERVEDReservedR0x0
1PCIE_SS2_AXI2OCP_LEGACY_MODE_ENABLEPCIe_SS2 AXI2OCP legacy mode enableRW0x0
0PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLEPCIe_SS1 AXI2OCP legacy mode enableRW0x0
Table 18-868 CTRL_CORE_SMA_SW_8
Address Offset0x0000 1C1C
Physical Address0x4A00 3C1CInstanceCTRL_MODULE_CORE
DescriptionTest control inputs used by the module
TypeRW
313029282726252423222120191817161514131211109876543210
PCIE_PLL_TEST_INPUT_1
BitsField NameDescriptionTypeReset
31:0PCIE_PLL_TEST_INPUT_1

Test control inputs used by the module

RW0x0
Table 18-869 CTRL_CORE_SMA_SW_9
Address Offset0x0000 1C20
Physical Address0x4A00 3C20InstanceCTRL_MODULE_CORE
DescriptionTest control inputs used by the module
TypeRW
313029282726252423222120191817161514131211109876543210
PCIE_PLL_TEST_INPUT_2
BitsField NameDescriptionTypeReset
31:0PCIE_PLL_TEST_INPUT_2

Test control inputs used by the module

RW0x0
Table 18-870 CTRL_CORE_PCIESS1_PCS1
Address Offset0x0000 1C24
Physical Address0x4A00 3C24InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
PCIESS1_PCS_TEST_TXDATAPCIESS1_PCS_ERR_BIT_ENPCIESS1_PCS_CFG_HOLDOFFPCIESS1_PCS_DET_DELAY
BitsField NameDescriptionTypeReset
31:22PCIESS1_PCS_TEST_TXDATARW0x0
21:12PCIESS1_PCS_ERR_BIT_ENRW0x0
11:4PCIESS1_PCS_CFG_HOLDOFFRW0x0
3:0PCIESS1_PCS_DET_DELAYRW0x1
Table 18-871 CTRL_CORE_PCIESS1_PCS2
Address Offset0x0000 1C28
Physical Address0x4A00 3C28InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
PCIESS1_PCS_CFG_SYNCPCIESS1_PCS_CFG_EQ_FUNCPCIESS1_PCS_CFG_EQ_HOLDPCIESS1_PCS_CFG_EQ_INITPCIESS1_PCS_TEST_OSELRESERVEDPCIESS1_PCS_TEST_LSELRESERVEDPCIESS1_PCS_ERR_MODEPCIESS1_PCS_L1_SLEEPPCIESS1_PCS_TEST_MODEPCIESS1_PCS_ERR_LN_ENRESERVEDPCIESS1_PCS_SHORT_TIMES
BitsField NameDescriptionTypeReset
31:27PCIESS1_PCS_CFG_SYNCRW0x0
26:23PCIESS1_PCS_CFG_EQ_FUNCRW0x0
22:19PCIESS1_PCS_CFG_EQ_HOLDRW0x0
18:15PCIESS1_PCS_CFG_EQ_INITRW0x0
14:12PCIESS1_PCS_TEST_OSELRW0x0
11:10RESERVEDR0x0
9PCIESS1_PCS_TEST_LSELRW0x0
8RESERVEDR0x0
7:6PCIESS1_PCS_ERR_MODERW0x0
5PCIESS1_PCS_L1_SLEEPRW0x0
4PCIESS1_PCS_TEST_MODERW0x0
3:2PCIESS1_PCS_ERR_LN_ENRW0x0
1RESERVEDR0x0
0PCIESS1_PCS_SHORT_TIMESRW0x0
Table 18-872 CTRL_CORE_PCIESS2_PCS1
Address Offset0x0000 1C2C
Physical Address0x4A00 3C2CInstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
PCIESS2_PCS_TEST_TXDATAPCIESS2_PCS_ERR_BIT_ENPCIESS2_PCS_CFG_HOLDOFFPCIESS2_PCS_DET_DELAY
BitsField NameDescriptionTypeReset
31:22PCIESS2_PCS_TEST_TXDATARW0x0
21:12PCIESS2_PCS_ERR_BIT_ENRW0x0
11:4PCIESS2_PCS_CFG_HOLDOFFRW0x0
3:0PCIESS2_PCS_DET_DELAYRW0x1
Table 18-873 CTRL_CORE_PCIESS2_PCS2
Address Offset0x0000 1C30
Physical Address0x4A00 3C30InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
PCIESS2_PCS_CFG_SYNCPCIESS2_PCS_CFG_EQ_FUNCPCIESS2_PCS_CFG_EQ_HOLDPCIESS2_PCS_CFG_EQ_INITPCIESS2_PCS_TEST_OSELRESERVEDPCIESS2_PCS_TEST_LSELRESERVEDPCIESS2_PCS_ERR_MODEPCIESS2_PCS_L1_SLEEPPCIESS2_PCS_TEST_MODEPCIESS2_PCS_ERR_LN_ENRESERVEDPCIESS2_PCS_SHORT_TIMES
BitsField NameDescriptionTypeReset
31:27PCIESS2_PCS_CFG_SYNCRW0x0
26:23PCIESS2_PCS_CFG_EQ_FUNCRW0x0
22:19PCIESS2_PCS_CFG_EQ_HOLDRW0x0
18:15PCIESS2_PCS_CFG_EQ_INITRW0x0
14:12PCIESS2_PCS_TEST_OSELRW0x0
11:10RESERVEDR0x0
9PCIESS2_PCS_TEST_LSELRW0x0
8RESERVEDR0x0
7:6PCIESS2_PCS_ERR_MODERW0x0
5PCIESS2_PCS_L1_SLEEPRW0x0
4PCIESS2_PCS_TEST_MODERW0x0
3:2PCIESS2_PCS_ERR_LN_ENRW0x0
1RESERVEDR0x0
0PCIESS2_PCS_SHORT_TIMESRW0x0
Table 18-874 CTRL_CORE_PCIE_PCS
Address Offset0x0000 1C34
Physical Address0x4A00 3C34InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPCIESS_PCS_RC_DELAY_COUNTRESERVED
BitsField NameDescriptionTypeReset
31:24RESERVED

Reserved

R0x0
23:16PCIESS_PCS_RC_DELAY_COUNTSet to 0x96 for proper functional and compliance-mode behavior on both PCIESS1 and PCIESS2.RW0x0
15:0RESERVED

Reserved

R0x0
Table 18-875 CTRL_CORE_PCIE_PCS_REVISION
Address Offset0x0000 1C38
Physical Address0x4A00 3C38InstanceCTRL_MODULE_CORE
Descriptionpcs_revision
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPCIESS2_PCS_REVISIONPCIESS1_PCS_REVISIONRESERVED
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:23PCIESS2_PCS_REVISIONR0x0
22:20PCIESS1_PCS_REVISIONR0x0
19:0RESERVEDR0x0
Table 18-876 CTRL_CORE_PCIE_CONTROL
Address Offset0x0000 1C3C
Physical Address0x4A00 3C3CInstanceCTRL_MODULE_CORE
Descriptionserdes control selection PCIE C0 (0 default) vs PCIE B1 (1)
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPCIE_B1C0_MODE_SELRESERVEDPCIE_B0_B1_TSYNCEN
BitsField NameDescriptionTypeReset
31:3RESERVEDR0x0
2PCIE_B1C0_MODE_SEL

0x0: PCIESS1 x1 Mode and/or PCIESS2 x1 Mode

0x1: PCIESS1 x2 Mode, PCIESS2 Unused

RW0x0
1RESERVEDR0x0
0PCIE_B0_B1_TSYNCEN

0x0: PCIESS1 x1 Mode and/or PCIESS2 x1 Mode

0x1: PCIESS1 x2 Mode, PCIESS2 Unused

RW0x0
Table 18-877 CTRL_CORE_PHY_POWER_PCIESS1
Address Offset0x0000 1C40
Physical Address0x4A00 3C40InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
PCIESS1_PWRCTL_CLKFREQPCIESS1_PWRCTL_CMDRESERVED
BitsField NameDescriptionTypeReset
31:22PCIESS1_PWRCTL_CLKFREQ

Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14.

RW0x0
21:14PCIESS1_PWRCTL_CMD

Powers up/down the PCIESS1_PHY_TX and PCIESS1_PHY_RX modules.

0x0: Powers down PCIESS1_PHY_TX and PCIESS1_PHY_RX

0x1: Powers up PCIESS1_PHY_RX

0x2: Powers up PCIESS1_PHY_TX

0x3: Powers up PCIESS1_PHY_TX and PCIESS1_PHY_RX

0x4-0xFF: Reserved

RW0x0
13:0RESERVED

Reserved

R0x0
Table 18-878 CTRL_CORE_PHY_POWER_PCIESS2
Address Offset0x0000 1C44
Physical Address0x4A00 3C44InstanceCTRL_MODULE_CORE
Description
TypeRW
313029282726252423222120191817161514131211109876543210
PCIESS2_PWRCTL_CLKFREQPCIESS2_PWRCTL_CMDRESERVED
BitsField NameDescriptionTypeReset
31:22PCIESS2_PWRCTL_CLKFREQ

Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14.

RW0x0
21:14PCIESS2_PWRCTL_CMD

Powers up/down the PCIESS2_PHY_TX and PCIESS2_PHY_RX modules.

0x0: Powers down PCIESS2_PHY_TX and PCIESS2_PHY_RX

0x1: Powers up PCIESS2_PHY_RX

0x2: Powers up PCIESS2_PHY_TX

0x3: Powers up PCIESS2_PHY_TX and PCIESS2_PHY_RX

0x4-0xFF: Reserved

RW0x0
13:0RESERVED

Reserved

R0x0

18.5.5 CTRL_MODULE_WKUP Registers

18.5.6 CTRL_MODULE_WKUP Register Summary

Table 18-879 CTRL_MODULE_WKUP Registers Mapping Summary
Register NameTypeRegister Width (Bits)Address OffsetCTRL_MODULE_WKUP Base Address
RESERVED_a (a = 0 to 63)R320x0000 0000 + (a*4)0x4AE0 C000 + (a*4)
CTRL_WKUP_SEC_CTRLRW320x0000 01000x4AE0 C100
RESERVEDR320x0000 01040x4AE0 C104
CTRL_WKUP_SEC_TAPRW320x0000 01080x4AE0 C108
CTRL_WKUP_OCPREG_SPARERW320x0000 010C0x4AE0 C10C
CTRL_WKUP_SECURE_EMIF1_SDRAM_CONFIGRW320x0000 01100x4AE0 C110
RESERVEDR320x0000 01140x4AE0 C114
CTRL_WKUP_SECURE_EMIF2_SDRAM_CONFIGRW320x0000 01180x4AE0 C118
RESERVED_i (i = 0 to 6)R320x0000 011C + (i*4)0x4AE0 C11C + (i*4)
CTRL_WKUP_STD_FUSE_USB_CONFR320x0000 01380x4AE0 C138
CTRL_WKUP_STD_FUSE_CONFR320x0000 013C0x4AE0 C13C
RESERVEDR320x0000 01400x4AE0 C140
CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXTRW320x0000 01440x4AE0 C144
CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXTRW320x0000 01480x4AE0 C148
CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT_1R320x0000 014C0x4AE0 C14C
CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT_2R320x0000 01500x4AE0 C150
CTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRLRW320x0000 01540x4AE0 C154
CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRLRW320x0000 01580x4AE0 C158
CTRL_WKUP_LDOSRAM_GPU_VOLTAGE_CTRLRW320x0000 015C0x4AE0 C15C
CTRL_WKUP_LDOSRAM_MPU_VOLTAGE_CTRLRW320x0000 01600x4AE0 C160
CTRL_WKUP_LDOSRAM_CORE_VOLTAGE_CTRLRW320x0000 01640x4AE0 C164
CTRL_WKUP_LDOSRAM_MPU_2_VOLTAGE_CTRLRW320x0000 01680x4AE0 C168
RESERVED_j (j = 0 to 36)R320x0000 016C + (j*4)0x4AE0 C16C + (j*4)
CTRL_WKUP_STD_FUSE_DIE_ID_0R320x0000 02000x4AE0 C200
CTRL_WKUP_ID_CODER320x0000 02040x4AE0 C204
CTRL_WKUP_STD_FUSE_DIE_ID_1R320x0000 02080x4AE0 C208
CTRL_WKUP_STD_FUSE_DIE_ID_2R320x0000 020C0x4AE0 C20C
CTRL_WKUP_STD_FUSE_DIE_ID_3R320x0000 02100x4AE0 C210
CTRL_WKUP_STD_FUSE_PROD_ID_0R320x0000 02140x4AE0 C214
RESERVED_k (k = 0 to 292)R320x0000 0218 + (k*4)0x4AE0 C218 + (k*4)
CTRL_WKUP_CONTROL_XTAL_OSCILLATORRW320x0000 05AC0x4AE0 C5AC
RESERVEDR320x0000 05B00x4AE0 C5B0
RESERVEDR320x0000 05B40x4AE0 C5B4
RESERVEDR320x0000 05B80x4AE0 C5B8
RESERVEDR320x0000 05BC0x4AE0 C5BC
RESERVEDR320x0000 05C00x4AE0 C5C0
RESERVEDR320x0000 05C40x4AE0 C5C4
CTRL_WKUP_EFUSE_1RW320x0000 05C80x4AE0 C5C8
CTRL_WKUP_EFUSE_2RW320x0000 05CC0x4AE0 C5CC
CTRL_WKUP_EFUSE_3RW320x0000 05D00x4AE0 C5D0
CTRL_WKUP_EFUSE_4RW320x0000 05D40x4AE0 C5D4
RESERVED_m (m = 0 to 7)R320x0000 05D8 + (m*4)0x4AE0 C5D8 + (m*4)
CTRL_WKUP_EFUSE_13RW320x0000 05F80x4AE0 C5F8

18.5.7 CTRL_MODULE_WKUP Register Description

Table 18-880 CTRL_WKUP_SEC_CTRL
Address Offset0x0000 0100
Physical Address0x4AE0 C100InstanceCTRL_MODULE_WKUP
DescriptionControl Register
TypeRW
313029282726252423222120191817161514131211109876543210
SECCTRLWRDISABLERESERVEDSECURE_EMIF_CONFIG_RO_ENRESERVED
BitsField NameDescriptionTypeReset
31SECCTRLWRDISABLE

Control Register write disable control.

0x0 = Write in this register is allowed

0x1 = Write in this register is forbidden

RW0x0
30:5RESERVEDR0x0
4SECURE_EMIF_CONFIG_RO_EN

Access mode for registers:

CTRL_WKUP_EMIF1_SDRAM_CONFIG

CTRL_WKUP_EMIF2_SDRAM_CONFIG

0x0 = These registers are RW

0x1 = These registers are RO

RW0x0
3:0RESERVEDR0x0
Table 18-881 CTRL_WKUP_SEC_TAP
Address Offset0x0000 0108
Physical Address0x4AE0 C108InstanceCTRL_MODULE_WKUP
DescriptionTAP controllers register.
TypeRW
313029282726252423222120191817161514131211109876543210
SECTAPWR_DISABLERESERVEDRESERVEDRESERVEDIPU2_TAPENABLEDSP2_TAPENABLEJTAGEXT_TAPENABLEIVA_TAPENABLEMPUGLOBALDEBUG_ENABLERESERVEDIEEE1500_ENABLEP1500_ENABLEIPU1_TAPENABLEDSP1_TAPENABLEDAP_TAPENABLE
BitsField NameDescriptionTypeReset
31SECTAPWR_DISABLETAP controllers register write disable controlRW0x0
0x0: Write in this register is allowedWoco
0x1: Write in this register is forbidden
30:27RESERVEDR0x0
26RESERVEDReserved. This bit must not be modified.RW0x1
25:14RESERVEDR0x0
13IPU2_TAPENABLEIPU2 TAP controlRW0x1
0x0: IPU2 TAP controller is disabled
0x1: IPU2 TAP controller is enabled
12DSP2_TAPENABLEDSP2 TAP controlRW0x1
0x0: DSP2 TAP controller is disabled
0x1: DSP2 TAP controller is enabled
11JTAGEXT_TAPENABLEExternal JTAG expansion TAP control.RW0x1
0x0: external JTAG TAP controller is disabled
0x1: external JTAG TAP controller is enabled
10IVA_TAPENABLEIVA TAP controlRW0x1
0x0: IVA TAP controller is disabled
0x1: IVA TAP controller is enabled
9MPUGLOBALDEBUG_ENABLEMPU TAP controlRW0x1
0x0: MPU TAP controller is disabled
0x1: MPU TAP controller is enabled
8:5RESERVEDR0x0
4IEEE1500_ENABLEIEEE1500 and P1500 access enableRW0x1
0x0: P1500 controller is disabledW1toClr
0x1: P1500 controller is enabled
3P1500_ENABLEP1500 access enableRW0x1
0x0: P1500 controller is disabled
0x1: P1500 controller is enabled
2IPU1_TAPENABLEIPU1 TAP controlRW0x1
0x0: IPU1 TAP controller is disabled
0x1: IPU1 TAP controller is enabled
1DSP1_TAPENABLEDSP1 TAP controlRW0x1
0x0: DSP1 TAP controller is disabled
0x1: DSP1 TAP controller is enabled
0DAP_TAPENABLEDAP TAP controlRW0x1
0x0: DAP TAP controller is disabled
0x1: DAP TAP controller is enabled
Table 18-882 CTRL_WKUP_OCPREG_SPARE
Address Offset0x0000 010C
Physical Address0x4AE0 C10CInstanceCTRL_MODULE_WKUP
DescriptionOCP Spare Register
TypeRW
313029282726252423222120191817161514131211109876543210
OCPREG_SPARE31OCPREG_SPARE30OCPREG_SPARE29OCPREG_SPARE28OCPREG_SPARE27OCPREG_SPARE26OCPREG_SPARE25OCPREG_SPARE24OCPREG_SPARE23OCPREG_SPARE22OCPREG_SPARE21OCPREG_SPARE20OCPREG_SPARE19OCPREG_SPARE18OCPREG_SPARE17OCPREG_SPARE16OCPREG_SPARE15OCPREG_SPARE14OCPREG_SPARE13OCPREG_SPARE12OCPREG_SPARE11OCPREG_SPARE10OCPREG_SPARE9OCPREG_SPARE8OCPREG_SPARE7OCPREG_SPARE6OCPREG_SPARE5OCPREG_SPARE4OCPREG_SPARE3OCPREG_SPARE2OCPREG_SPARE1RESERVED
BitsField NameDescriptionTypeReset
31OCPREG_SPARE31

OCP spare register 31

RW0x0
30OCPREG_SPARE30

OCP spare register 30

RW0x0
29OCPREG_SPARE29

OCP spare register 29

RW0x0
28OCPREG_SPARE28

OCP spare register 28

RW0x0
27OCPREG_SPARE27

OCP spare register 27

RW0x0
26OCPREG_SPARE26

OCP spare register 26

RW0x0
25OCPREG_SPARE25

OCP spare register 25

RW0x0
24OCPREG_SPARE24

OCP spare register 24

RW0x0
23OCPREG_SPARE23

OCP spare register 23

RW0x0
22OCPREG_SPARE22

OCP spare register 22

RW0x0
21OCPREG_SPARE21

OCP spare register 21

RW0x0
20OCPREG_SPARE20

OCP spare register 20

RW0x0
19OCPREG_SPARE19

OCP spare register 19

RW0x0
18OCPREG_SPARE18

OCP spare register 18

RW0x0
17OCPREG_SPARE17

OCP spare register 17

RW0x0
16OCPREG_SPARE16

OCP spare register 16

RW0x0
15OCPREG_SPARE15

OCP spare register 15

RW0x0
14OCPREG_SPARE14

OCP spare register 14

RW0x0
13OCPREG_SPARE13

OCP spare register 13

RW0x0
12OCPREG_SPARE12

OCP spare register 12

RW0x0
11OCPREG_SPARE11

OCP spare register 11

RW0x0
10OCPREG_SPARE10

OCP spare register 10

RW0x0
9OCPREG_SPARE9

OCP spare register 9

RW0x0
8OCPREG_SPARE8

OCP spare register 8

RW0x0
7OCPREG_SPARE7

OCP spare register 7

RW0x0
6OCPREG_SPARE6

OCP spare register 6

RW0x0
5OCPREG_SPARE5

OCP spare register 5

RW0x0
4OCPREG_SPARE4

OCP spare register 4

RW0x0
3OCPREG_SPARE3

OCP spare register 3

RW0x0
2OCPREG_SPARE2

OCP spare register 2

RW0x0
1OCPREG_SPARE1

OCP spare register 1

RW0x0
0RESERVEDR0x0
Table 18-883 CTRL_WKUP_SECURE_EMIF1_SDRAM_CONFIG
Address Offset0x0000 0110
Physical Address0x4AE0 C110InstanceCTRL_MODULE_WKUP
DescriptionEMIF1 SDRAM configuration register. Its values are exported to EMIF_SDRAM_CONFIG register at POR. For bit field descriptions see EMIF_SDRAM_CONFIG register in EMIF Controller, in Memory Subsystem. Write to this register is allowed if the CTRL_WKUP_SEC_CTRL[4] SECURE_EMIF_CONFIG_RO_EN bit is set to 0x0 (default).
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEMIF1_SDRAM_IBANK_POSEMIF1_SDRAM_DDR_TERMEMIF1_SDRAM_DDR2_DDQSEMIF1_SDRAM_DYN_ODTEMIF1_SDRAM_DDR_DISABLE_DLLEMIF1_SDRAM_DRIVEEMIF1_SDRAM_CWLRESERVEDEMIF1_SDRAM_CLEMIF1_SDRAM_ROWSIZEEMIF1_SDRAM_IBANKRESERVEDEMIF1_SDRAM_PAGESIZE
BitsField NameDescriptionTypeReset
31:29RESERVEDR0x0
28:27EMIF1_SDRAM_IBANK_POS

Internal bank position.

RW0x0
26:24EMIF1_SDRAM_DDR_TERM

DDR2 and DDR3 termination resistor value.

RW0x0
23EMIF1_SDRAM_DDR2_DDQS

DDR2 differential DQS enable.

RW0x1
22:21EMIF1_SDRAM_DYN_ODT

DDR3 Dynamic ODT.

RW0x0
20EMIF1_SDRAM_DDR_DISABLE_DLL

Disable DLL select.

RW0x0
19:18EMIF1_SDRAM_DRIVE

SDRAM drive strength.

RW0x0
17:16EMIF1_SDRAM_CWL

DDR3 CAS Write latency.

RW0x0
15:14RESERVEDR0x0
13:10EMIF1_SDRAM_CL

CAS Latency.

RW0x0
9:7EMIF1_SDRAM_ROWSIZE

Row Size.

RW0x0
6:4EMIF1_SDRAM_IBANK

Internal Bank setup.

RW0x0
3RESERVEDR0x0
2:0EMIF1_SDRAM_PAGESIZE

Page Size.

RW0x0
Table 18-884 CTRL_WKUP_SECURE_EMIF2_SDRAM_CONFIG
Address Offset0x0000 0118
Physical Address0x4AE0 C118InstanceCTRL_MODULE_WKUP
DescriptionEMIF2 SDRAM register. Its values are exported to EMIF_SDRAM_CONFIG register at POR. For bit field descriptions see EMIF_SDRAM_CONFIG register in EMIF Controller, in Memory Subsystem. Write to this register is allowed if the CTRL_WKUP_SEC_CTRL[4] SECURE_EMIF_CONFIG_RO_EN bit is set to 0x0 (default).
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEMIF2_SDRAM_IBANK_POSEMIF2_SDRAM_DDR_TERMEMIF2_SDRAM_DDR2_DDQSEMIF2_SDRAM_DYN_ODTEMIF2_SDRAM_DDR_DISABLE_DLLEMIF2_SDRAM_DRIVEEMIF2_SDRAM_CWLRESERVEDEMIF2_SDRAM_CLEMIF2_SDRAM_ROWSIZEEMIF2_SDRAM_IBANKRESERVEDEMIF2_SDRAM_PAGESIZE
BitsField NameDescriptionTypeReset
31:29RESERVEDR0x0
28:27EMIF2_SDRAM_IBANK_POS

Internal bank position.

RW0x0
26:24EMIF2_SDRAM_DDR_TERM

DDR2 and DDR3 termination resistor value.

RW0x0
23EMIF2_SDRAM_DDR2_DDQS

DDR2 differential DQS enable.

RW0x1
22:21EMIF2_SDRAM_DYN_ODT

DDR3 Dynamic ODT.

RW0x0
20EMIF2_SDRAM_DDR_DISABLE_DLL

Disable DLL select.

RW0x0
19:18EMIF2_SDRAM_DRIVE

SDRAM drive strength.

RW0x0
17:16EMIF2_SDRAM_CWL

DDR3 CAS Write latency.

RW0x0
15:14RESERVEDR0x0
13:10EMIF2_SDRAM_CL

CAS Latency.

RW0x0
9:7EMIF2_SDRAM_ROWSIZE

Row Size.

RW0x0
6:4EMIF2_SDRAM_IBANK

Internal Bank setup.

RW0x0
3RESERVEDR0x0
2:0EMIF2_SDRAM_PAGESIZE

Page Size.

RW0x0
Table 18-885 CTRL_WKUP_STD_FUSE_USB_CONF
Address Offset0x0000 0138
Physical Address0x4AE0 C138InstanceCTRL_MODULE_WKUP
DescriptionStandard Fuse conf [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
USB_PROD_IDUSB_VENDOR_ID
BitsField NameDescriptionTypeReset
31:16USB_PROD_ID

USB Product Identification

R0x0
15:0USB_VENDOR_ID

USB Vendor Identification

R0x0
Table 18-886 CTRL_WKUP_STD_FUSE_CONF
Address Offset0x0000 013C
Physical Address0x4AE0 C13CInstanceCTRL_MODULE_WKUP
DescriptionStandard Fuse conf [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDSTD_FUSE_EMIF2_INITREF_DEF_DISSTD_FUSE_EMIF2_DDR3_LPDDR2NSTD_FUSE_EMIF1_INITREF_DEF_DISSTD_FUSE_EMIF1_DDR3_LPDDR2NRESERVEDSTD_FUSE_HDCP_ENABLERESERVEDSTD_FUSE_CH_SPEEDUP_DISABLERESERVEDSTD_FUSE_SGX540_3D_CLOCK_SOURCESTD_FUSE_SGX540_3D_DISABLERESERVED
BitsField NameDescriptionTypeReset
31:22RESERVEDR0x-
21STD_FUSE_EMIF2_INITREF_DEF_DIS

Disable EMIF2 DDR refresh and initialization sequence

0x1 = refresh and initialization sequence are disabled

0x0 = refresh and initialization sequence are enabled

R0x-
20STD_FUSE_EMIF2_DDR3_LPDDR2N

EMIF2 DDR3

0x1= DDR3 configured

0x0 = reserved

R0x-
19STD_FUSE_EMIF1_INITREF_DEF_DIS

Disable EMIF1 DDR refresh and initialization sequence

0x1 = refresh and initialization sequence are disabled

0x0 = refresh and initialization sequence are enabled

R0x-
18STD_FUSE_EMIF1_DDR3_LPDDR2N

EMIF1 DDR3

0x1 = DDR3 configured

0x0 = reserved

R0x-
17RESERVEDR0x-
16STD_FUSE_HDCP_ENABLE

Enable hdcp

0x0 = enables hdcp

0x1 = disables hdcp

R0x-
15:13RESERVEDR0x-
12STD_FUSE_CH_SPEEDUP_DISABLE

ROM code settings for configuration header block and speedup block. Only SW access (no hardware access).

0x0 = enables CH and speedup

0x1 = disables CH and speedup

R0x-
11:5RESERVEDR0x-
4STD_FUSE_SGX540_3D_CLOCK_SOURCE

Functional clock selection for the 3D accelerator engine

0x0 = GPU is fully enabled (DPLL_CORE/PER)

0x1 = GPU is partially enabled (DPLL_PER/8 max)

R0x-
3STD_FUSE_SGX540_3D_DISABLE

Disable the 3D accelerator engine

0x1 = SGX is disabled

0x0 = SGX is enabled

R0x-
2:0RESERVEDR0x-
Table 18-887 CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT
Address Offset0x0000 0144
Physical Address0x4AE0 C144InstanceCTRL_MODULE_WKUP
DescriptionSLICE register for emif1 and emif2
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEMIF1_NARROW_ONLYEMIF1_EN_ECCEMIF1_REG_PHY_NUM_OF_SAMPLESEMIF1_REG_PHY_SEL_LOGICEMIF1_REG_PHY_ALL_DQ_MPR_RD_RESPEMIF1_REG_PHY_OUTPUT_STATUS_SELECTRESERVEDEMIF1_SDRAM_DISABLE_RESETEMIF1_PHY_RD_LOCAL_ODTRESERVEDEMIF1_DFI_CLOCK_PHASE_CTRLEMIF1_EN_SLICE_2EMIF1_EN_SLICE_1EMIF1_EN_SLICE_0
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17EMIF1_NARROW_ONLY

EMIF1 operates in narrow mode, to allow for data macros to be powered down to save power

0x0 = narrow mode disabled

0x1 = narrow mode enabled

RW0x0
16EMIF1_EN_ECC

EMIF1 ECC enable

0x0 = ECC is disabled

0x1 = ECC is enabled

RW0x0
15:14EMIF1_REG_PHY_NUM_OF_SAMPLES

Controls the number of DQ samples required for read leveling. The recommended setting for full leveling is 0x3 (128 samples) .

0x0 = 4 samples

0x1 = 8 samples.

0x2 = 16 samples

0x3 = 128 samples

RW0x0
13EMIF1_REG_PHY_SEL_LOGIC

Selects an algorithm for read leveling. The use of algorithm 1 (set by default) is recommended.

0x0 = Algorithm 1 is used

0x1 = Algorithm 2 is used

RW0x0
12EMIF1_REG_PHY_ALL_DQ_MPR_RD_RESP

Analysis method of DQ bits during read leveling.

0x0: if the DRAM provides a read response on only one DQ bit (this can be any bit, since in this mode all 8 DQ bits are OR-ed together). This is the default setting and works with all memory types (memories send responses on all DQ bits or on a single DQ bit).

0x1: if the DRAM provides a read response on all DQ bits.

RW0x0
11:9EMIF1_REG_PHY_OUTPUT_STATUS_SELECT

Selects the status to be observed on the outputs of the DDR PHYs through CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT_1 register.

0x0 = selects phy_reg_rdlvl_start_ratio[7:0]

0x1 = selects phy_reg_rdlvl_start_ratio[15:8]

0x2 = selects phy_reg_rdlvl_end_ratio[7:0]

0x3 = selects phy_reg_rdlvl_end_ratio[15:8]

RW0x0
8RESERVEDR0x1
7EMIF1_SDRAM_DISABLE_RESET

DDR3 SDRAM reset disable.

0x0 = DDR3 SDRAM reset signal is enabled. It can be asserted by EMIF

0x1 = DDR3 SDRAM reset signal is disabled. It is forbidden to EMIF to assert it.

RW0x0
6:5EMIF1_PHY_RD_LOCAL_ODT

Control of ODT (on – die termination) settings for the device DDR I/Os. ODT is enabled only during read operations when termination is required.

0x0 = ODT disabled

0x1= 60 Ohms

0x2 = 80 Ohms

0x3 =120 Ohms

RW0x0
4RESERVEDRW0x0
3EMIF1_DFI_CLOCK_PHASE_CTRL

EMIF_FICLK clock phase control (shifting by 180°). For normal operation this bit must always be set to 0x0 (disabled).

RW0x0
2EMIF1_EN_SLICE_2

Enable command PHY 2. When using DDR3 this bit can be set to 0x0 or 0x1. For lower power consumption 0x0 is used.

RW0x1
1EMIF1_EN_SLICE_1

Enable command PHY 1. 0x1 is the mandatory setting if DDR3 is used. EMIF1_EN_SLICE_0 and EMIF1_EN_SLICE_1 have to be programmed with the same value.

RW0x1
0EMIF1_EN_SLICE_0

Enable command PHY 0. 0x1 is the mandatory setting if DDR3 is used. EMIF1_EN_SLICE_0 and EMIF1_EN_SLICE_1 have to be programmed with the same value.

RW0x1
Table 18-888 CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT
Address Offset0x0000 0148
Physical Address0x4AE0 C148InstanceCTRL_MODULE_WKUP
DescriptionSLICE register for emif1 and emif2
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEMIF2_NARROW_ONLYRESERVEDEMIF2_REG_PHY_NUM_OF_SAMPLESEMIF2_REG_PHY_SEL_LOGICEMIF2_REG_PHY_ALL_DQ_MPR_RD_RESPEMIF2_REG_PHY_OUTPUT_STATUS_SELECTRESERVEDEMIF2_SDRAM_DISABLE_RESETEMIF2_PHY_RD_LOCAL_ODTRESERVEDEMIF2_DFI_CLOCK_PHASE_CTRLEMIF2_EN_SLICE_2EMIF2_EN_SLICE_1EMIF2_EN_SLICE_0
BitsField NameDescriptionTypeReset
31:18RESERVEDR0x0
17EMIF2_NARROW_ONLY

EMIF2 operates in narrow mode, to allow for data macros to be powered down to save power

0x0 = narrow mode disabled

0x1 = narrow mode enabled

RW0x0
16RESERVEDR0x0
15:14EMIF2_REG_PHY_NUM_OF_SAMPLES

Controls the number of DQ samples required for read leveling. The recommended setting for full leveling is 0x3 (128 samples) .

0x0 = 4 samples

0x1 = 8 samples.

0x2 = 16 samples

0x3 = 128 samples

RW0x0
13EMIF2_REG_PHY_SEL_LOGIC

Selects an algorithm for read leveling. The use of algorithm 1 (set by default) is recommended.

0x0 = Algorithm 1 is used

0x1 = Algorithm 2 is used

RW0x0
12EMIF2_REG_PHY_ALL_DQ_MPR_RD_RESP

Analysis method of DQ bits during read leveling.

0x0: if the DRAM provides a read response on only one DQ bit (this can be any bit, since in this mode all 8 DQ bits are OR-ed together). This is the default setting and works with all memory types (memories send responses on all DQ bits or on a single DQ bit).

0x1: if the DRAM provides a read response on all DQ bits.

RW0x0
11:9EMIF2_REG_PHY_OUTPUT_STATUS_SELECT

Selects the status to be observed on the outputs of the DDR PHYs through CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT_2 register.

0x0 = selects phy_reg_rdlvl_start_ratio[7:0]

0x1 = selects phy_reg_rdlvl_start_ratio[15:8]

0x2 = selects phy_reg_rdlvl_end_ratio[7:0]

0x3 = selects phy_reg_rdlvl_end_ratio[15:8]

RW0x0
8RESERVEDR0x1
7EMIF2_SDRAM_DISABLE_RESET

DDR3 SDRAM reset disable.

0x0 = DDR3 SDRAM reset signal is enabled. It can be asserted by EMIF

0x1 = DDR3 SDRAM reset signal is disabled. It is forbidden to EMIF to assert it.

RW0x0
6:5EMIF2_PHY_RD_LOCAL_ODT

Control of ODT (on – die termination) settings for the device DDR I/Os. ODT is enabled only during read operations when termination is required.

0x0 = ODT disabled

0x1= 60 Ohms

0x2 = 80 Ohms

0x3 =120 Ohms

RW0x0
4RESERVEDR0x0
3EMIF2_DFI_CLOCK_PHASE_CTRL

EMIF_FICLK clock phase control (shifting by 180°). For normal operation this bit must always be set to 0x0 (disabled).

RW0x0
2EMIF2_EN_SLICE_2

Enable command PHY 2. When using DDR3 this bit can be set to 0x0 or 0x1. For lower power consumption 0x0 is used.

RW0x1
1EMIF2_EN_SLICE_1

Enable command PHY 1. 0x1 is the mandatory setting if DDR3 is used. EMIF2_EN_SLICE_0 and EMIF2_EN_SLICE_1 have to be programmed with the same value.

RW0x1
0EMIF2_EN_SLICE_0

Enable command PHY 0. 0x1 is the mandatory setting if DDR3 is used. EMIF2_EN_SLICE_0 and EMIF2_EN_SLICE_1 have to be programmed with the same value.

RW0x1
Table 18-889 CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT_1
Address Offset0x0000 014C
Physical Address0x4AE0 C14CInstanceCTRL_MODULE_WKUP
Description
TypeR
313029282726252423222120191817161514131211109876543210
EMIF1_PHY_REG_READ_DATA_EYE_LVL
BitsField NameDescriptionTypeReset
31:0EMIF1_PHY_REG_READ_DATA_EYE_LVLR0x0
Table 18-890 CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT_2
Address Offset0x0000 0150
Physical Address0x4AE0 C150InstanceCTRL_MODULE_WKUP
Description
TypeR
313029282726252423222120191817161514131211109876543210
EMIF2_PHY_REG_READ_DATA_EYE_LVL
BitsField NameDescriptionTypeReset
31:0EMIF2_PHY_REG_READ_DATA_EYE_LVLR0x0
Table 18-891 CTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL
Address Offset0x0000 0154
Physical Address0x4AE0 C154InstanceCTRL_MODULE_WKUP
DescriptionGPU Voltage Body Bias LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOVBBGPU_FBB_MUX_CTRLLDOVBBGPU_FBB_VSET_INLDOVBBGPU_FBB_VSET_OUT
BitsField NameDescriptionTypeReset
31:11RESERVEDR0x0
10LDOVBBGPU_FBB_MUX_CTRL

Override control of EFUSE Forward Body Bias voltage value

0x0 = efuse value is used

0x1 = override value is used

RW0x0
9:5LDOVBBGPU_FBB_VSET_IN

EFUSE Forward Body Bias voltage value

R0x0
4:0LDOVBBGPU_FBB_VSET_OUT

Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_x[24:20] VSETABB bit fields. This value applies if LDOVBBGPU_FBB_MUX_CTRL is set to 0x1.

RW0x0
Table 18-892 CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL
Address Offset0x0000 0158
Physical Address0x4AE0 C158InstanceCTRL_MODULE_WKUP
DescriptionMPU Voltage Body Bias LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOVBBMPU_FBB_MUX_CTRLLDOVBBMPU_FBB_VSET_INLDOVBBMPU_FBB_VSET_OUT
BitsField NameDescriptionTypeReset
31:11RESERVEDR0x0
10LDOVBBMPU_FBB_MUX_CTRL

Override control of EFUSE Forward Body Bias voltage value

0x0 = efuse value is used

0x1 = override value is used

RW0x0
9:5LDOVBBMPU_FBB_VSET_IN

EFUSE Forward Body Bias voltage value

R0x0
4:0LDOVBBMPU_FBB_VSET_OUT

Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_x[24:20] VSETABB bit fields. This value applies if LDOVBBMPU_FBB_MUX_CTRL is set to 0x1.

RW0x0
Table 18-893 CTRL_WKUP_LDOSRAM_GPU_VOLTAGE_CTRL
Address Offset0x0000 015C
Physical Address0x4AE0 C15CInstanceCTRL_MODULE_WKUP
DescriptionGPU SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMGPU_RETMODE_MUX_CTRLLDOSRAMGPU_RETMODE_VSET_INLDOSRAMGPU_RETMODE_VSET_OUTRESERVEDLDOSRAMGPU_ACTMODE_MUX_CTRLLDOSRAMGPU_ACTMODE_VSET_INLDOSRAMGPU_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMGPU_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMGPU_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMGPU_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMGPU_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMGPU_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMGPU_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-894 CTRL_WKUP_LDOSRAM_MPU_VOLTAGE_CTRL
Address Offset0x0000 0160
Physical Address0x4AE0 C160InstanceCTRL_MODULE_WKUP
DescriptionMPU SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMMPU_RETMODE_MUX_CTRLLDOSRAMMPU_RETMODE_VSET_INLDOSRAMMPU_RETMODE_VSET_OUTRESERVEDLDOSRAMMPU_ACTMODE_MUX_CTRLLDOSRAMMPU_ACTMODE_VSET_INLDOSRAMMPU_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMMPU_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMMPU_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMMPU_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMMPU_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMMPU_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMMPU_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-895 CTRL_WKUP_LDOSRAM_CORE_VOLTAGE_CTRL
Address Offset0x0000 0164
Physical Address0x4AE0 C164InstanceCTRL_MODULE_WKUP
DescriptionCore SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMCORE_RETMODE_MUX_CTRLLDOSRAMCORE_RETMODE_VSET_INLDOSRAMCORE_RETMODE_VSET_OUTRESERVEDLDOSRAMCORE_ACTMODE_MUX_CTRLLDOSRAMCORE_ACTMODE_VSET_INLDOSRAMCORE_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMCORE_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMCORE_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMCORE_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMCORE_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMCORE_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMCORE_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-896 CTRL_WKUP_LDOSRAM_MPU_2_VOLTAGE_CTRL
Address Offset0x0000 0168
Physical Address0x4AE0 C168InstanceCTRL_MODULE_WKUP
DescriptionMPU 2nd SRAM LDO Control register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDLDOSRAMMPU_2_RETMODE_MUX_CTRLLDOSRAMMPU_2_RETMODE_VSET_INLDOSRAMMPU_2_RETMODE_VSET_OUTRESERVEDLDOSRAMMPU_2_ACTMODE_MUX_CTRLLDOSRAMMPU_2_ACTMODE_VSET_INLDOSRAMMPU_2_ACTMODE_VSET_OUT
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26LDOSRAMMPU_2_RETMODE_MUX_CTRLOverride control of EFUSE Retention Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
25:21LDOSRAMMPU_2_RETMODE_VSET_INEFUSE Retention Mode Voltage value (vset[9:5])R0x0
20:16LDOSRAMMPU_2_RETMODE_VSET_OUTOverride value for Retention Mode VoltageRW0x0
15:11RESERVEDR0x0
10LDOSRAMMPU_2_ACTMODE_MUX_CTRLOverride control of EFUSE Active Mode Voltage valueRW0x0
0x0: eFuse value is used
0x1: Override value is used
9:5LDOSRAMMPU_2_ACTMODE_VSET_INEFUSE Active Mode Voltage value (vset[4:0])R0x0
4:0LDOSRAMMPU_2_ACTMODE_VSET_OUTOverride value for Active Mode Voltage valueRW0x0
Table 18-897 CTRL_WKUP_STD_FUSE_DIE_ID_0
Address Offset0x0000 0200
Physical Address0x4AE0 C200InstanceCTRL_MODULE_WKUP
DescriptionDie ID Register : Part 0. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_DIE_ID_0
BitsField NameDescriptionTypeReset
31:0STD_FUSE_DIE_ID_0R0x0
Table 18-898 CTRL_WKUP_ID_CODE
Address Offset0x0000 0204
Physical Address0x4AE0 C204InstanceCTRL_MODULE_WKUP
DescriptionID_CODE Key Register
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_IDCODE
BitsField NameDescriptionTypeReset
31:0STD_FUSE_IDCODER0x0
Table 18-899 CTRL_WKUP_STD_FUSE_DIE_ID_1
Address Offset0x0000 0208
Physical Address0x4AE0 C208InstanceCTRL_MODULE_WKUP
DescriptionDie ID Register : Part 1. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_DIE_ID_1
BitsField NameDescriptionTypeReset
31:0STD_FUSE_DIE_ID_1R0x0
Table 18-900 CTRL_WKUP_STD_FUSE_DIE_ID_2
Address Offset0x0000 020C
Physical Address0x4AE0 C20CInstanceCTRL_MODULE_WKUP
DescriptionDie ID Register : Part 2. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_DIE_ID_2
BitsField NameDescriptionTypeReset
31:0STD_FUSE_DIE_ID_2R0x0
Table 18-901 CTRL_WKUP_STD_FUSE_DIE_ID_3
Address Offset0x0000 0210
Physical Address0x4AE0 C210InstanceCTRL_MODULE_WKUP
DescriptionDie ID Register : Part 3. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_DIE_ID_3
BitsField NameDescriptionTypeReset
31:0STD_FUSE_DIE_ID_3R0x0
Table 18-902 CTRL_WKUP_STD_FUSE_PROD_ID_0
Address Offset0x0000 0214
Physical Address0x4AE0 C214InstanceCTRL_MODULE_WKUP
DescriptionProd ID Register : Part 0. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.
TypeR
313029282726252423222120191817161514131211109876543210
STD_FUSE_PROD_ID
BitsField NameDescriptionTypeReset
31:0STD_FUSE_PROD_IDR0x0
Table 18-903 CTRL_WKUP_CONTROL_XTAL_OSCILLATOR
Address Offset0x0000 05AC
Physical Address0x4AE0 C5ACInstanceCTRL_MODULE_WKUP
DescriptionXTAL OSCILLATOR control
TypeRW
313029282726252423222120191817161514131211109876543210
OSCILLATOR0_BOOSTOSCILLATOR0_OS_OUTOSCILLATOR1_BOOSTOSCILLATOR1_OS_OUTRESERVED
BitsField NameDescriptionTypeReset
31OSCILLATOR0_BOOST

Fast startup control of OSC0

0x0 = Fast startup is disabled

0x1 = Fast startup is enabled

RW0x1
30OSCILLATOR0_OS_OUT

Oscillator output of OSC0

0x0 = low to high transition in BOOST mode

0x1 = BOOST is disabled

R0x0
29OSCILLATOR1_BOOST

Fast startup control of OSC1

0x0 = Fast startup is disabled

0x1 = Fast startup is enabled

RW0x1
28OSCILLATOR1_OS_OUT

Oscillator output of OSC1

0x0 = low to high transition in BOOST mode

0x1 = BOOST is disabled

R0x0
27:0RESERVEDR0x0
Table 18-904 CTRL_WKUP_EFUSE_1
Address Offset0x0000 05C8
Physical Address0x4AE0 C5C8InstanceCTRL_MODULE_WKUP
DescriptionEFUSE compensation 1
TypeRW
313029282726252423222120191817161514131211109876543210
DDRDIFF_PTV_NORTH_SIDE_N5DDRDIFF_PTV_NORTH_SIDE_N4DDRDIFF_PTV_NORTH_SIDE_N3DDRDIFF_PTV_NORTH_SIDE_N2DDRDIFF_PTV_NORTH_SIDE_N1DDRDIFF_PTV_NORTH_SIDE_N0DDRDIFF_PTV_NORTH_SIDE_P5DDRDIFF_PTV_NORTH_SIDE_P4DDRDIFF_PTV_NORTH_SIDE_P3DDRDIFF_PTV_NORTH_SIDE_P2DDRDIFF_PTV_NORTH_SIDE_P1DDRDIFF_PTV_NORTH_SIDE_P0DDRDIFF_PTV_EAST_SIDE_N5DDRDIFF_PTV_EAST_SIDE_N4DDRDIFF_PTV_EAST_SIDE_N3DDRDIFF_PTV_EAST_SIDE_N2DDRDIFF_PTV_EAST_SIDE_N1DDRDIFF_PTV_EAST_SIDE_N0DDRDIFF_PTV_EAST_SIDE_P5DDRDIFF_PTV_EAST_SIDE_P4DDRDIFF_PTV_EAST_SIDE_P3DDRDIFF_PTV_EAST_SIDE_P2DDRDIFF_PTV_EAST_SIDE_P1DDRDIFF_PTV_EAST_SIDE_P0RESERVED
BitsField NameDescriptionTypeReset
31DDRDIFF_PTV_NORTH_SIDE_N5RW0x0
30DDRDIFF_PTV_NORTH_SIDE_N4RW0x0
29DDRDIFF_PTV_NORTH_SIDE_N3RW0x0
28DDRDIFF_PTV_NORTH_SIDE_N2RW0x0
27DDRDIFF_PTV_NORTH_SIDE_N1RW0x0
26DDRDIFF_PTV_NORTH_SIDE_N0RW0x0
25DDRDIFF_PTV_NORTH_SIDE_P5RW0x0
24DDRDIFF_PTV_NORTH_SIDE_P4RW0x0
23DDRDIFF_PTV_NORTH_SIDE_P3RW0x0
22DDRDIFF_PTV_NORTH_SIDE_P2RW0x0
21DDRDIFF_PTV_NORTH_SIDE_P1RW0x0
20DDRDIFF_PTV_NORTH_SIDE_P0RW0x0
19DDRDIFF_PTV_EAST_SIDE_N5RW0x0
18DDRDIFF_PTV_EAST_SIDE_N4RW0x0
17DDRDIFF_PTV_EAST_SIDE_N3RW0x0
16DDRDIFF_PTV_EAST_SIDE_N2RW0x0
15DDRDIFF_PTV_EAST_SIDE_N1RW0x0
14DDRDIFF_PTV_EAST_SIDE_N0RW0x0
13DDRDIFF_PTV_EAST_SIDE_P5RW0x0
12DDRDIFF_PTV_EAST_SIDE_P4RW0x0
11DDRDIFF_PTV_EAST_SIDE_P3RW0x0
10DDRDIFF_PTV_EAST_SIDE_P2RW0x0
9DDRDIFF_PTV_EAST_SIDE_P1RW0x0
8DDRDIFF_PTV_EAST_SIDE_P0RW0x0
7:0RESERVEDR0x0
Table 18-905 CTRL_WKUP_EFUSE_2
Address Offset0x0000 05CC
Physical Address0x4AE0 C5CCInstanceCTRL_MODULE_WKUP
DescriptionEFUSE compensation 2
TypeRW
313029282726252423222120191817161514131211109876543210
DDRDIFF_PTV_SOUTH_SIDE_N5DDRDIFF_PTV_SOUTH_SIDE_N4DDRDIFF_PTV_SOUTH_SIDE_N3DDRDIFF_PTV_SOUTH_SIDE_N2DDRDIFF_PTV_SOUTH_SIDE_N1DDRDIFF_PTV_SOUTH_SIDE_N0DDRDIFF_PTV_SOUTH_SIDE_P5DDRDIFF_PTV_SOUTH_SIDE_P4DDRDIFF_PTV_SOUTH_SIDE_P3DDRDIFF_PTV_SOUTH_SIDE_P2DDRDIFF_PTV_SOUTH_SIDE_P1DDRDIFF_PTV_SOUTH_SIDE_P0DDRDIFF_PTV_WEST_SIDE_N5DDRDIFF_PTV_WEST_SIDE_N4DDRDIFF_PTV_WEST_SIDE_N3DDRDIFF_PTV_WEST_SIDE_N2DDRDIFF_PTV_WEST_SIDE_N1DDRDIFF_PTV_WEST_SIDE_N0DDRDIFF_PTV_WEST_SIDE_P5DDRDIFF_PTV_WEST_SIDE_P4DDRDIFF_PTV_WEST_SIDE_P3DDRDIFF_PTV_WEST_SIDE_P2DDRDIFF_PTV_WEST_SIDE_P1DDRDIFF_PTV_WEST_SIDE_P0RESERVED
BitsField NameDescriptionTypeReset
31DDRDIFF_PTV_SOUTH_SIDE_N5RW0x0
30DDRDIFF_PTV_SOUTH_SIDE_N4RW0x0
29DDRDIFF_PTV_SOUTH_SIDE_N3RW0x0
28DDRDIFF_PTV_SOUTH_SIDE_N2RW0x0
27DDRDIFF_PTV_SOUTH_SIDE_N1RW0x0
26DDRDIFF_PTV_SOUTH_SIDE_N0RW0x0
25DDRDIFF_PTV_SOUTH_SIDE_P5RW0x0
24DDRDIFF_PTV_SOUTH_SIDE_P4RW0x0
23DDRDIFF_PTV_SOUTH_SIDE_P3RW0x0
22DDRDIFF_PTV_SOUTH_SIDE_P2RW0x0
21DDRDIFF_PTV_SOUTH_SIDE_P1RW0x0
20DDRDIFF_PTV_SOUTH_SIDE_P0RW0x0
19DDRDIFF_PTV_WEST_SIDE_N5RW0x0
18DDRDIFF_PTV_WEST_SIDE_N4RW0x0
17DDRDIFF_PTV_WEST_SIDE_N3RW0x0
16DDRDIFF_PTV_WEST_SIDE_N2RW0x0
15DDRDIFF_PTV_WEST_SIDE_N1RW0x0
14DDRDIFF_PTV_WEST_SIDE_N0RW0x0
13DDRDIFF_PTV_WEST_SIDE_P5RW0x0
12DDRDIFF_PTV_WEST_SIDE_P4RW0x0
11DDRDIFF_PTV_WEST_SIDE_P3RW0x0
10DDRDIFF_PTV_WEST_SIDE_P2RW0x0
9DDRDIFF_PTV_WEST_SIDE_P1RW0x0
8DDRDIFF_PTV_WEST_SIDE_P0RW0x0
7:0RESERVEDR0x0
Table 18-906 CTRL_WKUP_EFUSE_3
Address Offset0x0000 05D0
Physical Address0x4AE0 C5D0InstanceCTRL_MODULE_WKUP
DescriptionEFUSE compensation 3
TypeRW
313029282726252423222120191817161514131211109876543210
DDRSE_PTV_NORTH_SIDE_N5DDRSE_PTV_NORTH_SIDE_N4DDRSE_PTV_NORTH_SIDE_N3DDRSE_PTV_NORTH_SIDE_N2DDRSE_PTV_NORTH_SIDE_N1DDRSE_PTV_NORTH_SIDE_N0DDRSE_PTV_NORTH_SIDE_P5DDRSE_PTV_NORTH_SIDE_P4DDRSE_PTV_NORTH_SIDE_P3DDRSE_PTV_NORTH_SIDE_P2DDRSE_PTV_NORTH_SIDE_P1DDRSE_PTV_NORTH_SIDE_P0DDRSE_PTV_EAST_SIDE_N5DDRSE_PTV_EAST_SIDE_N4DDRSE_PTV_EAST_SIDE_N3DDRSE_PTV_EAST_SIDE_N2DDRSE_PTV_EAST_SIDE_N1DDRSE_PTV_EAST_SIDE_N0DDRSE_PTV_EAST_SIDE_P5DDRSE_PTV_EAST_SIDE_P4DDRSE_PTV_EAST_SIDE_P3DDRSE_PTV_EAST_SIDE_P2DDRSE_PTV_EAST_SIDE_P1DDRSE_PTV_EAST_SIDE_P0RESERVED
BitsField NameDescriptionTypeReset
31DDRSE_PTV_NORTH_SIDE_N5RW0x0
30DDRSE_PTV_NORTH_SIDE_N4RW0x0
29DDRSE_PTV_NORTH_SIDE_N3RW0x0
28DDRSE_PTV_NORTH_SIDE_N2RW0x0
27DDRSE_PTV_NORTH_SIDE_N1RW0x0
26DDRSE_PTV_NORTH_SIDE_N0RW0x0
25DDRSE_PTV_NORTH_SIDE_P5RW0x0
24DDRSE_PTV_NORTH_SIDE_P4RW0x0
23DDRSE_PTV_NORTH_SIDE_P3RW0x0
22DDRSE_PTV_NORTH_SIDE_P2RW0x0
21DDRSE_PTV_NORTH_SIDE_P1RW0x0
20DDRSE_PTV_NORTH_SIDE_P0RW0x0
19DDRSE_PTV_EAST_SIDE_N5RW0x0
18DDRSE_PTV_EAST_SIDE_N4RW0x0
17DDRSE_PTV_EAST_SIDE_N3RW0x0
16DDRSE_PTV_EAST_SIDE_N2RW0x0
15DDRSE_PTV_EAST_SIDE_N1RW0x0
14DDRSE_PTV_EAST_SIDE_N0RW0x0
13DDRSE_PTV_EAST_SIDE_P5RW0x0
12DDRSE_PTV_EAST_SIDE_P4RW0x0
11DDRSE_PTV_EAST_SIDE_P3RW0x0
10DDRSE_PTV_EAST_SIDE_P2RW0x0
9DDRSE_PTV_EAST_SIDE_P1RW0x0
8DDRSE_PTV_EAST_SIDE_P0RW0x0
7:0RESERVEDR0x0
Table 18-907 CTRL_WKUP_EFUSE_4
Address Offset0x0000 05D4
Physical Address0x4AE0 C5D4InstanceCTRL_MODULE_WKUP
DescriptionEFUSE compensation 4
TypeRW
313029282726252423222120191817161514131211109876543210
DDRSE_PTV_SOUTH_SIDE_N5DDRSE_PTV_SOUTH_SIDE_N4DDRSE_PTV_SOUTH_SIDE_N3DDRSE_PTV_SOUTH_SIDE_N2DDRSE_PTV_SOUTH_SIDE_N1DDRSE_PTV_SOUTH_SIDE_N0DDRSE_PTV_SOUTH_SIDE_P5DDRSE_PTV_SOUTH_SIDE_P4DDRSE_PTV_SOUTH_SIDE_P3DDRSE_PTV_SOUTH_SIDE_P2DDRSE_PTV_SOUTH_SIDE_P1DDRSE_PTV_SOUTH_SIDE_P0DDRSE_PTV_WEST_SIDE_N5DDRSE_PTV_WEST_SIDE_N4DDRSE_PTV_WEST_SIDE_N3DDRSE_PTV_WEST_SIDE_N2DDRSE_PTV_WEST_SIDE_N1DDRSE_PTV_WEST_SIDE_N0DDRSE_PTV_WEST_SIDE_P5DDRSE_PTV_WEST_SIDE_P4DDRSE_PTV_WEST_SIDE_P3DDRSE_PTV_WEST_SIDE_P2DDRSE_PTV_WEST_SIDE_P1DDRSE_PTV_WEST_SIDE_P0RESERVED
BitsField NameDescriptionTypeReset
31DDRSE_PTV_SOUTH_SIDE_N5RW0x0
30DDRSE_PTV_SOUTH_SIDE_N4RW0x0
29DDRSE_PTV_SOUTH_SIDE_N3RW0x0
28DDRSE_PTV_SOUTH_SIDE_N2RW0x0
27DDRSE_PTV_SOUTH_SIDE_N1RW0x0
26DDRSE_PTV_SOUTH_SIDE_N0RW0x0
25DDRSE_PTV_SOUTH_SIDE_P5RW0x0
24DDRSE_PTV_SOUTH_SIDE_P4RW0x0
23DDRSE_PTV_SOUTH_SIDE_P3RW0x0
22DDRSE_PTV_SOUTH_SIDE_P2RW0x0
21DDRSE_PTV_SOUTH_SIDE_P1RW0x0
20DDRSE_PTV_SOUTH_SIDE_P0RW0x0
19DDRSE_PTV_WEST_SIDE_N5RW0x0
18DDRSE_PTV_WEST_SIDE_N4RW0x0
17DDRSE_PTV_WEST_SIDE_N3RW0x0
16DDRSE_PTV_WEST_SIDE_N2RW0x0
15DDRSE_PTV_WEST_SIDE_N1RW0x0
14DDRSE_PTV_WEST_SIDE_N0RW0x0
13DDRSE_PTV_WEST_SIDE_P5RW0x0
12DDRSE_PTV_WEST_SIDE_P4RW0x0
11DDRSE_PTV_WEST_SIDE_P3RW0x0
10DDRSE_PTV_WEST_SIDE_P2RW0x0
9DDRSE_PTV_WEST_SIDE_P1RW0x0
8DDRSE_PTV_WEST_SIDE_P0RW0x0
7:0RESERVEDR0x0
Table 18-908 CTRL_WKUP_EFUSE_13
Address Offset0x0000 05F8
Physical Address0x4AE0 C5F8InstanceCTRL_MODULE_WKUP
Description
TypeRW
313029282726252423222120191817161514131211109876543210
SDIO1833_PTV_N5SDIO1833_PTV_N4SDIO1833_PTV_N3SDIO1833_PTV_N2SDIO1833_PTV_N1SDIO1833_PTV_N0SDIO1833_PTV_P5SDIO1833_PTV_P4SDIO1833_PTV_P3SDIO1833_PTV_P2SDIO1833_PTV_P1SDIO1833_PTV_P0RESERVED
BitsField NameDescriptionTypeReset
31SDIO1833_PTV_N5RW0x0
30SDIO1833_PTV_N4RW0x0
29SDIO1833_PTV_N3RW0x0
28SDIO1833_PTV_N2RW0x0
27SDIO1833_PTV_N1RW0x0
26SDIO1833_PTV_N0RW0x0
25SDIO1833_PTV_P5RW0x0
24SDIO1833_PTV_P4RW0x0
23SDIO1833_PTV_P3RW0x0
22SDIO1833_PTV_P2RW0x0
21SDIO1833_PTV_P1RW0x0
20SDIO1833_PTV_P0RW0x0
19:0RESERVEDR0x0