MPU_AXI2OCP provides a protocol bridge between buses and also serves as a small local interconnect to:
- Handle traffic to the L3_MAIN interconnect
- Configure local configuration registers in the MPU subsystem
Main features of MPU_AXI2OCP:
- Connects to the L3_MAIN interconnect through a
64-bit port. The interface frequency is configurable between one fourth (default
value) and one eighth of the MPU_DPLL_CLK clock signal frequency. This is
programmable in the global PRCM register CM_MPU_MPU_CLKCTRL[25:24]
CLKSEL_EMIF_DIV_MODE bit. For CM_MPU_MPU_CLKCTRL register description, see
Power, Reset, and Clock Management
- Connects to the CS_STM module through a 32-bit AXI interface (for software instrumentation)
- Connection to the following modules for register configuration:
- MPU_MA
- MPU_PRCM
- MPU_WUGEN
- MPU_WD_TIMER
- Contains internal configuration register related
to the MPU_MA function (MA_PRIORITY)
- Supports memory barrier instruction
- Supports single-request-multiple-data (data handshaking) burst mode to pipeline requests
- Supports multiple outstanding requests
- Supports posted and nonposted write transactions,
based on the attributes of the transactions coming from the Cortex-A15
processor. Software can override all writes from the MPU_AXI2OCP to the L3_MAIN
interconnect to be nonposted, regardless of the attributes of the transactions
coming from the Arm Cortex-A15 processor, by setting the Control Module register
CTRL_CORE_MPU_FORCEWRNP[0] MPU_FORCEWRNP bit to 0x1. This bit must not be
changed until the transfer completes. For CTRL_CORE_MPU_FORCEWRNP register
description, see Control Module.