SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
Table 30-26 shows the sequence for configuring EDMA transfer for Soft-Decisions Mode. The parameters should be set as:
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Intermediate transfer complete chaining is disabled | EDMA.EDMA_TPCC_OPT_n[23] ITCCHEN | 0x0: Disable |
Transfer complete chaining is disabled | EDMA.EDMA_TPCC_OPT_n[22] TCCHEN | 0x0: Disable |
Intermediate transfer complete interrupt is disabled | EDMA.EDMA_TPCC_OPT_n[21] ITCINTEN | 0x0: Disable |
Transfer complete interrupt is disabled | EDMA.EDMA_TPCC_OPT_n[20] TCINTEN | 0x0: Disable |
Backward compatibility mode | EDMA.EDMA_TPCC_OPT_n[19] WIMODE | 0x0: Normal operation |
Transfer complete code | EDMA.EDMA_TPCC_OPT_n[17:12] TCC | 1 to 63 |
Transfer complete code mode | EDMA.EDMA_TPCC_OPT_n[11] TCCMODE | 0x0: Normal completion |
FIFO width | EDMA.EDMA_TPCC_OPT_n[10:8] FWID | x |
Static Entry | EDMA.EDMA_TPCC_OPT_n[3] STATIC | 0x0: Entry is updated as normal. |
Transfer Synchronization Dimension | EDMA.EDMA_TPCC_OPT_n[2] SYNCDIM | 0x1 AB-Sync, Each event triggers the transfer of BCNT arrays of ACNT elements . |
Destination Address Mode | EDMA.EDMA_TPCC_OPT_n[1] DAM | 0x1: NCR, Dst addressing within an array increments. Dst is not a FIFO . |
Source Address Mode | EDMA.EDMA_TPCC_OPT_n[0] SAM | 0x0: INCR, Src addressing within an array increments. Source is not a FIFO. |
Source Address | EDMA.EDMA_TPCC_SRC_n[31:0] SRC | xxxx: VCPRDECS Decision FIFO address |
Number of Hard decision bytes in an array | EDMA.EDMA_TPCC_ABCNT_n[15:0] ACNT | 0x8, where
Equation 18. A(SYMR+1) x 8 |
Number of arrays in a frame Where TNSD is the total number of soft decisions (framelength) | EDMA.EDMA_TPCC_ABCNT_n[15:0] BCNT | Equation 19. BCNT = CEIL(TNSD/ACNT) |
Destination Address | EDMA.EDMA_TPCC_DST_n[31:0] DST | xxxx: Soft Decision Array Address |
Source 2nd Dimension Index | EDMA.EDMA_TPCC_BIDX_n[15:0] SBIDX | 0x8 (to create incrementing transfer) |
Destination 2nd Dimension Index | EDMA.EDMA_TPCC_BIDX_n[31:16] DBIDX | 0x0 (to access the FIFO) |
Source Frame Index | EDMA.EDMA_TPCC_CIDX_n[15:0] SCIDX | ACNT × BCNT |
Destination Frame Index | EDMA.EDMA_TPCC_CIDX_n[31:16] DCIDX | 0x00 (to access the FIFO) |
C byte count. Count for 3rd Dimension | EDMA.EDMA_TPCC_CCNT_n[15:0] CCNT | 0x1: One frame in the block |