SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The BB2D subsystem is part of the DSS power domain (PD_DSS). For additional information about PD_DSS, see PD_DSS Description in the Power, Reset, and Clock Management.
The BB2D handles automatic clock gating performed on the multiple internal clock domains.
When 2D operations are complete, software may set the GCGPOUT0[0] GCHOLD bit to 1 to enter a low-power state. Setting GCHOLD to 1 moves the BB2D operational state into IDLE. Once in IDLE state, the system standby hardware signal (mstandby) is asserted.