SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
An ATU outbound region can then be programmed to remap the desired parts of the memory space (which correspond to BARs on other devices) into the local controller target’s outbound window, accessed through the L3_MAIN slave port.
Alternatively, the iATU can be bypassed, and the outgoing access forwarded to the PCIe wire without address translation. In that pass-through mode, the PCIe address is equal to the 28 LSBits of the PCIe controller target address, that is, the address offset within the 256 MiB-wide outbound window. This gives access to the lowest 256 MiB of the PCIe memory space, from 0x0 to 0x0FFF_FFFC.
The forwarded PCIe TLPs shall have the following (hardcoded) header field values:
Initiators in the device local PCIe subsystem (typically CPUs or DMA) can then access memory space by initiating read/write accesses on the controller’s slave port over L3_MAIN, either to the range of an enabled ATU outbound region, for the translated mode (with all TLP fields configurable), or outside any enabled ATU outbound region, for the pass-through mode (with the TLP fields hardcoded as explained above).