SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
The functionality of all mailbox instances in the device is the same and is described in this section.
In this chapter, u is the user number and m is the mailbox number as follows:
The mailbox module provides a means of communication through message queues among the users. The individual mailbox modules, or FIFOs, can associate (or de-associate) with any of the processors using the MAILBOX_IRQENABLE_SET_u (or MAILBOX_IRQENABLE_CLR_u) register.
Table 19-11 shows the potential users of the mailbox modules in the device.
Mailbox Type | Users | |||||
---|---|---|---|---|---|---|
User 0 | User 1 | User 2 | User 3 | |||
System Mailbox | MAILBOX1 | Any of: MPU, DSP1, DSP2, IPU1, IPU2 | – | |||
MAILBOX2..13 | Any of: MPU, DSP1, DSP2, IPU1, IPU2 | |||||
IVA Mailbox | Any of: MPU, DSP1, DSP2, IPU1, IPU2 | IVA local - ICONT, or ICONT2 | ||||
EVEx Mailbox | EVEx_MBOX0, EVEx_MBOX1 | TBD | Any of: MPU, DSP1, DSP2, IPU1, IPU2 | |||
EVEx_ MBOX2 | EVE1_MBOX2 | ARP32 of EVE1 | ARP32 of EVE2 | – | ||
EVE2_MBOX2 | ARP32 of EVE2 | ARP32 of EVE1 | – |
It is software responsibility to select a user by mapping (via IRQ_CROSSBAR) the corresponding mailbox interrupt to the interrupt controller of the appropriate processor subsystem.
Each user has a dedicated interrupt signal from
the corresponding mailbox module instance and dedicated interrupt enabling and
status registers.
Each
MAILBOX_IRQSTATUS_RAW_u/MAILBOX_IRQSTATUS_CLR_u interrupt status register
corresponds to a particular user.