SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
This section describes the SATA AHCI host controller integration in the device, including information about clocks, resets, and hardware requests. Figure 24-153 shows the SATA controller integration.
SATA controller integration includes these features:
The SATA encoded symbol transmission/decoded symbol reception relies on two serial clocks , which are supplied indirectly from the DPLL_SATA through the SATA_PHY component.
For more information about the slave idle protocol and the wakeup request, see Module-Level Clock Management in Power, Reset, and Clock Management.
Table 24-440 through Table 24-442 summarize the integration of the module in the device.
Module Instance | Attributes | |
Power Domain | Interconnect | |
SATA | PD_L3INIT | L4_CFG |
L3_MAIN |
Clocks | ||||
Module Instance | Destination Signal Name | Source Signal Name | Source | Description |
SATA | SATA_FICLK | L3INIT_L3_GICLK | PRCM | SATA interface and functional clock |
SATA_PMALIVE_FCLK | L3INIT_48M_GFCLK | PRCM | Always-on SATA-specific, power-management support clock | |
Resets | ||||
Module Instance | Destination Signal Name | Source Signal Name | Source | Description |
SATA | SATA_RST_MAIN_ARST_N | L3INIT_RST | PRCM | A nonretention hardware reset |
Interrupt Requests | ||||
Module Instance | Source Signal Name | Destination IRQ_CROSSBAR Input | Default Mapping | Description |
SATA | SATA_IRQ | IRQ_CROSSBAR_49 | MPU_IRQ_54 DSP1_IRQ_80 DSP2_IRQ_80 | SATA Controller IRQ line |
The “Default Mapping” column in Table 24-442
SATA Controller Hardware Requests shows the default mapping of module IRQ
source signals. These IRQ source signals can also be mapped to other lines of
each device Interrupt controller through the IRQ_CROSSBAR module.
For more information about the IRQ_CROSSBAR
module, see IRQ_CROSSBAR Module Functional Description, in Control
Module.
For
more information about the device interrupt controllers, see Interrupt
Controllers.